|
|
reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
|
References
gen/lib/Target/ARM/ARMGenInstrInfo.inc 9572 { 3739, 6, 1, 4, 690, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef)|(1ULL<<MCID::HasPostISelHook), 0xc80ULL, ImplicitList1, ImplicitList1, OperandInfo447, -1 ,nullptr }, // Inst #3739 = t2ADCri
9580 { 3747, 6, 1, 4, 692, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0xc80ULL, nullptr, nullptr, OperandInfo447, -1 ,nullptr }, // Inst #3747 = t2ANDri
9583 { 3750, 6, 1, 4, 872, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0xc80ULL, nullptr, nullptr, OperandInfo447, -1 ,nullptr }, // Inst #3750 = t2ASRri
9593 { 3760, 6, 1, 4, 692, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0xc80ULL, nullptr, nullptr, OperandInfo447, -1 ,nullptr }, // Inst #3760 = t2BICri
9629 { 3796, 6, 1, 4, 692, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0xc80ULL, nullptr, nullptr, OperandInfo447, -1 ,nullptr }, // Inst #3796 = t2EORri
9709 { 3876, 6, 1, 4, 872, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0xc80ULL, nullptr, nullptr, OperandInfo447, -1 ,nullptr }, // Inst #3876 = t2LSLri
9711 { 3878, 6, 1, 4, 872, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0xc80ULL, nullptr, nullptr, OperandInfo447, -1 ,nullptr }, // Inst #3878 = t2LSRri
9740 { 3907, 6, 1, 4, 42, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0xc80ULL, nullptr, nullptr, OperandInfo447, -1 ,nullptr }, // Inst #3907 = t2ORNri
9743 { 3910, 6, 1, 4, 692, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0xc80ULL, nullptr, nullptr, OperandInfo447, -1 ,nullptr }, // Inst #3910 = t2ORRri
9777 { 3944, 6, 1, 4, 872, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0xc80ULL, nullptr, nullptr, OperandInfo447, -1 ,nullptr }, // Inst #3944 = t2RORri
9780 { 3947, 6, 1, 4, 690, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0xc80ULL, nullptr, nullptr, OperandInfo447, -1 ,nullptr }, // Inst #3947 = t2RSBri
9787 { 3954, 6, 1, 4, 690, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef)|(1ULL<<MCID::HasPostISelHook), 0xc80ULL, ImplicitList1, ImplicitList1, OperandInfo447, -1 ,nullptr }, // Inst #3954 = t2SBCri