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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/ARM/ARMGenInstrInfo.inc 9250 { 3417, 7, 1, 4, 1041, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo421, -1 ,nullptr }, // Inst #3417 = VST1q16LowQPseudo_UPD
9251 { 3418, 7, 1, 4, 1040, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo421, -1 ,nullptr }, // Inst #3418 = VST1q16LowTPseudo_UPD
9257 { 3424, 7, 1, 4, 1041, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo421, -1 ,nullptr }, // Inst #3424 = VST1q32LowQPseudo_UPD
9258 { 3425, 7, 1, 4, 1040, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo421, -1 ,nullptr }, // Inst #3425 = VST1q32LowTPseudo_UPD
9264 { 3431, 7, 1, 4, 1041, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo421, -1 ,nullptr }, // Inst #3431 = VST1q64LowQPseudo_UPD
9265 { 3432, 7, 1, 4, 1040, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo421, -1 ,nullptr }, // Inst #3432 = VST1q64LowTPseudo_UPD
9271 { 3438, 7, 1, 4, 1041, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo421, -1 ,nullptr }, // Inst #3438 = VST1q8LowQPseudo_UPD
9272 { 3439, 7, 1, 4, 1040, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo421, -1 ,nullptr }, // Inst #3439 = VST1q8LowTPseudo_UPD
9364 { 3531, 7, 1, 4, 657, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo421, -1 ,nullptr }, // Inst #3531 = VST3q16Pseudo_UPD
9367 { 3534, 7, 1, 4, 657, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo421, -1 ,nullptr }, // Inst #3534 = VST3q16oddPseudo_UPD
9369 { 3536, 7, 1, 4, 657, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo421, -1 ,nullptr }, // Inst #3536 = VST3q32Pseudo_UPD
9372 { 3539, 7, 1, 4, 657, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo421, -1 ,nullptr }, // Inst #3539 = VST3q32oddPseudo_UPD
9374 { 3541, 7, 1, 4, 657, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo421, -1 ,nullptr }, // Inst #3541 = VST3q8Pseudo_UPD
9377 { 3544, 7, 1, 4, 657, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo421, -1 ,nullptr }, // Inst #3544 = VST3q8oddPseudo_UPD
9411 { 3578, 7, 1, 4, 659, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo421, -1 ,nullptr }, // Inst #3578 = VST4q16Pseudo_UPD
9414 { 3581, 7, 1, 4, 659, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo421, -1 ,nullptr }, // Inst #3581 = VST4q16oddPseudo_UPD
9416 { 3583, 7, 1, 4, 659, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo421, -1 ,nullptr }, // Inst #3583 = VST4q32Pseudo_UPD
9419 { 3586, 7, 1, 4, 659, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo421, -1 ,nullptr }, // Inst #3586 = VST4q32oddPseudo_UPD
9421 { 3588, 7, 1, 4, 659, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo421, -1 ,nullptr }, // Inst #3588 = VST4q8Pseudo_UPD
9424 { 3591, 7, 1, 4, 659, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo421, -1 ,nullptr }, // Inst #3591 = VST4q8oddPseudo_UPD