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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/ARM/ARMGenInstrInfo.inc 9248 { 3415, 5, 0, 4, 1041, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo420, -1 ,nullptr }, // Inst #3415 = VST1q16HighQPseudo
9249 { 3416, 5, 0, 4, 1040, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo420, -1 ,nullptr }, // Inst #3416 = VST1q16HighTPseudo
9255 { 3422, 5, 0, 4, 1041, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo420, -1 ,nullptr }, // Inst #3422 = VST1q32HighQPseudo
9256 { 3423, 5, 0, 4, 1040, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo420, -1 ,nullptr }, // Inst #3423 = VST1q32HighTPseudo
9262 { 3429, 5, 0, 4, 1041, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo420, -1 ,nullptr }, // Inst #3429 = VST1q64HighQPseudo
9263 { 3430, 5, 0, 4, 1040, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo420, -1 ,nullptr }, // Inst #3430 = VST1q64HighTPseudo
9269 { 3436, 5, 0, 4, 1041, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo420, -1 ,nullptr }, // Inst #3436 = VST1q8HighQPseudo
9270 { 3437, 5, 0, 4, 1040, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo420, -1 ,nullptr }, // Inst #3437 = VST1q8HighTPseudo
9366 { 3533, 5, 0, 4, 656, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo420, -1 ,nullptr }, // Inst #3533 = VST3q16oddPseudo
9371 { 3538, 5, 0, 4, 656, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo420, -1 ,nullptr }, // Inst #3538 = VST3q32oddPseudo
9376 { 3543, 5, 0, 4, 656, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo420, -1 ,nullptr }, // Inst #3543 = VST3q8oddPseudo
9413 { 3580, 5, 0, 4, 658, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo420, -1 ,nullptr }, // Inst #3580 = VST4q16oddPseudo
9418 { 3585, 5, 0, 4, 658, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo420, -1 ,nullptr }, // Inst #3585 = VST4q32oddPseudo
9423 { 3590, 5, 0, 4, 658, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo420, -1 ,nullptr }, // Inst #3590 = VST4q8oddPseudo