|
|
reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
|
References
gen/lib/Target/ARM/ARMGenInstrInfo.inc 9052 { 3219, 6, 1, 4, 479, 0|(1ULL<<MCID::Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo399, -1 ,nullptr }, // Inst #3219 = VRSRAsv1i64
9053 { 3220, 6, 1, 4, 479, 0|(1ULL<<MCID::Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo399, -1 ,nullptr }, // Inst #3220 = VRSRAsv2i32
9055 { 3222, 6, 1, 4, 479, 0|(1ULL<<MCID::Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo399, -1 ,nullptr }, // Inst #3222 = VRSRAsv4i16
9058 { 3225, 6, 1, 4, 479, 0|(1ULL<<MCID::Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo399, -1 ,nullptr }, // Inst #3225 = VRSRAsv8i8
9060 { 3227, 6, 1, 4, 479, 0|(1ULL<<MCID::Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo399, -1 ,nullptr }, // Inst #3227 = VRSRAuv1i64
9061 { 3228, 6, 1, 4, 479, 0|(1ULL<<MCID::Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo399, -1 ,nullptr }, // Inst #3228 = VRSRAuv2i32
9063 { 3230, 6, 1, 4, 479, 0|(1ULL<<MCID::Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo399, -1 ,nullptr }, // Inst #3230 = VRSRAuv4i16
9066 { 3233, 6, 1, 4, 479, 0|(1ULL<<MCID::Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo399, -1 ,nullptr }, // Inst #3233 = VRSRAuv8i8
9164 { 3331, 6, 1, 4, 479, 0|(1ULL<<MCID::Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo399, -1 ,nullptr }, // Inst #3331 = VSRAsv1i64
9165 { 3332, 6, 1, 4, 479, 0|(1ULL<<MCID::Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo399, -1 ,nullptr }, // Inst #3332 = VSRAsv2i32
9167 { 3334, 6, 1, 4, 479, 0|(1ULL<<MCID::Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo399, -1 ,nullptr }, // Inst #3334 = VSRAsv4i16
9170 { 3337, 6, 1, 4, 479, 0|(1ULL<<MCID::Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo399, -1 ,nullptr }, // Inst #3337 = VSRAsv8i8
9172 { 3339, 6, 1, 4, 479, 0|(1ULL<<MCID::Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo399, -1 ,nullptr }, // Inst #3339 = VSRAuv1i64
9173 { 3340, 6, 1, 4, 479, 0|(1ULL<<MCID::Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo399, -1 ,nullptr }, // Inst #3340 = VSRAuv2i32
9175 { 3342, 6, 1, 4, 479, 0|(1ULL<<MCID::Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo399, -1 ,nullptr }, // Inst #3342 = VSRAuv4i16
9178 { 3345, 6, 1, 4, 479, 0|(1ULL<<MCID::Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo399, -1 ,nullptr }, // Inst #3345 = VSRAuv8i8
9180 { 3347, 6, 1, 4, 980, 0|(1ULL<<MCID::Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo399, -1 ,nullptr }, // Inst #3347 = VSRIv1i64
9181 { 3348, 6, 1, 4, 980, 0|(1ULL<<MCID::Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo399, -1 ,nullptr }, // Inst #3348 = VSRIv2i32
9183 { 3350, 6, 1, 4, 980, 0|(1ULL<<MCID::Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo399, -1 ,nullptr }, // Inst #3350 = VSRIv4i16
9186 { 3353, 6, 1, 4, 980, 0|(1ULL<<MCID::Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo399, -1 ,nullptr }, // Inst #3353 = VSRIv8i8