|
|
reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
|
References
gen/lib/Target/ARM/ARMGenInstrInfo.inc 9051 { 3218, 6, 1, 4, 479, 0|(1ULL<<MCID::Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo398, -1 ,nullptr }, // Inst #3218 = VRSRAsv16i8
9054 { 3221, 6, 1, 4, 479, 0|(1ULL<<MCID::Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo398, -1 ,nullptr }, // Inst #3221 = VRSRAsv2i64
9056 { 3223, 6, 1, 4, 479, 0|(1ULL<<MCID::Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo398, -1 ,nullptr }, // Inst #3223 = VRSRAsv4i32
9057 { 3224, 6, 1, 4, 479, 0|(1ULL<<MCID::Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo398, -1 ,nullptr }, // Inst #3224 = VRSRAsv8i16
9059 { 3226, 6, 1, 4, 479, 0|(1ULL<<MCID::Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo398, -1 ,nullptr }, // Inst #3226 = VRSRAuv16i8
9062 { 3229, 6, 1, 4, 479, 0|(1ULL<<MCID::Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo398, -1 ,nullptr }, // Inst #3229 = VRSRAuv2i64
9064 { 3231, 6, 1, 4, 479, 0|(1ULL<<MCID::Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo398, -1 ,nullptr }, // Inst #3231 = VRSRAuv4i32
9065 { 3232, 6, 1, 4, 479, 0|(1ULL<<MCID::Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo398, -1 ,nullptr }, // Inst #3232 = VRSRAuv8i16
9163 { 3330, 6, 1, 4, 479, 0|(1ULL<<MCID::Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo398, -1 ,nullptr }, // Inst #3330 = VSRAsv16i8
9166 { 3333, 6, 1, 4, 479, 0|(1ULL<<MCID::Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo398, -1 ,nullptr }, // Inst #3333 = VSRAsv2i64
9168 { 3335, 6, 1, 4, 479, 0|(1ULL<<MCID::Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo398, -1 ,nullptr }, // Inst #3335 = VSRAsv4i32
9169 { 3336, 6, 1, 4, 479, 0|(1ULL<<MCID::Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo398, -1 ,nullptr }, // Inst #3336 = VSRAsv8i16
9171 { 3338, 6, 1, 4, 479, 0|(1ULL<<MCID::Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo398, -1 ,nullptr }, // Inst #3338 = VSRAuv16i8
9174 { 3341, 6, 1, 4, 479, 0|(1ULL<<MCID::Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo398, -1 ,nullptr }, // Inst #3341 = VSRAuv2i64
9176 { 3343, 6, 1, 4, 479, 0|(1ULL<<MCID::Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo398, -1 ,nullptr }, // Inst #3343 = VSRAuv4i32
9177 { 3344, 6, 1, 4, 479, 0|(1ULL<<MCID::Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo398, -1 ,nullptr }, // Inst #3344 = VSRAuv8i16
9179 { 3346, 6, 1, 4, 981, 0|(1ULL<<MCID::Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo398, -1 ,nullptr }, // Inst #3346 = VSRIv16i8
9182 { 3349, 6, 1, 4, 981, 0|(1ULL<<MCID::Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo398, -1 ,nullptr }, // Inst #3349 = VSRIv2i64
9184 { 3351, 6, 1, 4, 981, 0|(1ULL<<MCID::Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo398, -1 ,nullptr }, // Inst #3351 = VSRIv4i32
9185 { 3352, 6, 1, 4, 981, 0|(1ULL<<MCID::Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo398, -1 ,nullptr }, // Inst #3352 = VSRIv8i16