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|
reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
|
References
gen/lib/Target/ARM/ARMGenInstrInfo.inc 8850 { 3017, 5, 1, 4, 500, 0|(1ULL<<MCID::Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo394, -1 ,nullptr }, // Inst #3017 = VQRSHRNsv2i32
8851 { 3018, 5, 1, 4, 500, 0|(1ULL<<MCID::Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo394, -1 ,nullptr }, // Inst #3018 = VQRSHRNsv4i16
8852 { 3019, 5, 1, 4, 500, 0|(1ULL<<MCID::Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo394, -1 ,nullptr }, // Inst #3019 = VQRSHRNsv8i8
8853 { 3020, 5, 1, 4, 500, 0|(1ULL<<MCID::Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo394, -1 ,nullptr }, // Inst #3020 = VQRSHRNuv2i32
8854 { 3021, 5, 1, 4, 500, 0|(1ULL<<MCID::Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo394, -1 ,nullptr }, // Inst #3021 = VQRSHRNuv4i16
8855 { 3022, 5, 1, 4, 500, 0|(1ULL<<MCID::Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo394, -1 ,nullptr }, // Inst #3022 = VQRSHRNuv8i8
8856 { 3023, 5, 1, 4, 500, 0|(1ULL<<MCID::Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo394, -1 ,nullptr }, // Inst #3023 = VQRSHRUNv2i32
8857 { 3024, 5, 1, 4, 500, 0|(1ULL<<MCID::Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo394, -1 ,nullptr }, // Inst #3024 = VQRSHRUNv4i16
8858 { 3025, 5, 1, 4, 500, 0|(1ULL<<MCID::Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo394, -1 ,nullptr }, // Inst #3025 = VQRSHRUNv8i8
8899 { 3066, 5, 1, 4, 793, 0|(1ULL<<MCID::Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo394, -1 ,nullptr }, // Inst #3066 = VQSHRNsv2i32
8900 { 3067, 5, 1, 4, 793, 0|(1ULL<<MCID::Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo394, -1 ,nullptr }, // Inst #3067 = VQSHRNsv4i16
8901 { 3068, 5, 1, 4, 793, 0|(1ULL<<MCID::Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo394, -1 ,nullptr }, // Inst #3068 = VQSHRNsv8i8
8902 { 3069, 5, 1, 4, 793, 0|(1ULL<<MCID::Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo394, -1 ,nullptr }, // Inst #3069 = VQSHRNuv2i32
8903 { 3070, 5, 1, 4, 793, 0|(1ULL<<MCID::Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo394, -1 ,nullptr }, // Inst #3070 = VQSHRNuv4i16
8904 { 3071, 5, 1, 4, 793, 0|(1ULL<<MCID::Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo394, -1 ,nullptr }, // Inst #3071 = VQSHRNuv8i8
8905 { 3072, 5, 1, 4, 500, 0|(1ULL<<MCID::Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo394, -1 ,nullptr }, // Inst #3072 = VQSHRUNv2i32
8906 { 3073, 5, 1, 4, 500, 0|(1ULL<<MCID::Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo394, -1 ,nullptr }, // Inst #3073 = VQSHRUNv4i16
8907 { 3074, 5, 1, 4, 500, 0|(1ULL<<MCID::Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo394, -1 ,nullptr }, // Inst #3074 = VQSHRUNv8i8
9022 { 3189, 5, 1, 4, 796, 0|(1ULL<<MCID::Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo394, -1 ,nullptr }, // Inst #3189 = VRSHRNv2i32
9023 { 3190, 5, 1, 4, 796, 0|(1ULL<<MCID::Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo394, -1 ,nullptr }, // Inst #3190 = VRSHRNv4i16
9024 { 3191, 5, 1, 4, 796, 0|(1ULL<<MCID::Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo394, -1 ,nullptr }, // Inst #3191 = VRSHRNv8i8
9124 { 3291, 5, 1, 4, 498, 0|(1ULL<<MCID::Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo394, -1 ,nullptr }, // Inst #3291 = VSHRNv2i32
9125 { 3292, 5, 1, 4, 498, 0|(1ULL<<MCID::Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo394, -1 ,nullptr }, // Inst #3292 = VSHRNv4i16
9126 { 3293, 5, 1, 4, 498, 0|(1ULL<<MCID::Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo394, -1 ,nullptr }, // Inst #3293 = VSHRNv8i8