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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/ARM/ARMGenInstrInfo.inc 6009 { 176, 5, 1, 4, 697, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Add)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook), 0x0ULL, nullptr, ImplicitList1, OperandInfo38, -1 ,nullptr }, // Inst #176 = ADDSrr
6115 { 282, 5, 1, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasPostISelHook), 0x0ULL, nullptr, ImplicitList1, OperandInfo38, -1 ,nullptr }, // Inst #282 = SUBSrr
7521 { 1688, 5, 1, 4, 384, 0|(1ULL<<MCID::Predicable), 0x600ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr }, // Inst #1688 = SDIV
7522 { 1689, 5, 1, 4, 334, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0x200ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr }, // Inst #1689 = SEL
7565 { 1732, 5, 1, 4, 336, 0|(1ULL<<MCID::Predicable), 0x80ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr }, // Inst #1732 = SMMUL
7566 { 1733, 5, 1, 4, 336, 0|(1ULL<<MCID::Predicable), 0x80ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr }, // Inst #1733 = SMMULR
7569 { 1736, 5, 1, 4, 345, 0|(1ULL<<MCID::Predicable), 0x80ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr }, // Inst #1736 = SMULBB
7570 { 1737, 5, 1, 4, 345, 0|(1ULL<<MCID::Predicable), 0x80ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr }, // Inst #1737 = SMULBT
7572 { 1739, 5, 1, 4, 345, 0|(1ULL<<MCID::Predicable), 0x80ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr }, // Inst #1739 = SMULTB
7573 { 1740, 5, 1, 4, 345, 0|(1ULL<<MCID::Predicable), 0x80ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr }, // Inst #1740 = SMULTT
7574 { 1741, 5, 1, 4, 345, 0|(1ULL<<MCID::Predicable), 0x80ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr }, // Inst #1741 = SMULWB
7575 { 1742, 5, 1, 4, 345, 0|(1ULL<<MCID::Predicable), 0x80ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr }, // Inst #1742 = SMULWT
7679 { 1846, 5, 1, 4, 384, 0|(1ULL<<MCID::Predicable), 0x600ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr }, // Inst #1846 = UDIV
7695 { 1862, 5, 1, 4, 369, 0|(1ULL<<MCID::Predicable), 0x80ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr }, // Inst #1862 = USAD8
9792 { 3959, 5, 1, 4, 357, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr }, // Inst #3959 = t2SEL