|
|
reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
|
References
gen/lib/Target/ARM/ARMGenInstrInfo.inc 8392 { 2559, 10, 5, 4, 636, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo358, -1 ,nullptr }, // Inst #2559 = VLD4DUPd16_UPD
8396 { 2563, 10, 5, 4, 636, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo358, -1 ,nullptr }, // Inst #2563 = VLD4DUPd32_UPD
8400 { 2567, 10, 5, 4, 636, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo358, -1 ,nullptr }, // Inst #2567 = VLD4DUPd8_UPD
8404 { 2571, 10, 5, 4, 636, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo358, -1 ,nullptr }, // Inst #2571 = VLD4DUPq16_UPD
8408 { 2575, 10, 5, 4, 636, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo358, -1 ,nullptr }, // Inst #2575 = VLD4DUPq32_UPD
8412 { 2579, 10, 5, 4, 636, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo358, -1 ,nullptr }, // Inst #2579 = VLD4DUPq8_UPD
8436 { 2603, 10, 5, 4, 613, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo358, -1 ,nullptr }, // Inst #2603 = VLD4d16_UPD
8440 { 2607, 10, 5, 4, 613, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo358, -1 ,nullptr }, // Inst #2607 = VLD4d32_UPD
8444 { 2611, 10, 5, 4, 613, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo358, -1 ,nullptr }, // Inst #2611 = VLD4d8_UPD
8447 { 2614, 10, 5, 4, 613, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo358, -1 ,nullptr }, // Inst #2614 = VLD4q16_UPD
8452 { 2619, 10, 5, 4, 613, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo358, -1 ,nullptr }, // Inst #2619 = VLD4q32_UPD
8457 { 2624, 10, 5, 4, 613, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo358, -1 ,nullptr }, // Inst #2624 = VLD4q8_UPD