|
|
reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
|
References
gen/lib/Target/ARM/ARMGenInstrInfo.inc 8320 { 2487, 7, 2, 4, 631, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo351, -1 ,nullptr }, // Inst #2487 = VLD3DUPd16Pseudo_UPD
8324 { 2491, 7, 2, 4, 631, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo351, -1 ,nullptr }, // Inst #2491 = VLD3DUPd32Pseudo_UPD
8328 { 2495, 7, 2, 4, 631, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo351, -1 ,nullptr }, // Inst #2495 = VLD3DUPd8Pseudo_UPD
8364 { 2531, 7, 2, 4, 610, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo351, -1 ,nullptr }, // Inst #2531 = VLD3d16Pseudo_UPD
8368 { 2535, 7, 2, 4, 610, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo351, -1 ,nullptr }, // Inst #2535 = VLD3d32Pseudo_UPD
8372 { 2539, 7, 2, 4, 610, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo351, -1 ,nullptr }, // Inst #2539 = VLD3d8Pseudo_UPD
8391 { 2558, 7, 2, 4, 638, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo351, -1 ,nullptr }, // Inst #2558 = VLD4DUPd16Pseudo_UPD
8395 { 2562, 7, 2, 4, 638, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo351, -1 ,nullptr }, // Inst #2562 = VLD4DUPd32Pseudo_UPD
8399 { 2566, 7, 2, 4, 638, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo351, -1 ,nullptr }, // Inst #2566 = VLD4DUPd8Pseudo_UPD
8435 { 2602, 7, 2, 4, 614, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo351, -1 ,nullptr }, // Inst #2602 = VLD4d16Pseudo_UPD
8439 { 2606, 7, 2, 4, 614, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo351, -1 ,nullptr }, // Inst #2606 = VLD4d32Pseudo_UPD
8443 { 2610, 7, 2, 4, 614, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo351, -1 ,nullptr }, // Inst #2610 = VLD4d8Pseudo_UPD