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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/ARM/ARMGenInstrInfo.inc 8213 { 2380, 8, 2, 4, 1035, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo342, -1 ,nullptr }, // Inst #2380 = VLD1q16LowQPseudo_UPD
8214 { 2381, 8, 2, 4, 1036, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo342, -1 ,nullptr }, // Inst #2381 = VLD1q16LowTPseudo_UPD
8220 { 2387, 8, 2, 4, 1035, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo342, -1 ,nullptr }, // Inst #2387 = VLD1q32LowQPseudo_UPD
8221 { 2388, 8, 2, 4, 1036, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo342, -1 ,nullptr }, // Inst #2388 = VLD1q32LowTPseudo_UPD
8227 { 2394, 8, 2, 4, 1035, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo342, -1 ,nullptr }, // Inst #2394 = VLD1q64LowQPseudo_UPD
8228 { 2395, 8, 2, 4, 1036, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo342, -1 ,nullptr }, // Inst #2395 = VLD1q64LowTPseudo_UPD
8234 { 2401, 8, 2, 4, 1035, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo342, -1 ,nullptr }, // Inst #2401 = VLD1q8LowQPseudo_UPD
8235 { 2402, 8, 2, 4, 1036, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo342, -1 ,nullptr }, // Inst #2402 = VLD1q8LowTPseudo_UPD
8375 { 2542, 8, 2, 4, 610, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo342, -1 ,nullptr }, // Inst #2542 = VLD3q16Pseudo_UPD
8378 { 2545, 8, 2, 4, 610, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo342, -1 ,nullptr }, // Inst #2545 = VLD3q16oddPseudo_UPD
8380 { 2547, 8, 2, 4, 610, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo342, -1 ,nullptr }, // Inst #2547 = VLD3q32Pseudo_UPD
8383 { 2550, 8, 2, 4, 610, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo342, -1 ,nullptr }, // Inst #2550 = VLD3q32oddPseudo_UPD
8385 { 2552, 8, 2, 4, 610, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo342, -1 ,nullptr }, // Inst #2552 = VLD3q8Pseudo_UPD
8388 { 2555, 8, 2, 4, 610, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo342, -1 ,nullptr }, // Inst #2555 = VLD3q8oddPseudo_UPD
8446 { 2613, 8, 2, 4, 614, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo342, -1 ,nullptr }, // Inst #2613 = VLD4q16Pseudo_UPD
8449 { 2616, 8, 2, 4, 614, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo342, -1 ,nullptr }, // Inst #2616 = VLD4q16oddPseudo_UPD
8451 { 2618, 8, 2, 4, 614, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo342, -1 ,nullptr }, // Inst #2618 = VLD4q32Pseudo_UPD
8454 { 2621, 8, 2, 4, 614, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo342, -1 ,nullptr }, // Inst #2621 = VLD4q32oddPseudo_UPD
8456 { 2623, 8, 2, 4, 614, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo342, -1 ,nullptr }, // Inst #2623 = VLD4q8Pseudo_UPD
8459 { 2626, 8, 2, 4, 614, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo342, -1 ,nullptr }, // Inst #2626 = VLD4q8oddPseudo_UPD