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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/ARM/ARMGenInstrInfo.inc 8211 { 2378, 6, 1, 4, 1035, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo341, -1 ,nullptr }, // Inst #2378 = VLD1q16HighQPseudo
8212 { 2379, 6, 1, 4, 1036, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo341, -1 ,nullptr }, // Inst #2379 = VLD1q16HighTPseudo
8218 { 2385, 6, 1, 4, 1035, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo341, -1 ,nullptr }, // Inst #2385 = VLD1q32HighQPseudo
8219 { 2386, 6, 1, 4, 1036, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo341, -1 ,nullptr }, // Inst #2386 = VLD1q32HighTPseudo
8225 { 2392, 6, 1, 4, 1035, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo341, -1 ,nullptr }, // Inst #2392 = VLD1q64HighQPseudo
8226 { 2393, 6, 1, 4, 1036, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo341, -1 ,nullptr }, // Inst #2393 = VLD1q64HighTPseudo
8232 { 2399, 6, 1, 4, 1035, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo341, -1 ,nullptr }, // Inst #2399 = VLD1q8HighQPseudo
8233 { 2400, 6, 1, 4, 1036, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo341, -1 ,nullptr }, // Inst #2400 = VLD1q8HighTPseudo
8331 { 2498, 6, 1, 4, 1038, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo341, -1 ,nullptr }, // Inst #2498 = VLD3DUPq16EvenPseudo
8332 { 2499, 6, 1, 4, 1038, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo341, -1 ,nullptr }, // Inst #2499 = VLD3DUPq16OddPseudo
8335 { 2502, 6, 1, 4, 1038, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo341, -1 ,nullptr }, // Inst #2502 = VLD3DUPq32EvenPseudo
8336 { 2503, 6, 1, 4, 1038, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo341, -1 ,nullptr }, // Inst #2503 = VLD3DUPq32OddPseudo
8339 { 2506, 6, 1, 4, 1038, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo341, -1 ,nullptr }, // Inst #2506 = VLD3DUPq8EvenPseudo
8340 { 2507, 6, 1, 4, 1038, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo341, -1 ,nullptr }, // Inst #2507 = VLD3DUPq8OddPseudo
8377 { 2544, 6, 1, 4, 608, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo341, -1 ,nullptr }, // Inst #2544 = VLD3q16oddPseudo
8382 { 2549, 6, 1, 4, 608, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo341, -1 ,nullptr }, // Inst #2549 = VLD3q32oddPseudo
8387 { 2554, 6, 1, 4, 608, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo341, -1 ,nullptr }, // Inst #2554 = VLD3q8oddPseudo
8402 { 2569, 6, 1, 4, 1039, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo341, -1 ,nullptr }, // Inst #2569 = VLD4DUPq16EvenPseudo
8403 { 2570, 6, 1, 4, 1039, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo341, -1 ,nullptr }, // Inst #2570 = VLD4DUPq16OddPseudo
8406 { 2573, 6, 1, 4, 1039, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo341, -1 ,nullptr }, // Inst #2573 = VLD4DUPq32EvenPseudo
8407 { 2574, 6, 1, 4, 1039, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo341, -1 ,nullptr }, // Inst #2574 = VLD4DUPq32OddPseudo
8410 { 2577, 6, 1, 4, 1039, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo341, -1 ,nullptr }, // Inst #2577 = VLD4DUPq8EvenPseudo
8411 { 2578, 6, 1, 4, 1039, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo341, -1 ,nullptr }, // Inst #2578 = VLD4DUPq8OddPseudo
8448 { 2615, 6, 1, 4, 612, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo341, -1 ,nullptr }, // Inst #2615 = VLD4q16oddPseudo
8453 { 2620, 6, 1, 4, 612, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo341, -1 ,nullptr }, // Inst #2620 = VLD4q32oddPseudo
8458 { 2625, 6, 1, 4, 612, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo341, -1 ,nullptr }, // Inst #2625 = VLD4q8oddPseudo