reference, declarationdefinition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced

References

gen/lib/Target/ARM/ARMGenInstrInfo.inc
 8188   { 2355,	7,	2,	4,	601,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo340, -1 ,nullptr },  // Inst #2355 = VLD1d64QPseudoWB_register
 8194   { 2361,	7,	2,	4,	599,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo340, -1 ,nullptr },  // Inst #2361 = VLD1d64TPseudoWB_register
 8303   { 2470,	7,	2,	4,	606,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo340, -1 ,nullptr },  // Inst #2470 = VLD2q16PseudoWB_register
 8309   { 2476,	7,	2,	4,	606,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo340, -1 ,nullptr },  // Inst #2476 = VLD2q32PseudoWB_register
 8315   { 2482,	7,	2,	4,	606,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo340, -1 ,nullptr },  // Inst #2482 = VLD2q8PseudoWB_register