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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/ARM/ARMGenInstrInfo.inc 8164 { 2331, 5, 1, 4, 1035, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo338, -1 ,nullptr }, // Inst #2331 = VLD1d16QPseudo
8168 { 2335, 5, 1, 4, 1036, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo338, -1 ,nullptr }, // Inst #2335 = VLD1d16TPseudo
8175 { 2342, 5, 1, 4, 1035, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo338, -1 ,nullptr }, // Inst #2342 = VLD1d32QPseudo
8179 { 2346, 5, 1, 4, 1036, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo338, -1 ,nullptr }, // Inst #2346 = VLD1d32TPseudo
8186 { 2353, 5, 1, 4, 601, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo338, -1 ,nullptr }, // Inst #2353 = VLD1d64QPseudo
8192 { 2359, 5, 1, 4, 599, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo338, -1 ,nullptr }, // Inst #2359 = VLD1d64TPseudo
8201 { 2368, 5, 1, 4, 1035, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo338, -1 ,nullptr }, // Inst #2368 = VLD1d8QPseudo
8205 { 2372, 5, 1, 4, 1036, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo338, -1 ,nullptr }, // Inst #2372 = VLD1d8TPseudo
8256 { 2423, 5, 1, 4, 1037, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo338, -1 ,nullptr }, // Inst #2423 = VLD2DUPq16EvenPseudo
8257 { 2424, 5, 1, 4, 1037, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo338, -1 ,nullptr }, // Inst #2424 = VLD2DUPq16OddPseudo
8258 { 2425, 5, 1, 4, 1037, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo338, -1 ,nullptr }, // Inst #2425 = VLD2DUPq32EvenPseudo
8259 { 2426, 5, 1, 4, 1037, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo338, -1 ,nullptr }, // Inst #2426 = VLD2DUPq32OddPseudo
8260 { 2427, 5, 1, 4, 1037, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo338, -1 ,nullptr }, // Inst #2427 = VLD2DUPq8EvenPseudo
8261 { 2428, 5, 1, 4, 1037, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo338, -1 ,nullptr }, // Inst #2428 = VLD2DUPq8OddPseudo
8301 { 2468, 5, 1, 4, 604, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo338, -1 ,nullptr }, // Inst #2468 = VLD2q16Pseudo
8307 { 2474, 5, 1, 4, 604, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo338, -1 ,nullptr }, // Inst #2474 = VLD2q32Pseudo
8313 { 2480, 5, 1, 4, 604, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo338, -1 ,nullptr }, // Inst #2480 = VLD2q8Pseudo
8319 { 2486, 5, 1, 4, 627, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo338, -1 ,nullptr }, // Inst #2486 = VLD3DUPd16Pseudo
8323 { 2490, 5, 1, 4, 627, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo338, -1 ,nullptr }, // Inst #2490 = VLD3DUPd32Pseudo
8327 { 2494, 5, 1, 4, 627, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo338, -1 ,nullptr }, // Inst #2494 = VLD3DUPd8Pseudo
8363 { 2530, 5, 1, 4, 608, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo338, -1 ,nullptr }, // Inst #2530 = VLD3d16Pseudo
8367 { 2534, 5, 1, 4, 608, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo338, -1 ,nullptr }, // Inst #2534 = VLD3d32Pseudo
8371 { 2538, 5, 1, 4, 608, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo338, -1 ,nullptr }, // Inst #2538 = VLD3d8Pseudo
8390 { 2557, 5, 1, 4, 635, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo338, -1 ,nullptr }, // Inst #2557 = VLD4DUPd16Pseudo
8394 { 2561, 5, 1, 4, 635, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo338, -1 ,nullptr }, // Inst #2561 = VLD4DUPd32Pseudo
8398 { 2565, 5, 1, 4, 635, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo338, -1 ,nullptr }, // Inst #2565 = VLD4DUPd8Pseudo
8434 { 2601, 5, 1, 4, 612, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo338, -1 ,nullptr }, // Inst #2601 = VLD4d16Pseudo
8438 { 2605, 5, 1, 4, 612, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo338, -1 ,nullptr }, // Inst #2605 = VLD4d32Pseudo
8442 { 2609, 5, 1, 4, 612, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo338, -1 ,nullptr }, // Inst #2609 = VLD4d8Pseudo