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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/ARM/ARMGenInstrInfo.inc 8142 { 2309, 6, 2, 4, 620, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo332, -1 ,nullptr }, // Inst #2309 = VLD1DUPq16wb_fixed
8145 { 2312, 6, 2, 4, 620, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo332, -1 ,nullptr }, // Inst #2312 = VLD1DUPq32wb_fixed
8148 { 2315, 6, 2, 4, 620, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo332, -1 ,nullptr }, // Inst #2315 = VLD1DUPq8wb_fixed
8215 { 2382, 6, 2, 4, 598, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo332, -1 ,nullptr }, // Inst #2382 = VLD1q16wb_fixed
8222 { 2389, 6, 2, 4, 598, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo332, -1 ,nullptr }, // Inst #2389 = VLD1q32wb_fixed
8229 { 2396, 6, 2, 4, 598, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo332, -1 ,nullptr }, // Inst #2396 = VLD1q64wb_fixed
8236 { 2403, 6, 2, 4, 598, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo332, -1 ,nullptr }, // Inst #2403 = VLD1q8wb_fixed
8239 { 2406, 6, 2, 4, 625, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo332, -1 ,nullptr }, // Inst #2406 = VLD2DUPd16wb_fixed
8245 { 2412, 6, 2, 4, 625, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo332, -1 ,nullptr }, // Inst #2412 = VLD2DUPd32wb_fixed
8251 { 2418, 6, 2, 4, 625, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo332, -1 ,nullptr }, // Inst #2418 = VLD2DUPd8wb_fixed
8283 { 2450, 6, 2, 4, 605, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo332, -1 ,nullptr }, // Inst #2450 = VLD2b16wb_fixed
8286 { 2453, 6, 2, 4, 605, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo332, -1 ,nullptr }, // Inst #2453 = VLD2b32wb_fixed
8289 { 2456, 6, 2, 4, 605, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo332, -1 ,nullptr }, // Inst #2456 = VLD2b8wb_fixed
8292 { 2459, 6, 2, 4, 994, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo332, -1 ,nullptr }, // Inst #2459 = VLD2d16wb_fixed
8295 { 2462, 6, 2, 4, 994, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo332, -1 ,nullptr }, // Inst #2462 = VLD2d32wb_fixed
8298 { 2465, 6, 2, 4, 994, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo332, -1 ,nullptr }, // Inst #2465 = VLD2d8wb_fixed