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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/ARM/ARMGenInstrInfo.inc 8141 { 2308, 5, 1, 4, 616, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0x10f06ULL, nullptr, nullptr, OperandInfo331, -1 ,nullptr }, // Inst #2308 = VLD1DUPq16
8144 { 2311, 5, 1, 4, 616, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0x10f06ULL, nullptr, nullptr, OperandInfo331, -1 ,nullptr }, // Inst #2311 = VLD1DUPq32
8147 { 2314, 5, 1, 4, 616, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0x10f06ULL, nullptr, nullptr, OperandInfo331, -1 ,nullptr }, // Inst #2314 = VLD1DUPq8
8210 { 2377, 5, 1, 4, 596, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo331, -1 ,nullptr }, // Inst #2377 = VLD1q16
8217 { 2384, 5, 1, 4, 596, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo331, -1 ,nullptr }, // Inst #2384 = VLD1q32
8224 { 2391, 5, 1, 4, 596, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo331, -1 ,nullptr }, // Inst #2391 = VLD1q64
8231 { 2398, 5, 1, 4, 596, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo331, -1 ,nullptr }, // Inst #2398 = VLD1q8
8238 { 2405, 5, 1, 4, 622, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo331, -1 ,nullptr }, // Inst #2405 = VLD2DUPd16
8244 { 2411, 5, 1, 4, 622, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo331, -1 ,nullptr }, // Inst #2411 = VLD2DUPd32
8250 { 2417, 5, 1, 4, 622, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo331, -1 ,nullptr }, // Inst #2417 = VLD2DUPd8
8282 { 2449, 5, 1, 4, 603, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo331, -1 ,nullptr }, // Inst #2449 = VLD2b16
8285 { 2452, 5, 1, 4, 603, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo331, -1 ,nullptr }, // Inst #2452 = VLD2b32
8288 { 2455, 5, 1, 4, 603, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo331, -1 ,nullptr }, // Inst #2455 = VLD2b8
8291 { 2458, 5, 1, 4, 993, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo331, -1 ,nullptr }, // Inst #2458 = VLD2d16
8294 { 2461, 5, 1, 4, 993, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo331, -1 ,nullptr }, // Inst #2461 = VLD2d32
8297 { 2464, 5, 1, 4, 993, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo331, -1 ,nullptr }, // Inst #2464 = VLD2d8