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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/ARM/ARMGenInstrInfo.inc 8134 { 2301, 7, 2, 4, 619, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo330, -1 ,nullptr }, // Inst #2301 = VLD1DUPd16wb_register
8137 { 2304, 7, 2, 4, 619, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo330, -1 ,nullptr }, // Inst #2304 = VLD1DUPd32wb_register
8140 { 2307, 7, 2, 4, 619, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo330, -1 ,nullptr }, // Inst #2307 = VLD1DUPd8wb_register
8166 { 2333, 7, 2, 4, 602, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo330, -1 ,nullptr }, // Inst #2333 = VLD1d16Qwb_register
8170 { 2337, 7, 2, 4, 600, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo330, -1 ,nullptr }, // Inst #2337 = VLD1d16Twb_register
8172 { 2339, 7, 2, 4, 597, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo330, -1 ,nullptr }, // Inst #2339 = VLD1d16wb_register
8177 { 2344, 7, 2, 4, 602, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo330, -1 ,nullptr }, // Inst #2344 = VLD1d32Qwb_register
8181 { 2348, 7, 2, 4, 600, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo330, -1 ,nullptr }, // Inst #2348 = VLD1d32Twb_register
8183 { 2350, 7, 2, 4, 597, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo330, -1 ,nullptr }, // Inst #2350 = VLD1d32wb_register
8190 { 2357, 7, 2, 4, 602, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo330, -1 ,nullptr }, // Inst #2357 = VLD1d64Qwb_register
8196 { 2363, 7, 2, 4, 600, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo330, -1 ,nullptr }, // Inst #2363 = VLD1d64Twb_register
8198 { 2365, 7, 2, 4, 597, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo330, -1 ,nullptr }, // Inst #2365 = VLD1d64wb_register
8203 { 2370, 7, 2, 4, 602, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo330, -1 ,nullptr }, // Inst #2370 = VLD1d8Qwb_register
8207 { 2374, 7, 2, 4, 600, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo330, -1 ,nullptr }, // Inst #2374 = VLD1d8Twb_register
8209 { 2376, 7, 2, 4, 597, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo330, -1 ,nullptr }, // Inst #2376 = VLD1d8wb_register
8305 { 2472, 7, 2, 4, 606, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo330, -1 ,nullptr }, // Inst #2472 = VLD2q16wb_register
8311 { 2478, 7, 2, 4, 606, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo330, -1 ,nullptr }, // Inst #2478 = VLD2q32wb_register
8317 { 2484, 7, 2, 4, 606, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo330, -1 ,nullptr }, // Inst #2484 = VLD2q8wb_register