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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/ARM/ARMGenInstrInfo.inc 8133 { 2300, 6, 2, 4, 619, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo329, -1 ,nullptr }, // Inst #2300 = VLD1DUPd16wb_fixed
8136 { 2303, 6, 2, 4, 619, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo329, -1 ,nullptr }, // Inst #2303 = VLD1DUPd32wb_fixed
8139 { 2306, 6, 2, 4, 619, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo329, -1 ,nullptr }, // Inst #2306 = VLD1DUPd8wb_fixed
8165 { 2332, 6, 2, 4, 602, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo329, -1 ,nullptr }, // Inst #2332 = VLD1d16Qwb_fixed
8169 { 2336, 6, 2, 4, 600, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo329, -1 ,nullptr }, // Inst #2336 = VLD1d16Twb_fixed
8171 { 2338, 6, 2, 4, 597, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo329, -1 ,nullptr }, // Inst #2338 = VLD1d16wb_fixed
8176 { 2343, 6, 2, 4, 602, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo329, -1 ,nullptr }, // Inst #2343 = VLD1d32Qwb_fixed
8180 { 2347, 6, 2, 4, 600, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo329, -1 ,nullptr }, // Inst #2347 = VLD1d32Twb_fixed
8182 { 2349, 6, 2, 4, 597, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo329, -1 ,nullptr }, // Inst #2349 = VLD1d32wb_fixed
8189 { 2356, 6, 2, 4, 602, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo329, -1 ,nullptr }, // Inst #2356 = VLD1d64Qwb_fixed
8195 { 2362, 6, 2, 4, 600, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo329, -1 ,nullptr }, // Inst #2362 = VLD1d64Twb_fixed
8197 { 2364, 6, 2, 4, 597, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo329, -1 ,nullptr }, // Inst #2364 = VLD1d64wb_fixed
8202 { 2369, 6, 2, 4, 602, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo329, -1 ,nullptr }, // Inst #2369 = VLD1d8Qwb_fixed
8206 { 2373, 6, 2, 4, 600, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo329, -1 ,nullptr }, // Inst #2373 = VLD1d8Twb_fixed
8208 { 2375, 6, 2, 4, 597, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo329, -1 ,nullptr }, // Inst #2375 = VLD1d8wb_fixed
8304 { 2471, 6, 2, 4, 606, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo329, -1 ,nullptr }, // Inst #2471 = VLD2q16wb_fixed
8310 { 2477, 6, 2, 4, 606, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo329, -1 ,nullptr }, // Inst #2477 = VLD2q32wb_fixed
8316 { 2483, 6, 2, 4, 606, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo329, -1 ,nullptr }, // Inst #2483 = VLD2q8wb_fixed