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|
reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/ARM/ARMGenInstrInfo.inc 8014 { 2181, 5, 1, 4, 985, 0|(1ULL<<MCID::Predicable), 0x11080ULL, nullptr, nullptr, OperandInfo312, -1 ,nullptr }, // Inst #2181 = VCVTf2xsd
8016 { 2183, 5, 1, 4, 985, 0|(1ULL<<MCID::Predicable), 0x11080ULL, nullptr, nullptr, OperandInfo312, -1 ,nullptr }, // Inst #2183 = VCVTf2xud
8023 { 2190, 5, 1, 4, 557, 0|(1ULL<<MCID::Predicable), 0x11080ULL, nullptr, nullptr, OperandInfo312, -1 ,nullptr }, // Inst #2190 = VCVTh2xsd
8025 { 2192, 5, 1, 4, 557, 0|(1ULL<<MCID::Predicable), 0x11080ULL, nullptr, nullptr, OperandInfo312, -1 ,nullptr }, // Inst #2192 = VCVTh2xud
8035 { 2202, 5, 1, 4, 985, 0|(1ULL<<MCID::Predicable), 0x11080ULL, nullptr, nullptr, OperandInfo312, -1 ,nullptr }, // Inst #2202 = VCVTxs2fd
8037 { 2204, 5, 1, 4, 557, 0|(1ULL<<MCID::Predicable), 0x11080ULL, nullptr, nullptr, OperandInfo312, -1 ,nullptr }, // Inst #2204 = VCVTxs2hd
8039 { 2206, 5, 1, 4, 985, 0|(1ULL<<MCID::Predicable), 0x11080ULL, nullptr, nullptr, OperandInfo312, -1 ,nullptr }, // Inst #2206 = VCVTxu2fd
8041 { 2208, 5, 1, 4, 557, 0|(1ULL<<MCID::Predicable), 0x11080ULL, nullptr, nullptr, OperandInfo312, -1 ,nullptr }, // Inst #2208 = VCVTxu2hd
8052 { 2219, 5, 1, 4, 571, 0|(1ULL<<MCID::Predicable), 0x11100ULL, nullptr, nullptr, OperandInfo312, -1 ,nullptr }, // Inst #2219 = VDUPLN16d
8054 { 2221, 5, 1, 4, 571, 0|(1ULL<<MCID::Predicable), 0x11100ULL, nullptr, nullptr, OperandInfo312, -1 ,nullptr }, // Inst #2221 = VDUPLN32d
8056 { 2223, 5, 1, 4, 571, 0|(1ULL<<MCID::Predicable), 0x11100ULL, nullptr, nullptr, OperandInfo312, -1 ,nullptr }, // Inst #2223 = VDUPLN8d
9026 { 3193, 5, 1, 4, 979, 0|(1ULL<<MCID::Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo312, -1 ,nullptr }, // Inst #3193 = VRSHRsv1i64
9027 { 3194, 5, 1, 4, 979, 0|(1ULL<<MCID::Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo312, -1 ,nullptr }, // Inst #3194 = VRSHRsv2i32
9029 { 3196, 5, 1, 4, 979, 0|(1ULL<<MCID::Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo312, -1 ,nullptr }, // Inst #3196 = VRSHRsv4i16
9032 { 3199, 5, 1, 4, 979, 0|(1ULL<<MCID::Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo312, -1 ,nullptr }, // Inst #3199 = VRSHRsv8i8
9034 { 3201, 5, 1, 4, 979, 0|(1ULL<<MCID::Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo312, -1 ,nullptr }, // Inst #3201 = VRSHRuv1i64
9035 { 3202, 5, 1, 4, 979, 0|(1ULL<<MCID::Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo312, -1 ,nullptr }, // Inst #3202 = VRSHRuv2i32
9037 { 3204, 5, 1, 4, 979, 0|(1ULL<<MCID::Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo312, -1 ,nullptr }, // Inst #3204 = VRSHRuv4i16
9040 { 3207, 5, 1, 4, 979, 0|(1ULL<<MCID::Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo312, -1 ,nullptr }, // Inst #3207 = VRSHRuv8i8
9128 { 3295, 5, 1, 4, 977, 0|(1ULL<<MCID::Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo312, -1 ,nullptr }, // Inst #3295 = VSHRsv1i64
9129 { 3296, 5, 1, 4, 977, 0|(1ULL<<MCID::Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo312, -1 ,nullptr }, // Inst #3296 = VSHRsv2i32
9131 { 3298, 5, 1, 4, 977, 0|(1ULL<<MCID::Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo312, -1 ,nullptr }, // Inst #3298 = VSHRsv4i16
9134 { 3301, 5, 1, 4, 977, 0|(1ULL<<MCID::Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo312, -1 ,nullptr }, // Inst #3301 = VSHRsv8i8
9136 { 3303, 5, 1, 4, 977, 0|(1ULL<<MCID::Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo312, -1 ,nullptr }, // Inst #3303 = VSHRuv1i64
9137 { 3304, 5, 1, 4, 977, 0|(1ULL<<MCID::Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo312, -1 ,nullptr }, // Inst #3304 = VSHRuv2i32
9139 { 3306, 5, 1, 4, 977, 0|(1ULL<<MCID::Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo312, -1 ,nullptr }, // Inst #3306 = VSHRuv4i16
9142 { 3309, 5, 1, 4, 977, 0|(1ULL<<MCID::Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo312, -1 ,nullptr }, // Inst #3309 = VSHRuv8i8