|
|
reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
|
References
gen/lib/Target/ARM/ARMGenInstrInfo.inc 7752 { 1919, 4, 1, 4, 488, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo287, -1 ,nullptr }, // Inst #1919 = VABSfq
7754 { 1921, 4, 1, 4, 736, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo287, -1 ,nullptr }, // Inst #1921 = VABShq
7755 { 1922, 4, 1, 4, 489, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo287, -1 ,nullptr }, // Inst #1922 = VABSv16i8
7758 { 1925, 4, 1, 4, 489, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo287, -1 ,nullptr }, // Inst #1925 = VABSv4i32
7759 { 1926, 4, 1, 4, 489, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo287, -1 ,nullptr }, // Inst #1926 = VABSv8i16
7827 { 1994, 4, 1, 4, 484, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo287, -1 ,nullptr }, // Inst #1994 = VCEQzv16i8
7831 { 1998, 4, 1, 4, 484, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo287, -1 ,nullptr }, // Inst #1998 = VCEQzv4f32
7833 { 2000, 4, 1, 4, 484, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo287, -1 ,nullptr }, // Inst #2000 = VCEQzv4i32
7834 { 2001, 4, 1, 4, 484, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo287, -1 ,nullptr }, // Inst #2001 = VCEQzv8f16
7835 { 2002, 4, 1, 4, 484, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo287, -1 ,nullptr }, // Inst #2002 = VCEQzv8i16
7853 { 2020, 4, 1, 4, 484, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo287, -1 ,nullptr }, // Inst #2020 = VCGEzv16i8
7857 { 2024, 4, 1, 4, 484, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo287, -1 ,nullptr }, // Inst #2024 = VCGEzv4f32
7859 { 2026, 4, 1, 4, 484, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo287, -1 ,nullptr }, // Inst #2026 = VCGEzv4i32
7860 { 2027, 4, 1, 4, 484, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo287, -1 ,nullptr }, // Inst #2027 = VCGEzv8f16
7861 { 2028, 4, 1, 4, 484, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo287, -1 ,nullptr }, // Inst #2028 = VCGEzv8i16
7879 { 2046, 4, 1, 4, 484, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo287, -1 ,nullptr }, // Inst #2046 = VCGTzv16i8
7883 { 2050, 4, 1, 4, 484, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo287, -1 ,nullptr }, // Inst #2050 = VCGTzv4f32
7885 { 2052, 4, 1, 4, 484, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo287, -1 ,nullptr }, // Inst #2052 = VCGTzv4i32
7886 { 2053, 4, 1, 4, 484, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo287, -1 ,nullptr }, // Inst #2053 = VCGTzv8f16
7887 { 2054, 4, 1, 4, 484, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo287, -1 ,nullptr }, // Inst #2054 = VCGTzv8i16
7889 { 2056, 4, 1, 4, 484, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo287, -1 ,nullptr }, // Inst #2056 = VCLEzv16i8
7893 { 2060, 4, 1, 4, 484, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo287, -1 ,nullptr }, // Inst #2060 = VCLEzv4f32
7895 { 2062, 4, 1, 4, 484, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo287, -1 ,nullptr }, // Inst #2062 = VCLEzv4i32
7896 { 2063, 4, 1, 4, 484, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo287, -1 ,nullptr }, // Inst #2063 = VCLEzv8f16
7897 { 2064, 4, 1, 4, 484, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo287, -1 ,nullptr }, // Inst #2064 = VCLEzv8i16
7899 { 2066, 4, 1, 4, 471, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo287, -1 ,nullptr }, // Inst #2066 = VCLSv16i8
7902 { 2069, 4, 1, 4, 471, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo287, -1 ,nullptr }, // Inst #2069 = VCLSv4i32
7903 { 2070, 4, 1, 4, 471, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo287, -1 ,nullptr }, // Inst #2070 = VCLSv8i16
7905 { 2072, 4, 1, 4, 484, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo287, -1 ,nullptr }, // Inst #2072 = VCLTzv16i8
7909 { 2076, 4, 1, 4, 484, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo287, -1 ,nullptr }, // Inst #2076 = VCLTzv4f32
7911 { 2078, 4, 1, 4, 484, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo287, -1 ,nullptr }, // Inst #2078 = VCLTzv4i32
7912 { 2079, 4, 1, 4, 484, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo287, -1 ,nullptr }, // Inst #2079 = VCLTzv8f16
7913 { 2080, 4, 1, 4, 484, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo287, -1 ,nullptr }, // Inst #2080 = VCLTzv8i16
7915 { 2082, 4, 1, 4, 766, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo287, -1 ,nullptr }, // Inst #2082 = VCLZv16i8
7918 { 2085, 4, 1, 4, 766, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo287, -1 ,nullptr }, // Inst #2085 = VCLZv4i32
7919 { 2086, 4, 1, 4, 766, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo287, -1 ,nullptr }, // Inst #2086 = VCLZv8i16
7942 { 2109, 4, 1, 4, 766, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo287, -1 ,nullptr }, // Inst #2109 = VCNTq
8011 { 2178, 4, 1, 4, 986, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo287, -1 ,nullptr }, // Inst #2178 = VCVTf2sq
8013 { 2180, 4, 1, 4, 986, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo287, -1 ,nullptr }, // Inst #2180 = VCVTf2uq
8020 { 2187, 4, 1, 4, 556, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo287, -1 ,nullptr }, // Inst #2187 = VCVTh2sq
8022 { 2189, 4, 1, 4, 556, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo287, -1 ,nullptr }, // Inst #2189 = VCVTh2uq
8028 { 2195, 4, 1, 4, 986, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo287, -1 ,nullptr }, // Inst #2195 = VCVTs2fq
8030 { 2197, 4, 1, 4, 556, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo287, -1 ,nullptr }, // Inst #2197 = VCVTs2hq
8032 { 2199, 4, 1, 4, 986, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo287, -1 ,nullptr }, // Inst #2199 = VCVTu2fq
8034 { 2201, 4, 1, 4, 556, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo287, -1 ,nullptr }, // Inst #2201 = VCVTu2hq
8673 { 2840, 4, 1, 4, 567, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo287, -1 ,nullptr }, // Inst #2840 = VMVNq
8681 { 2848, 4, 1, 4, 459, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo287, -1 ,nullptr }, // Inst #2848 = VNEGf32q
8684 { 2851, 4, 1, 4, 779, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo287, -1 ,nullptr }, // Inst #2851 = VNEGhq
8686 { 2853, 4, 1, 4, 781, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo287, -1 ,nullptr }, // Inst #2853 = VNEGs16q
8688 { 2855, 4, 1, 4, 781, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo287, -1 ,nullptr }, // Inst #2855 = VNEGs32q
8690 { 2857, 4, 1, 4, 781, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo287, -1 ,nullptr }, // Inst #2857 = VNEGs8q
8720 { 2887, 4, 1, 4, 784, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo287, -1 ,nullptr }, // Inst #2887 = VPADDLsv16i8
8723 { 2890, 4, 1, 4, 784, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo287, -1 ,nullptr }, // Inst #2890 = VPADDLsv4i32
8724 { 2891, 4, 1, 4, 784, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo287, -1 ,nullptr }, // Inst #2891 = VPADDLsv8i16
8726 { 2893, 4, 1, 4, 784, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo287, -1 ,nullptr }, // Inst #2893 = VPADDLuv16i8
8729 { 2896, 4, 1, 4, 784, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo287, -1 ,nullptr }, // Inst #2896 = VPADDLuv4i32
8730 { 2897, 4, 1, 4, 784, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo287, -1 ,nullptr }, // Inst #2897 = VPADDLuv8i16
8753 { 2920, 4, 1, 4, 786, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo287, -1 ,nullptr }, // Inst #2920 = VQABSv16i8
8756 { 2923, 4, 1, 4, 786, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo287, -1 ,nullptr }, // Inst #2923 = VQABSv4i32
8757 { 2924, 4, 1, 4, 786, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo287, -1 ,nullptr }, // Inst #2924 = VQABSv8i16
8804 { 2971, 4, 1, 4, 491, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo287, -1 ,nullptr }, // Inst #2971 = VQNEGv16i8
8807 { 2974, 4, 1, 4, 491, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo287, -1 ,nullptr }, // Inst #2974 = VQNEGv4i32
8808 { 2975, 4, 1, 4, 491, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo287, -1 ,nullptr }, // Inst #2975 = VQNEGv8i16
8929 { 3096, 4, 1, 4, 496, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo287, -1 ,nullptr }, // Inst #3096 = VRECPEfq
8931 { 3098, 4, 1, 4, 496, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo287, -1 ,nullptr }, // Inst #3098 = VRECPEhq
8932 { 3099, 4, 1, 4, 496, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo287, -1 ,nullptr }, // Inst #3099 = VRECPEq
8938 { 3105, 4, 1, 4, 475, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo287, -1 ,nullptr }, // Inst #3105 = VREV16q8
8941 { 3108, 4, 1, 4, 475, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo287, -1 ,nullptr }, // Inst #3108 = VREV32q16
8942 { 3109, 4, 1, 4, 475, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo287, -1 ,nullptr }, // Inst #3109 = VREV32q8
8946 { 3113, 4, 1, 4, 475, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo287, -1 ,nullptr }, // Inst #3113 = VREV64q16
8947 { 3114, 4, 1, 4, 475, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo287, -1 ,nullptr }, // Inst #3114 = VREV64q32
8948 { 3115, 4, 1, 4, 475, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo287, -1 ,nullptr }, // Inst #3115 = VREV64q8
9043 { 3210, 4, 1, 4, 496, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo287, -1 ,nullptr }, // Inst #3210 = VRSQRTEfq
9045 { 3212, 4, 1, 4, 496, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo287, -1 ,nullptr }, // Inst #3212 = VRSQRTEhq
9046 { 3213, 4, 1, 4, 496, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo287, -1 ,nullptr }, // Inst #3213 = VRSQRTEq