|
|
reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
|
References
gen/lib/Target/ARM/ARMGenInstrInfo.inc 7748 { 1915, 4, 1, 4, 732, 0|(1ULL<<MCID::Predicable), 0x8780ULL, nullptr, nullptr, OperandInfo284, -1 ,nullptr }, // Inst #1915 = VABSD
7751 { 1918, 4, 1, 4, 487, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo284, -1 ,nullptr }, // Inst #1918 = VABSfd
7753 { 1920, 4, 1, 4, 735, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo284, -1 ,nullptr }, // Inst #1920 = VABShd
7756 { 1923, 4, 1, 4, 490, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo284, -1 ,nullptr }, // Inst #1923 = VABSv2i32
7757 { 1924, 4, 1, 4, 490, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo284, -1 ,nullptr }, // Inst #1924 = VABSv4i16
7760 { 1927, 4, 1, 4, 490, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo284, -1 ,nullptr }, // Inst #1927 = VABSv8i8
7828 { 1995, 4, 1, 4, 484, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo284, -1 ,nullptr }, // Inst #1995 = VCEQzv2f32
7829 { 1996, 4, 1, 4, 484, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo284, -1 ,nullptr }, // Inst #1996 = VCEQzv2i32
7830 { 1997, 4, 1, 4, 484, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo284, -1 ,nullptr }, // Inst #1997 = VCEQzv4f16
7832 { 1999, 4, 1, 4, 484, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo284, -1 ,nullptr }, // Inst #1999 = VCEQzv4i16
7836 { 2003, 4, 1, 4, 484, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo284, -1 ,nullptr }, // Inst #2003 = VCEQzv8i8
7854 { 2021, 4, 1, 4, 484, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo284, -1 ,nullptr }, // Inst #2021 = VCGEzv2f32
7855 { 2022, 4, 1, 4, 484, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo284, -1 ,nullptr }, // Inst #2022 = VCGEzv2i32
7856 { 2023, 4, 1, 4, 484, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo284, -1 ,nullptr }, // Inst #2023 = VCGEzv4f16
7858 { 2025, 4, 1, 4, 484, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo284, -1 ,nullptr }, // Inst #2025 = VCGEzv4i16
7862 { 2029, 4, 1, 4, 484, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo284, -1 ,nullptr }, // Inst #2029 = VCGEzv8i8
7880 { 2047, 4, 1, 4, 484, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo284, -1 ,nullptr }, // Inst #2047 = VCGTzv2f32
7881 { 2048, 4, 1, 4, 484, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo284, -1 ,nullptr }, // Inst #2048 = VCGTzv2i32
7882 { 2049, 4, 1, 4, 484, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo284, -1 ,nullptr }, // Inst #2049 = VCGTzv4f16
7884 { 2051, 4, 1, 4, 484, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo284, -1 ,nullptr }, // Inst #2051 = VCGTzv4i16
7888 { 2055, 4, 1, 4, 484, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo284, -1 ,nullptr }, // Inst #2055 = VCGTzv8i8
7890 { 2057, 4, 1, 4, 484, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo284, -1 ,nullptr }, // Inst #2057 = VCLEzv2f32
7891 { 2058, 4, 1, 4, 484, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo284, -1 ,nullptr }, // Inst #2058 = VCLEzv2i32
7892 { 2059, 4, 1, 4, 484, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo284, -1 ,nullptr }, // Inst #2059 = VCLEzv4f16
7894 { 2061, 4, 1, 4, 484, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo284, -1 ,nullptr }, // Inst #2061 = VCLEzv4i16
7898 { 2065, 4, 1, 4, 484, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo284, -1 ,nullptr }, // Inst #2065 = VCLEzv8i8
7900 { 2067, 4, 1, 4, 470, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo284, -1 ,nullptr }, // Inst #2067 = VCLSv2i32
7901 { 2068, 4, 1, 4, 470, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo284, -1 ,nullptr }, // Inst #2068 = VCLSv4i16
7904 { 2071, 4, 1, 4, 470, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo284, -1 ,nullptr }, // Inst #2071 = VCLSv8i8
7906 { 2073, 4, 1, 4, 484, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo284, -1 ,nullptr }, // Inst #2073 = VCLTzv2f32
7907 { 2074, 4, 1, 4, 484, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo284, -1 ,nullptr }, // Inst #2074 = VCLTzv2i32
7908 { 2075, 4, 1, 4, 484, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo284, -1 ,nullptr }, // Inst #2075 = VCLTzv4f16
7910 { 2077, 4, 1, 4, 484, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo284, -1 ,nullptr }, // Inst #2077 = VCLTzv4i16
7914 { 2081, 4, 1, 4, 484, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo284, -1 ,nullptr }, // Inst #2081 = VCLTzv8i8
7916 { 2083, 4, 1, 4, 767, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo284, -1 ,nullptr }, // Inst #2083 = VCLZv2i32
7917 { 2084, 4, 1, 4, 767, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo284, -1 ,nullptr }, // Inst #2084 = VCLZv4i16
7920 { 2087, 4, 1, 4, 767, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo284, -1 ,nullptr }, // Inst #2087 = VCLZv8i8
7929 { 2096, 4, 0, 4, 515, 0|(1ULL<<MCID::Predicable), 0x8780ULL, nullptr, ImplicitList11, OperandInfo284, -1 ,nullptr }, // Inst #2096 = VCMPD
7930 { 2097, 4, 0, 4, 515, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8780ULL, nullptr, ImplicitList11, OperandInfo284, -1 ,nullptr }, // Inst #2097 = VCMPED
7941 { 2108, 4, 1, 4, 767, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo284, -1 ,nullptr }, // Inst #2108 = VCNTd
8010 { 2177, 4, 1, 4, 985, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo284, -1 ,nullptr }, // Inst #2177 = VCVTf2sd
8012 { 2179, 4, 1, 4, 985, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo284, -1 ,nullptr }, // Inst #2179 = VCVTf2ud
8019 { 2186, 4, 1, 4, 557, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo284, -1 ,nullptr }, // Inst #2186 = VCVTh2sd
8021 { 2188, 4, 1, 4, 557, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo284, -1 ,nullptr }, // Inst #2188 = VCVTh2ud
8027 { 2194, 4, 1, 4, 985, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo284, -1 ,nullptr }, // Inst #2194 = VCVTs2fd
8029 { 2196, 4, 1, 4, 557, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo284, -1 ,nullptr }, // Inst #2196 = VCVTs2hd
8031 { 2198, 4, 1, 4, 985, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo284, -1 ,nullptr }, // Inst #2198 = VCVTu2fd
8033 { 2200, 4, 1, 4, 557, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo284, -1 ,nullptr }, // Inst #2200 = VCVTu2hd
8584 { 2751, 4, 1, 4, 565, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::Predicable), 0x8780ULL, nullptr, nullptr, OperandInfo284, -1 ,nullptr }, // Inst #2751 = VMOVD
8672 { 2839, 4, 1, 4, 567, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo284, -1 ,nullptr }, // Inst #2839 = VMVNd
8678 { 2845, 4, 1, 4, 513, 0|(1ULL<<MCID::Predicable), 0x8780ULL, nullptr, nullptr, OperandInfo284, -1 ,nullptr }, // Inst #2845 = VNEGD
8682 { 2849, 4, 1, 4, 460, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo284, -1 ,nullptr }, // Inst #2849 = VNEGfd
8683 { 2850, 4, 1, 4, 778, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo284, -1 ,nullptr }, // Inst #2850 = VNEGhd
8685 { 2852, 4, 1, 4, 780, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo284, -1 ,nullptr }, // Inst #2852 = VNEGs16d
8687 { 2854, 4, 1, 4, 780, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo284, -1 ,nullptr }, // Inst #2854 = VNEGs32d
8689 { 2856, 4, 1, 4, 780, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo284, -1 ,nullptr }, // Inst #2856 = VNEGs8d
8721 { 2888, 4, 1, 4, 784, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo284, -1 ,nullptr }, // Inst #2888 = VPADDLsv2i32
8722 { 2889, 4, 1, 4, 784, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo284, -1 ,nullptr }, // Inst #2889 = VPADDLsv4i16
8725 { 2892, 4, 1, 4, 784, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo284, -1 ,nullptr }, // Inst #2892 = VPADDLsv8i8
8727 { 2894, 4, 1, 4, 784, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo284, -1 ,nullptr }, // Inst #2894 = VPADDLuv2i32
8728 { 2895, 4, 1, 4, 784, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo284, -1 ,nullptr }, // Inst #2895 = VPADDLuv4i16
8731 { 2898, 4, 1, 4, 784, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo284, -1 ,nullptr }, // Inst #2898 = VPADDLuv8i8
8754 { 2921, 4, 1, 4, 785, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo284, -1 ,nullptr }, // Inst #2921 = VQABSv2i32
8755 { 2922, 4, 1, 4, 785, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo284, -1 ,nullptr }, // Inst #2922 = VQABSv4i16
8758 { 2925, 4, 1, 4, 785, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo284, -1 ,nullptr }, // Inst #2925 = VQABSv8i8
8805 { 2972, 4, 1, 4, 492, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo284, -1 ,nullptr }, // Inst #2972 = VQNEGv2i32
8806 { 2973, 4, 1, 4, 492, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo284, -1 ,nullptr }, // Inst #2973 = VQNEGv4i16
8809 { 2976, 4, 1, 4, 492, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo284, -1 ,nullptr }, // Inst #2976 = VQNEGv8i8
8927 { 3094, 4, 1, 4, 495, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo284, -1 ,nullptr }, // Inst #3094 = VRECPEd
8928 { 3095, 4, 1, 4, 495, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo284, -1 ,nullptr }, // Inst #3095 = VRECPEfd
8930 { 3097, 4, 1, 4, 495, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo284, -1 ,nullptr }, // Inst #3097 = VRECPEhd
8937 { 3104, 4, 1, 4, 474, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo284, -1 ,nullptr }, // Inst #3104 = VREV16d8
8939 { 3106, 4, 1, 4, 474, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo284, -1 ,nullptr }, // Inst #3106 = VREV32d16
8940 { 3107, 4, 1, 4, 474, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo284, -1 ,nullptr }, // Inst #3107 = VREV32d8
8943 { 3110, 4, 1, 4, 474, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo284, -1 ,nullptr }, // Inst #3110 = VREV64d16
8944 { 3111, 4, 1, 4, 474, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo284, -1 ,nullptr }, // Inst #3111 = VREV64d32
8945 { 3112, 4, 1, 4, 474, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo284, -1 ,nullptr }, // Inst #3112 = VREV64d8
8989 { 3156, 4, 1, 4, 951, 0|(1ULL<<MCID::Predicable), 0x8780ULL, nullptr, nullptr, OperandInfo284, -1 ,nullptr }, // Inst #3156 = VRINTRD
8992 { 3159, 4, 1, 4, 951, 0|(1ULL<<MCID::Predicable), 0x8780ULL, nullptr, nullptr, OperandInfo284, -1 ,nullptr }, // Inst #3159 = VRINTXD
8999 { 3166, 4, 1, 4, 951, 0|(1ULL<<MCID::Predicable), 0x8780ULL, nullptr, nullptr, OperandInfo284, -1 ,nullptr }, // Inst #3166 = VRINTZD
9041 { 3208, 4, 1, 4, 495, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo284, -1 ,nullptr }, // Inst #3208 = VRSQRTEd
9042 { 3209, 4, 1, 4, 495, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo284, -1 ,nullptr }, // Inst #3209 = VRSQRTEfd
9044 { 3211, 4, 1, 4, 495, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo284, -1 ,nullptr }, // Inst #3211 = VRSQRTEhd
9160 { 3327, 4, 1, 4, 675, 0|(1ULL<<MCID::Predicable), 0x8780ULL, nullptr, nullptr, OperandInfo284, -1 ,nullptr }, // Inst #3327 = VSQRTD