|
|
reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
|
References
gen/lib/Target/ARM/ARMGenInstrInfo.inc 7733 { 1900, 5, 1, 4, 731, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo283, -1 ,nullptr }, // Inst #1900 = VABDfq
7735 { 1902, 5, 1, 4, 731, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo283, -1 ,nullptr }, // Inst #1902 = VABDhq
7736 { 1903, 5, 1, 4, 750, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo283, -1 ,nullptr }, // Inst #1903 = VABDsv16i8
7739 { 1906, 5, 1, 4, 750, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo283, -1 ,nullptr }, // Inst #1906 = VABDsv4i32
7740 { 1907, 5, 1, 4, 750, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo283, -1 ,nullptr }, // Inst #1907 = VABDsv8i16
7742 { 1909, 5, 1, 4, 750, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo283, -1 ,nullptr }, // Inst #1909 = VABDuv16i8
7745 { 1912, 5, 1, 4, 750, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo283, -1 ,nullptr }, // Inst #1912 = VABDuv4i32
7746 { 1913, 5, 1, 4, 750, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo283, -1 ,nullptr }, // Inst #1913 = VABDuv8i16
7762 { 1929, 5, 1, 4, 738, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo283, -1 ,nullptr }, // Inst #1929 = VACGEfq
7764 { 1931, 5, 1, 4, 738, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo283, -1 ,nullptr }, // Inst #1931 = VACGEhq
7766 { 1933, 5, 1, 4, 738, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo283, -1 ,nullptr }, // Inst #1933 = VACGTfq
7768 { 1935, 5, 1, 4, 738, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo283, -1 ,nullptr }, // Inst #1935 = VACGThq
7788 { 1955, 5, 1, 4, 742, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo283, -1 ,nullptr }, // Inst #1955 = VADDfq
7790 { 1957, 5, 1, 4, 743, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo283, -1 ,nullptr }, // Inst #1957 = VADDhq
7791 { 1958, 5, 1, 4, 754, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo283, -1 ,nullptr }, // Inst #1958 = VADDv16i8
7794 { 1961, 5, 1, 4, 754, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo283, -1 ,nullptr }, // Inst #1961 = VADDv2i64
7796 { 1963, 5, 1, 4, 754, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo283, -1 ,nullptr }, // Inst #1963 = VADDv4i32
7797 { 1964, 5, 1, 4, 754, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo283, -1 ,nullptr }, // Inst #1964 = VADDv8i16
7800 { 1967, 5, 1, 4, 757, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo283, -1 ,nullptr }, // Inst #1967 = VANDq
7806 { 1973, 5, 1, 4, 757, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo283, -1 ,nullptr }, // Inst #1973 = VBICq
7818 { 1985, 5, 1, 4, 481, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo283, -1 ,nullptr }, // Inst #1985 = VCEQfq
7820 { 1987, 5, 1, 4, 481, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo283, -1 ,nullptr }, // Inst #1987 = VCEQhq
7821 { 1988, 5, 1, 4, 764, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo283, -1 ,nullptr }, // Inst #1988 = VCEQv16i8
7824 { 1991, 5, 1, 4, 764, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo283, -1 ,nullptr }, // Inst #1991 = VCEQv4i32
7825 { 1992, 5, 1, 4, 764, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo283, -1 ,nullptr }, // Inst #1992 = VCEQv8i16
7838 { 2005, 5, 1, 4, 481, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo283, -1 ,nullptr }, // Inst #2005 = VCGEfq
7840 { 2007, 5, 1, 4, 481, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo283, -1 ,nullptr }, // Inst #2007 = VCGEhq
7841 { 2008, 5, 1, 4, 764, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo283, -1 ,nullptr }, // Inst #2008 = VCGEsv16i8
7844 { 2011, 5, 1, 4, 764, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo283, -1 ,nullptr }, // Inst #2011 = VCGEsv4i32
7845 { 2012, 5, 1, 4, 764, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo283, -1 ,nullptr }, // Inst #2012 = VCGEsv8i16
7847 { 2014, 5, 1, 4, 764, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo283, -1 ,nullptr }, // Inst #2014 = VCGEuv16i8
7850 { 2017, 5, 1, 4, 764, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo283, -1 ,nullptr }, // Inst #2017 = VCGEuv4i32
7851 { 2018, 5, 1, 4, 764, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo283, -1 ,nullptr }, // Inst #2018 = VCGEuv8i16
7864 { 2031, 5, 1, 4, 481, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo283, -1 ,nullptr }, // Inst #2031 = VCGTfq
7866 { 2033, 5, 1, 4, 481, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo283, -1 ,nullptr }, // Inst #2033 = VCGThq
7867 { 2034, 5, 1, 4, 764, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo283, -1 ,nullptr }, // Inst #2034 = VCGTsv16i8
7870 { 2037, 5, 1, 4, 764, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo283, -1 ,nullptr }, // Inst #2037 = VCGTsv4i32
7871 { 2038, 5, 1, 4, 764, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo283, -1 ,nullptr }, // Inst #2038 = VCGTsv8i16
7873 { 2040, 5, 1, 4, 764, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo283, -1 ,nullptr }, // Inst #2040 = VCGTuv16i8
7876 { 2043, 5, 1, 4, 764, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo283, -1 ,nullptr }, // Inst #2043 = VCGTuv4i32
7877 { 2044, 5, 1, 4, 764, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo283, -1 ,nullptr }, // Inst #2044 = VCGTuv8i16
8059 { 2226, 5, 1, 4, 757, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo283, -1 ,nullptr }, // Inst #2226 = VEORq
8106 { 2273, 5, 1, 4, 774, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo283, -1 ,nullptr }, // Inst #2273 = VHADDsv16i8
8109 { 2276, 5, 1, 4, 774, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo283, -1 ,nullptr }, // Inst #2276 = VHADDsv4i32
8110 { 2277, 5, 1, 4, 774, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo283, -1 ,nullptr }, // Inst #2277 = VHADDsv8i16
8112 { 2279, 5, 1, 4, 774, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo283, -1 ,nullptr }, // Inst #2279 = VHADDuv16i8
8115 { 2282, 5, 1, 4, 774, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo283, -1 ,nullptr }, // Inst #2282 = VHADDuv4i32
8116 { 2283, 5, 1, 4, 774, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo283, -1 ,nullptr }, // Inst #2283 = VHADDuv8i16
8118 { 2285, 5, 1, 4, 465, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo283, -1 ,nullptr }, // Inst #2285 = VHSUBsv16i8
8121 { 2288, 5, 1, 4, 465, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo283, -1 ,nullptr }, // Inst #2288 = VHSUBsv4i32
8122 { 2289, 5, 1, 4, 465, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo283, -1 ,nullptr }, // Inst #2289 = VHSUBsv8i16
8124 { 2291, 5, 1, 4, 465, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo283, -1 ,nullptr }, // Inst #2291 = VHSUBuv16i8
8127 { 2294, 5, 1, 4, 465, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo283, -1 ,nullptr }, // Inst #2294 = VHSUBuv4i32
8128 { 2295, 5, 1, 4, 465, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo283, -1 ,nullptr }, // Inst #2295 = VHSUBuv8i16
8491 { 2658, 5, 1, 4, 519, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo283, -1 ,nullptr }, // Inst #2658 = VMAXfq
8493 { 2660, 5, 1, 4, 519, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo283, -1 ,nullptr }, // Inst #2660 = VMAXhq
8494 { 2661, 5, 1, 4, 775, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo283, -1 ,nullptr }, // Inst #2661 = VMAXsv16i8
8497 { 2664, 5, 1, 4, 775, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo283, -1 ,nullptr }, // Inst #2664 = VMAXsv4i32
8498 { 2665, 5, 1, 4, 775, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo283, -1 ,nullptr }, // Inst #2665 = VMAXsv8i16
8500 { 2667, 5, 1, 4, 775, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo283, -1 ,nullptr }, // Inst #2667 = VMAXuv16i8
8503 { 2670, 5, 1, 4, 775, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo283, -1 ,nullptr }, // Inst #2670 = VMAXuv4i32
8504 { 2671, 5, 1, 4, 775, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo283, -1 ,nullptr }, // Inst #2671 = VMAXuv8i16
8507 { 2674, 5, 1, 4, 519, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo283, -1 ,nullptr }, // Inst #2674 = VMINfq
8509 { 2676, 5, 1, 4, 519, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo283, -1 ,nullptr }, // Inst #2676 = VMINhq
8510 { 2677, 5, 1, 4, 775, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo283, -1 ,nullptr }, // Inst #2677 = VMINsv16i8
8513 { 2680, 5, 1, 4, 775, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo283, -1 ,nullptr }, // Inst #2680 = VMINsv4i32
8514 { 2681, 5, 1, 4, 775, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo283, -1 ,nullptr }, // Inst #2681 = VMINsv8i16
8516 { 2683, 5, 1, 4, 775, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo283, -1 ,nullptr }, // Inst #2683 = VMINuv16i8
8519 { 2686, 5, 1, 4, 775, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo283, -1 ,nullptr }, // Inst #2686 = VMINuv4i32
8520 { 2687, 5, 1, 4, 775, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo283, -1 ,nullptr }, // Inst #2687 = VMINuv8i16
8653 { 2820, 5, 1, 4, 528, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo283, -1 ,nullptr }, // Inst #2820 = VMULfq
8655 { 2822, 5, 1, 4, 989, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo283, -1 ,nullptr }, // Inst #2822 = VMULhq
8657 { 2824, 5, 1, 4, 969, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo283, -1 ,nullptr }, // Inst #2824 = VMULpq
8666 { 2833, 5, 1, 4, 969, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo283, -1 ,nullptr }, // Inst #2833 = VMULv16i8
8669 { 2836, 5, 1, 4, 534, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo283, -1 ,nullptr }, // Inst #2836 = VMULv4i32
8670 { 2837, 5, 1, 4, 969, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo283, -1 ,nullptr }, // Inst #2837 = VMULv8i16
8701 { 2868, 5, 1, 4, 455, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo283, -1 ,nullptr }, // Inst #2868 = VORNq
8707 { 2874, 5, 1, 4, 455, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo283, -1 ,nullptr }, // Inst #2874 = VORRq
8759 { 2926, 5, 1, 4, 493, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo283, -1 ,nullptr }, // Inst #2926 = VQADDsv16i8
8762 { 2929, 5, 1, 4, 493, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo283, -1 ,nullptr }, // Inst #2929 = VQADDsv2i64
8764 { 2931, 5, 1, 4, 493, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo283, -1 ,nullptr }, // Inst #2931 = VQADDsv4i32
8765 { 2932, 5, 1, 4, 493, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo283, -1 ,nullptr }, // Inst #2932 = VQADDsv8i16
8767 { 2934, 5, 1, 4, 493, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo283, -1 ,nullptr }, // Inst #2934 = VQADDuv16i8
8770 { 2937, 5, 1, 4, 493, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo283, -1 ,nullptr }, // Inst #2937 = VQADDuv2i64
8772 { 2939, 5, 1, 4, 493, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo283, -1 ,nullptr }, // Inst #2939 = VQADDuv4i32
8773 { 2940, 5, 1, 4, 493, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo283, -1 ,nullptr }, // Inst #2940 = VQADDuv8i16
8789 { 2956, 5, 1, 4, 791, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo283, -1 ,nullptr }, // Inst #2956 = VQDMULHv4i32
8790 { 2957, 5, 1, 4, 792, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo283, -1 ,nullptr }, // Inst #2957 = VQDMULHv8i16
8832 { 2999, 5, 1, 4, 791, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo283, -1 ,nullptr }, // Inst #2999 = VQRDMULHv4i32
8833 { 3000, 5, 1, 4, 792, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo283, -1 ,nullptr }, // Inst #3000 = VQRDMULHv8i16
8834 { 3001, 5, 1, 4, 485, 0|(1ULL<<MCID::Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo283, -1 ,nullptr }, // Inst #3001 = VQRSHLsv16i8
8837 { 3004, 5, 1, 4, 485, 0|(1ULL<<MCID::Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo283, -1 ,nullptr }, // Inst #3004 = VQRSHLsv2i64
8839 { 3006, 5, 1, 4, 485, 0|(1ULL<<MCID::Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo283, -1 ,nullptr }, // Inst #3006 = VQRSHLsv4i32
8840 { 3007, 5, 1, 4, 485, 0|(1ULL<<MCID::Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo283, -1 ,nullptr }, // Inst #3007 = VQRSHLsv8i16
8842 { 3009, 5, 1, 4, 485, 0|(1ULL<<MCID::Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo283, -1 ,nullptr }, // Inst #3009 = VQRSHLuv16i8
8845 { 3012, 5, 1, 4, 485, 0|(1ULL<<MCID::Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo283, -1 ,nullptr }, // Inst #3012 = VQRSHLuv2i64
8847 { 3014, 5, 1, 4, 485, 0|(1ULL<<MCID::Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo283, -1 ,nullptr }, // Inst #3014 = VQRSHLuv4i32
8848 { 3015, 5, 1, 4, 485, 0|(1ULL<<MCID::Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo283, -1 ,nullptr }, // Inst #3015 = VQRSHLuv8i16
8875 { 3042, 5, 1, 4, 469, 0|(1ULL<<MCID::Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo283, -1 ,nullptr }, // Inst #3042 = VQSHLsv16i8
8878 { 3045, 5, 1, 4, 469, 0|(1ULL<<MCID::Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo283, -1 ,nullptr }, // Inst #3045 = VQSHLsv2i64
8880 { 3047, 5, 1, 4, 469, 0|(1ULL<<MCID::Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo283, -1 ,nullptr }, // Inst #3047 = VQSHLsv4i32
8881 { 3048, 5, 1, 4, 469, 0|(1ULL<<MCID::Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo283, -1 ,nullptr }, // Inst #3048 = VQSHLsv8i16
8891 { 3058, 5, 1, 4, 469, 0|(1ULL<<MCID::Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo283, -1 ,nullptr }, // Inst #3058 = VQSHLuv16i8
8894 { 3061, 5, 1, 4, 469, 0|(1ULL<<MCID::Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo283, -1 ,nullptr }, // Inst #3061 = VQSHLuv2i64
8896 { 3063, 5, 1, 4, 469, 0|(1ULL<<MCID::Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo283, -1 ,nullptr }, // Inst #3063 = VQSHLuv4i32
8897 { 3064, 5, 1, 4, 469, 0|(1ULL<<MCID::Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo283, -1 ,nullptr }, // Inst #3064 = VQSHLuv8i16
8908 { 3075, 5, 1, 4, 482, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo283, -1 ,nullptr }, // Inst #3075 = VQSUBsv16i8
8911 { 3078, 5, 1, 4, 482, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo283, -1 ,nullptr }, // Inst #3078 = VQSUBsv2i64
8913 { 3080, 5, 1, 4, 482, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo283, -1 ,nullptr }, // Inst #3080 = VQSUBsv4i32
8914 { 3081, 5, 1, 4, 482, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo283, -1 ,nullptr }, // Inst #3081 = VQSUBsv8i16
8916 { 3083, 5, 1, 4, 482, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo283, -1 ,nullptr }, // Inst #3083 = VQSUBuv16i8
8919 { 3086, 5, 1, 4, 482, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo283, -1 ,nullptr }, // Inst #3086 = VQSUBuv2i64
8921 { 3088, 5, 1, 4, 482, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo283, -1 ,nullptr }, // Inst #3088 = VQSUBuv4i32
8922 { 3089, 5, 1, 4, 482, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo283, -1 ,nullptr }, // Inst #3089 = VQSUBuv8i16
8934 { 3101, 5, 1, 4, 525, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo283, -1 ,nullptr }, // Inst #3101 = VRECPSfq
8936 { 3103, 5, 1, 4, 525, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo283, -1 ,nullptr }, // Inst #3103 = VRECPShq
8949 { 3116, 5, 1, 4, 962, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo283, -1 ,nullptr }, // Inst #3116 = VRHADDsv16i8
8952 { 3119, 5, 1, 4, 962, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo283, -1 ,nullptr }, // Inst #3119 = VRHADDsv4i32
8953 { 3120, 5, 1, 4, 962, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo283, -1 ,nullptr }, // Inst #3120 = VRHADDsv8i16
8955 { 3122, 5, 1, 4, 962, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo283, -1 ,nullptr }, // Inst #3122 = VRHADDuv16i8
8958 { 3125, 5, 1, 4, 962, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo283, -1 ,nullptr }, // Inst #3125 = VRHADDuv4i32
8959 { 3126, 5, 1, 4, 962, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo283, -1 ,nullptr }, // Inst #3126 = VRHADDuv8i16
9006 { 3173, 5, 1, 4, 794, 0|(1ULL<<MCID::Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo283, -1 ,nullptr }, // Inst #3173 = VRSHLsv16i8
9009 { 3176, 5, 1, 4, 794, 0|(1ULL<<MCID::Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo283, -1 ,nullptr }, // Inst #3176 = VRSHLsv2i64
9011 { 3178, 5, 1, 4, 794, 0|(1ULL<<MCID::Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo283, -1 ,nullptr }, // Inst #3178 = VRSHLsv4i32
9012 { 3179, 5, 1, 4, 794, 0|(1ULL<<MCID::Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo283, -1 ,nullptr }, // Inst #3179 = VRSHLsv8i16
9014 { 3181, 5, 1, 4, 794, 0|(1ULL<<MCID::Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo283, -1 ,nullptr }, // Inst #3181 = VRSHLuv16i8
9017 { 3184, 5, 1, 4, 794, 0|(1ULL<<MCID::Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo283, -1 ,nullptr }, // Inst #3184 = VRSHLuv2i64
9019 { 3186, 5, 1, 4, 794, 0|(1ULL<<MCID::Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo283, -1 ,nullptr }, // Inst #3186 = VRSHLuv4i32
9020 { 3187, 5, 1, 4, 794, 0|(1ULL<<MCID::Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo283, -1 ,nullptr }, // Inst #3187 = VRSHLuv8i16
9048 { 3215, 5, 1, 4, 525, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo283, -1 ,nullptr }, // Inst #3215 = VRSQRTSfq
9050 { 3217, 5, 1, 4, 525, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo283, -1 ,nullptr }, // Inst #3217 = VRSQRTShq
9108 { 3275, 5, 1, 4, 462, 0|(1ULL<<MCID::Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo283, -1 ,nullptr }, // Inst #3275 = VSHLsv16i8
9111 { 3278, 5, 1, 4, 462, 0|(1ULL<<MCID::Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo283, -1 ,nullptr }, // Inst #3278 = VSHLsv2i64
9113 { 3280, 5, 1, 4, 462, 0|(1ULL<<MCID::Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo283, -1 ,nullptr }, // Inst #3280 = VSHLsv4i32
9114 { 3281, 5, 1, 4, 462, 0|(1ULL<<MCID::Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo283, -1 ,nullptr }, // Inst #3281 = VSHLsv8i16
9116 { 3283, 5, 1, 4, 462, 0|(1ULL<<MCID::Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo283, -1 ,nullptr }, // Inst #3283 = VSHLuv16i8
9119 { 3286, 5, 1, 4, 462, 0|(1ULL<<MCID::Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo283, -1 ,nullptr }, // Inst #3286 = VSHLuv2i64
9121 { 3288, 5, 1, 4, 462, 0|(1ULL<<MCID::Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo283, -1 ,nullptr }, // Inst #3288 = VSHLuv4i32
9122 { 3289, 5, 1, 4, 462, 0|(1ULL<<MCID::Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo283, -1 ,nullptr }, // Inst #3289 = VSHLuv8i16
9472 { 3639, 5, 1, 4, 742, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo283, -1 ,nullptr }, // Inst #3639 = VSUBfq
9474 { 3641, 5, 1, 4, 743, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo283, -1 ,nullptr }, // Inst #3641 = VSUBhq
9475 { 3642, 5, 1, 4, 457, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo283, -1 ,nullptr }, // Inst #3642 = VSUBv16i8
9478 { 3645, 5, 1, 4, 457, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo283, -1 ,nullptr }, // Inst #3645 = VSUBv2i64
9480 { 3647, 5, 1, 4, 457, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo283, -1 ,nullptr }, // Inst #3647 = VSUBv4i32
9481 { 3648, 5, 1, 4, 457, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo283, -1 ,nullptr }, // Inst #3648 = VSUBv8i16
9527 { 3694, 5, 1, 4, 463, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo283, -1 ,nullptr }, // Inst #3694 = VTSTv16i8
9530 { 3697, 5, 1, 4, 463, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo283, -1 ,nullptr }, // Inst #3697 = VTSTv4i32
9531 { 3698, 5, 1, 4, 463, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo283, -1 ,nullptr }, // Inst #3698 = VTSTv8i16