|
|
reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
|
References
gen/lib/Target/ARM/ARMGenInstrInfo.inc 7732 { 1899, 5, 1, 4, 730, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo282, -1 ,nullptr }, // Inst #1899 = VABDfd
7734 { 1901, 5, 1, 4, 730, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo282, -1 ,nullptr }, // Inst #1901 = VABDhd
7737 { 1904, 5, 1, 4, 749, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo282, -1 ,nullptr }, // Inst #1904 = VABDsv2i32
7738 { 1905, 5, 1, 4, 749, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo282, -1 ,nullptr }, // Inst #1905 = VABDsv4i16
7741 { 1908, 5, 1, 4, 749, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo282, -1 ,nullptr }, // Inst #1908 = VABDsv8i8
7743 { 1910, 5, 1, 4, 749, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo282, -1 ,nullptr }, // Inst #1910 = VABDuv2i32
7744 { 1911, 5, 1, 4, 749, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo282, -1 ,nullptr }, // Inst #1911 = VABDuv4i16
7747 { 1914, 5, 1, 4, 749, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo282, -1 ,nullptr }, // Inst #1914 = VABDuv8i8
7761 { 1928, 5, 1, 4, 737, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo282, -1 ,nullptr }, // Inst #1928 = VACGEfd
7763 { 1930, 5, 1, 4, 737, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo282, -1 ,nullptr }, // Inst #1930 = VACGEhd
7765 { 1932, 5, 1, 4, 737, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo282, -1 ,nullptr }, // Inst #1932 = VACGTfd
7767 { 1934, 5, 1, 4, 737, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo282, -1 ,nullptr }, // Inst #1934 = VACGThd
7769 { 1936, 5, 1, 4, 523, 0|(1ULL<<MCID::Predicable), 0x8800ULL, nullptr, nullptr, OperandInfo282, -1 ,nullptr }, // Inst #1936 = VADDD
7787 { 1954, 5, 1, 4, 740, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo282, -1 ,nullptr }, // Inst #1954 = VADDfd
7789 { 1956, 5, 1, 4, 741, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo282, -1 ,nullptr }, // Inst #1956 = VADDhd
7792 { 1959, 5, 1, 4, 752, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo282, -1 ,nullptr }, // Inst #1959 = VADDv1i64
7793 { 1960, 5, 1, 4, 752, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo282, -1 ,nullptr }, // Inst #1960 = VADDv2i32
7795 { 1962, 5, 1, 4, 752, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo282, -1 ,nullptr }, // Inst #1962 = VADDv4i16
7798 { 1965, 5, 1, 4, 752, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo282, -1 ,nullptr }, // Inst #1965 = VADDv8i8
7799 { 1966, 5, 1, 4, 756, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo282, -1 ,nullptr }, // Inst #1966 = VANDd
7801 { 1968, 5, 1, 4, 756, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo282, -1 ,nullptr }, // Inst #1968 = VBICd
7817 { 1984, 5, 1, 4, 480, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo282, -1 ,nullptr }, // Inst #1984 = VCEQfd
7819 { 1986, 5, 1, 4, 480, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo282, -1 ,nullptr }, // Inst #1986 = VCEQhd
7822 { 1989, 5, 1, 4, 765, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo282, -1 ,nullptr }, // Inst #1989 = VCEQv2i32
7823 { 1990, 5, 1, 4, 765, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo282, -1 ,nullptr }, // Inst #1990 = VCEQv4i16
7826 { 1993, 5, 1, 4, 765, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo282, -1 ,nullptr }, // Inst #1993 = VCEQv8i8
7837 { 2004, 5, 1, 4, 480, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo282, -1 ,nullptr }, // Inst #2004 = VCGEfd
7839 { 2006, 5, 1, 4, 480, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo282, -1 ,nullptr }, // Inst #2006 = VCGEhd
7842 { 2009, 5, 1, 4, 765, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo282, -1 ,nullptr }, // Inst #2009 = VCGEsv2i32
7843 { 2010, 5, 1, 4, 765, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo282, -1 ,nullptr }, // Inst #2010 = VCGEsv4i16
7846 { 2013, 5, 1, 4, 765, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo282, -1 ,nullptr }, // Inst #2013 = VCGEsv8i8
7848 { 2015, 5, 1, 4, 765, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo282, -1 ,nullptr }, // Inst #2015 = VCGEuv2i32
7849 { 2016, 5, 1, 4, 765, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo282, -1 ,nullptr }, // Inst #2016 = VCGEuv4i16
7852 { 2019, 5, 1, 4, 765, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo282, -1 ,nullptr }, // Inst #2019 = VCGEuv8i8
7863 { 2030, 5, 1, 4, 480, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo282, -1 ,nullptr }, // Inst #2030 = VCGTfd
7865 { 2032, 5, 1, 4, 480, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo282, -1 ,nullptr }, // Inst #2032 = VCGThd
7868 { 2035, 5, 1, 4, 765, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo282, -1 ,nullptr }, // Inst #2035 = VCGTsv2i32
7869 { 2036, 5, 1, 4, 765, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo282, -1 ,nullptr }, // Inst #2036 = VCGTsv4i16
7872 { 2039, 5, 1, 4, 765, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo282, -1 ,nullptr }, // Inst #2039 = VCGTsv8i8
7874 { 2041, 5, 1, 4, 765, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo282, -1 ,nullptr }, // Inst #2041 = VCGTuv2i32
7875 { 2042, 5, 1, 4, 765, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo282, -1 ,nullptr }, // Inst #2042 = VCGTuv4i16
7878 { 2045, 5, 1, 4, 765, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo282, -1 ,nullptr }, // Inst #2045 = VCGTuv8i8
8043 { 2210, 5, 1, 4, 674, 0|(1ULL<<MCID::Predicable), 0x8800ULL, nullptr, nullptr, OperandInfo282, -1 ,nullptr }, // Inst #2210 = VDIVD
8058 { 2225, 5, 1, 4, 756, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo282, -1 ,nullptr }, // Inst #2225 = VEORd
8107 { 2274, 5, 1, 4, 773, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo282, -1 ,nullptr }, // Inst #2274 = VHADDsv2i32
8108 { 2275, 5, 1, 4, 773, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo282, -1 ,nullptr }, // Inst #2275 = VHADDsv4i16
8111 { 2278, 5, 1, 4, 773, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo282, -1 ,nullptr }, // Inst #2278 = VHADDsv8i8
8113 { 2280, 5, 1, 4, 773, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo282, -1 ,nullptr }, // Inst #2280 = VHADDuv2i32
8114 { 2281, 5, 1, 4, 773, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo282, -1 ,nullptr }, // Inst #2281 = VHADDuv4i16
8117 { 2284, 5, 1, 4, 773, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo282, -1 ,nullptr }, // Inst #2284 = VHADDuv8i8
8119 { 2286, 5, 1, 4, 466, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo282, -1 ,nullptr }, // Inst #2286 = VHSUBsv2i32
8120 { 2287, 5, 1, 4, 466, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo282, -1 ,nullptr }, // Inst #2287 = VHSUBsv4i16
8123 { 2290, 5, 1, 4, 466, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo282, -1 ,nullptr }, // Inst #2290 = VHSUBsv8i8
8125 { 2292, 5, 1, 4, 466, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo282, -1 ,nullptr }, // Inst #2292 = VHSUBuv2i32
8126 { 2293, 5, 1, 4, 466, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo282, -1 ,nullptr }, // Inst #2293 = VHSUBuv4i16
8129 { 2296, 5, 1, 4, 466, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo282, -1 ,nullptr }, // Inst #2296 = VHSUBuv8i8
8490 { 2657, 5, 1, 4, 518, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo282, -1 ,nullptr }, // Inst #2657 = VMAXfd
8492 { 2659, 5, 1, 4, 518, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo282, -1 ,nullptr }, // Inst #2659 = VMAXhd
8495 { 2662, 5, 1, 4, 953, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo282, -1 ,nullptr }, // Inst #2662 = VMAXsv2i32
8496 { 2663, 5, 1, 4, 953, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo282, -1 ,nullptr }, // Inst #2663 = VMAXsv4i16
8499 { 2666, 5, 1, 4, 953, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo282, -1 ,nullptr }, // Inst #2666 = VMAXsv8i8
8501 { 2668, 5, 1, 4, 953, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo282, -1 ,nullptr }, // Inst #2668 = VMAXuv2i32
8502 { 2669, 5, 1, 4, 953, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo282, -1 ,nullptr }, // Inst #2669 = VMAXuv4i16
8505 { 2672, 5, 1, 4, 953, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo282, -1 ,nullptr }, // Inst #2672 = VMAXuv8i8
8506 { 2673, 5, 1, 4, 518, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo282, -1 ,nullptr }, // Inst #2673 = VMINfd
8508 { 2675, 5, 1, 4, 518, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo282, -1 ,nullptr }, // Inst #2675 = VMINhd
8511 { 2678, 5, 1, 4, 953, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo282, -1 ,nullptr }, // Inst #2678 = VMINsv2i32
8512 { 2679, 5, 1, 4, 953, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo282, -1 ,nullptr }, // Inst #2679 = VMINsv4i16
8515 { 2682, 5, 1, 4, 953, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo282, -1 ,nullptr }, // Inst #2682 = VMINsv8i8
8517 { 2684, 5, 1, 4, 953, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo282, -1 ,nullptr }, // Inst #2684 = VMINuv2i32
8518 { 2685, 5, 1, 4, 953, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo282, -1 ,nullptr }, // Inst #2685 = VMINuv4i16
8521 { 2688, 5, 1, 4, 953, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo282, -1 ,nullptr }, // Inst #2688 = VMINuv8i8
8637 { 2804, 5, 1, 4, 201, 0|(1ULL<<MCID::Predicable), 0x8800ULL, nullptr, nullptr, OperandInfo282, -1 ,nullptr }, // Inst #2804 = VMULD
8652 { 2819, 5, 1, 4, 527, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo282, -1 ,nullptr }, // Inst #2819 = VMULfd
8654 { 2821, 5, 1, 4, 988, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo282, -1 ,nullptr }, // Inst #2821 = VMULhd
8656 { 2823, 5, 1, 4, 965, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo282, -1 ,nullptr }, // Inst #2823 = VMULpd
8667 { 2834, 5, 1, 4, 966, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo282, -1 ,nullptr }, // Inst #2834 = VMULv2i32
8668 { 2835, 5, 1, 4, 965, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo282, -1 ,nullptr }, // Inst #2835 = VMULv4i16
8671 { 2838, 5, 1, 4, 965, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo282, -1 ,nullptr }, // Inst #2838 = VMULv8i8
8697 { 2864, 5, 1, 4, 201, 0|(1ULL<<MCID::Predicable), 0x8800ULL, nullptr, nullptr, OperandInfo282, -1 ,nullptr }, // Inst #2864 = VNMULD
8700 { 2867, 5, 1, 4, 456, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo282, -1 ,nullptr }, // Inst #2867 = VORNd
8702 { 2869, 5, 1, 4, 456, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo282, -1 ,nullptr }, // Inst #2869 = VORRd
8732 { 2899, 5, 1, 4, 522, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo282, -1 ,nullptr }, // Inst #2899 = VPADDf
8733 { 2900, 5, 1, 4, 982, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo282, -1 ,nullptr }, // Inst #2900 = VPADDh
8734 { 2901, 5, 1, 4, 782, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo282, -1 ,nullptr }, // Inst #2901 = VPADDi16
8735 { 2902, 5, 1, 4, 782, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo282, -1 ,nullptr }, // Inst #2902 = VPADDi32
8736 { 2903, 5, 1, 4, 782, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo282, -1 ,nullptr }, // Inst #2903 = VPADDi8
8737 { 2904, 5, 1, 4, 776, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo282, -1 ,nullptr }, // Inst #2904 = VPMAXf
8738 { 2905, 5, 1, 4, 776, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo282, -1 ,nullptr }, // Inst #2905 = VPMAXh
8739 { 2906, 5, 1, 4, 521, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo282, -1 ,nullptr }, // Inst #2906 = VPMAXs16
8740 { 2907, 5, 1, 4, 521, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo282, -1 ,nullptr }, // Inst #2907 = VPMAXs32
8741 { 2908, 5, 1, 4, 521, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo282, -1 ,nullptr }, // Inst #2908 = VPMAXs8
8742 { 2909, 5, 1, 4, 521, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo282, -1 ,nullptr }, // Inst #2909 = VPMAXu16
8743 { 2910, 5, 1, 4, 521, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo282, -1 ,nullptr }, // Inst #2910 = VPMAXu32
8744 { 2911, 5, 1, 4, 521, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo282, -1 ,nullptr }, // Inst #2911 = VPMAXu8
8745 { 2912, 5, 1, 4, 776, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo282, -1 ,nullptr }, // Inst #2912 = VPMINf
8746 { 2913, 5, 1, 4, 776, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo282, -1 ,nullptr }, // Inst #2913 = VPMINh
8747 { 2914, 5, 1, 4, 521, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo282, -1 ,nullptr }, // Inst #2914 = VPMINs16
8748 { 2915, 5, 1, 4, 521, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo282, -1 ,nullptr }, // Inst #2915 = VPMINs32
8749 { 2916, 5, 1, 4, 521, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo282, -1 ,nullptr }, // Inst #2916 = VPMINs8
8750 { 2917, 5, 1, 4, 521, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo282, -1 ,nullptr }, // Inst #2917 = VPMINu16
8751 { 2918, 5, 1, 4, 521, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo282, -1 ,nullptr }, // Inst #2918 = VPMINu32
8752 { 2919, 5, 1, 4, 521, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo282, -1 ,nullptr }, // Inst #2919 = VPMINu8
8760 { 2927, 5, 1, 4, 494, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo282, -1 ,nullptr }, // Inst #2927 = VQADDsv1i64
8761 { 2928, 5, 1, 4, 494, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo282, -1 ,nullptr }, // Inst #2928 = VQADDsv2i32
8763 { 2930, 5, 1, 4, 494, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo282, -1 ,nullptr }, // Inst #2930 = VQADDsv4i16
8766 { 2933, 5, 1, 4, 494, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo282, -1 ,nullptr }, // Inst #2933 = VQADDsv8i8
8768 { 2935, 5, 1, 4, 494, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo282, -1 ,nullptr }, // Inst #2935 = VQADDuv1i64
8769 { 2936, 5, 1, 4, 494, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo282, -1 ,nullptr }, // Inst #2936 = VQADDuv2i32
8771 { 2938, 5, 1, 4, 494, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo282, -1 ,nullptr }, // Inst #2938 = VQADDuv4i16
8774 { 2941, 5, 1, 4, 494, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo282, -1 ,nullptr }, // Inst #2941 = VQADDuv8i8
8787 { 2954, 5, 1, 4, 967, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo282, -1 ,nullptr }, // Inst #2954 = VQDMULHv2i32
8788 { 2955, 5, 1, 4, 968, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo282, -1 ,nullptr }, // Inst #2955 = VQDMULHv4i16
8830 { 2997, 5, 1, 4, 967, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo282, -1 ,nullptr }, // Inst #2997 = VQRDMULHv2i32
8831 { 2998, 5, 1, 4, 968, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo282, -1 ,nullptr }, // Inst #2998 = VQRDMULHv4i16
8835 { 3002, 5, 1, 4, 486, 0|(1ULL<<MCID::Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo282, -1 ,nullptr }, // Inst #3002 = VQRSHLsv1i64
8836 { 3003, 5, 1, 4, 486, 0|(1ULL<<MCID::Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo282, -1 ,nullptr }, // Inst #3003 = VQRSHLsv2i32
8838 { 3005, 5, 1, 4, 486, 0|(1ULL<<MCID::Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo282, -1 ,nullptr }, // Inst #3005 = VQRSHLsv4i16
8841 { 3008, 5, 1, 4, 486, 0|(1ULL<<MCID::Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo282, -1 ,nullptr }, // Inst #3008 = VQRSHLsv8i8
8843 { 3010, 5, 1, 4, 486, 0|(1ULL<<MCID::Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo282, -1 ,nullptr }, // Inst #3010 = VQRSHLuv1i64
8844 { 3011, 5, 1, 4, 486, 0|(1ULL<<MCID::Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo282, -1 ,nullptr }, // Inst #3011 = VQRSHLuv2i32
8846 { 3013, 5, 1, 4, 486, 0|(1ULL<<MCID::Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo282, -1 ,nullptr }, // Inst #3013 = VQRSHLuv4i16
8849 { 3016, 5, 1, 4, 486, 0|(1ULL<<MCID::Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo282, -1 ,nullptr }, // Inst #3016 = VQRSHLuv8i8
8876 { 3043, 5, 1, 4, 468, 0|(1ULL<<MCID::Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo282, -1 ,nullptr }, // Inst #3043 = VQSHLsv1i64
8877 { 3044, 5, 1, 4, 468, 0|(1ULL<<MCID::Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo282, -1 ,nullptr }, // Inst #3044 = VQSHLsv2i32
8879 { 3046, 5, 1, 4, 468, 0|(1ULL<<MCID::Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo282, -1 ,nullptr }, // Inst #3046 = VQSHLsv4i16
8882 { 3049, 5, 1, 4, 468, 0|(1ULL<<MCID::Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo282, -1 ,nullptr }, // Inst #3049 = VQSHLsv8i8
8892 { 3059, 5, 1, 4, 468, 0|(1ULL<<MCID::Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo282, -1 ,nullptr }, // Inst #3059 = VQSHLuv1i64
8893 { 3060, 5, 1, 4, 468, 0|(1ULL<<MCID::Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo282, -1 ,nullptr }, // Inst #3060 = VQSHLuv2i32
8895 { 3062, 5, 1, 4, 468, 0|(1ULL<<MCID::Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo282, -1 ,nullptr }, // Inst #3062 = VQSHLuv4i16
8898 { 3065, 5, 1, 4, 468, 0|(1ULL<<MCID::Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo282, -1 ,nullptr }, // Inst #3065 = VQSHLuv8i8
8909 { 3076, 5, 1, 4, 483, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo282, -1 ,nullptr }, // Inst #3076 = VQSUBsv1i64
8910 { 3077, 5, 1, 4, 483, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo282, -1 ,nullptr }, // Inst #3077 = VQSUBsv2i32
8912 { 3079, 5, 1, 4, 483, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo282, -1 ,nullptr }, // Inst #3079 = VQSUBsv4i16
8915 { 3082, 5, 1, 4, 483, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo282, -1 ,nullptr }, // Inst #3082 = VQSUBsv8i8
8917 { 3084, 5, 1, 4, 483, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo282, -1 ,nullptr }, // Inst #3084 = VQSUBuv1i64
8918 { 3085, 5, 1, 4, 483, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo282, -1 ,nullptr }, // Inst #3085 = VQSUBuv2i32
8920 { 3087, 5, 1, 4, 483, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo282, -1 ,nullptr }, // Inst #3087 = VQSUBuv4i16
8923 { 3090, 5, 1, 4, 483, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo282, -1 ,nullptr }, // Inst #3090 = VQSUBuv8i8
8933 { 3100, 5, 1, 4, 524, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo282, -1 ,nullptr }, // Inst #3100 = VRECPSfd
8935 { 3102, 5, 1, 4, 524, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo282, -1 ,nullptr }, // Inst #3102 = VRECPShd
8950 { 3117, 5, 1, 4, 963, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo282, -1 ,nullptr }, // Inst #3117 = VRHADDsv2i32
8951 { 3118, 5, 1, 4, 963, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo282, -1 ,nullptr }, // Inst #3118 = VRHADDsv4i16
8954 { 3121, 5, 1, 4, 963, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo282, -1 ,nullptr }, // Inst #3121 = VRHADDsv8i8
8956 { 3123, 5, 1, 4, 963, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo282, -1 ,nullptr }, // Inst #3123 = VRHADDuv2i32
8957 { 3124, 5, 1, 4, 963, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo282, -1 ,nullptr }, // Inst #3124 = VRHADDuv4i16
8960 { 3127, 5, 1, 4, 963, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo282, -1 ,nullptr }, // Inst #3127 = VRHADDuv8i8
9007 { 3174, 5, 1, 4, 795, 0|(1ULL<<MCID::Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo282, -1 ,nullptr }, // Inst #3174 = VRSHLsv1i64
9008 { 3175, 5, 1, 4, 795, 0|(1ULL<<MCID::Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo282, -1 ,nullptr }, // Inst #3175 = VRSHLsv2i32
9010 { 3177, 5, 1, 4, 795, 0|(1ULL<<MCID::Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo282, -1 ,nullptr }, // Inst #3177 = VRSHLsv4i16
9013 { 3180, 5, 1, 4, 795, 0|(1ULL<<MCID::Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo282, -1 ,nullptr }, // Inst #3180 = VRSHLsv8i8
9015 { 3182, 5, 1, 4, 795, 0|(1ULL<<MCID::Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo282, -1 ,nullptr }, // Inst #3182 = VRSHLuv1i64
9016 { 3183, 5, 1, 4, 795, 0|(1ULL<<MCID::Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo282, -1 ,nullptr }, // Inst #3183 = VRSHLuv2i32
9018 { 3185, 5, 1, 4, 795, 0|(1ULL<<MCID::Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo282, -1 ,nullptr }, // Inst #3185 = VRSHLuv4i16
9021 { 3188, 5, 1, 4, 795, 0|(1ULL<<MCID::Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo282, -1 ,nullptr }, // Inst #3188 = VRSHLuv8i8
9047 { 3214, 5, 1, 4, 524, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo282, -1 ,nullptr }, // Inst #3214 = VRSQRTSfd
9049 { 3216, 5, 1, 4, 524, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo282, -1 ,nullptr }, // Inst #3216 = VRSQRTShd
9109 { 3276, 5, 1, 4, 461, 0|(1ULL<<MCID::Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo282, -1 ,nullptr }, // Inst #3276 = VSHLsv1i64
9110 { 3277, 5, 1, 4, 461, 0|(1ULL<<MCID::Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo282, -1 ,nullptr }, // Inst #3277 = VSHLsv2i32
9112 { 3279, 5, 1, 4, 461, 0|(1ULL<<MCID::Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo282, -1 ,nullptr }, // Inst #3279 = VSHLsv4i16
9115 { 3282, 5, 1, 4, 461, 0|(1ULL<<MCID::Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo282, -1 ,nullptr }, // Inst #3282 = VSHLsv8i8
9117 { 3284, 5, 1, 4, 461, 0|(1ULL<<MCID::Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo282, -1 ,nullptr }, // Inst #3284 = VSHLuv1i64
9118 { 3285, 5, 1, 4, 461, 0|(1ULL<<MCID::Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo282, -1 ,nullptr }, // Inst #3285 = VSHLuv2i32
9120 { 3287, 5, 1, 4, 461, 0|(1ULL<<MCID::Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo282, -1 ,nullptr }, // Inst #3287 = VSHLuv4i16
9123 { 3290, 5, 1, 4, 461, 0|(1ULL<<MCID::Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo282, -1 ,nullptr }, // Inst #3290 = VSHLuv8i8
9453 { 3620, 5, 1, 4, 523, 0|(1ULL<<MCID::Predicable), 0x8800ULL, nullptr, nullptr, OperandInfo282, -1 ,nullptr }, // Inst #3620 = VSUBD
9471 { 3638, 5, 1, 4, 740, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo282, -1 ,nullptr }, // Inst #3638 = VSUBfd
9473 { 3640, 5, 1, 4, 741, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo282, -1 ,nullptr }, // Inst #3640 = VSUBhd
9476 { 3643, 5, 1, 4, 753, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo282, -1 ,nullptr }, // Inst #3643 = VSUBv1i64
9477 { 3644, 5, 1, 4, 753, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo282, -1 ,nullptr }, // Inst #3644 = VSUBv2i32
9479 { 3646, 5, 1, 4, 753, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo282, -1 ,nullptr }, // Inst #3646 = VSUBv4i16
9482 { 3649, 5, 1, 4, 753, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo282, -1 ,nullptr }, // Inst #3649 = VSUBv8i8
9485 { 3652, 5, 1, 4, 501, 0|(1ULL<<MCID::Predicable), 0x11480ULL, nullptr, nullptr, OperandInfo282, -1 ,nullptr }, // Inst #3652 = VTBL1
9487 { 3654, 5, 1, 4, 505, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x11480ULL, nullptr, nullptr, OperandInfo282, -1 ,nullptr }, // Inst #3654 = VTBL3
9489 { 3656, 5, 1, 4, 507, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x11480ULL, nullptr, nullptr, OperandInfo282, -1 ,nullptr }, // Inst #3656 = VTBL4
9528 { 3695, 5, 1, 4, 464, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo282, -1 ,nullptr }, // Inst #3695 = VTSTv2i32
9529 { 3696, 5, 1, 4, 464, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo282, -1 ,nullptr }, // Inst #3696 = VTSTv4i16
9532 { 3699, 5, 1, 4, 464, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo282, -1 ,nullptr }, // Inst #3699 = VTSTv8i8