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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/ARM/ARMGenInstrInfo.inc 7482 { 1649, 5, 1, 4, 891, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x200ULL, nullptr, nullptr, OperandInfo257, -1 ,nullptr }, // Inst #1649 = QADD
7483 { 1650, 5, 1, 4, 886, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x200ULL, nullptr, nullptr, OperandInfo257, -1 ,nullptr }, // Inst #1650 = QADD16
7484 { 1651, 5, 1, 4, 886, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x200ULL, nullptr, nullptr, OperandInfo257, -1 ,nullptr }, // Inst #1651 = QADD8
7485 { 1652, 5, 1, 4, 888, 0|(1ULL<<MCID::Predicable), 0x200ULL, nullptr, nullptr, OperandInfo257, -1 ,nullptr }, // Inst #1652 = QASX
7486 { 1653, 5, 1, 4, 360, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x200ULL, nullptr, nullptr, OperandInfo257, -1 ,nullptr }, // Inst #1653 = QDADD
7487 { 1654, 5, 1, 4, 360, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x200ULL, nullptr, nullptr, OperandInfo257, -1 ,nullptr }, // Inst #1654 = QDSUB
7488 { 1655, 5, 1, 4, 888, 0|(1ULL<<MCID::Predicable), 0x200ULL, nullptr, nullptr, OperandInfo257, -1 ,nullptr }, // Inst #1655 = QSAX
7489 { 1656, 5, 1, 4, 891, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x200ULL, nullptr, nullptr, OperandInfo257, -1 ,nullptr }, // Inst #1656 = QSUB
7490 { 1657, 5, 1, 4, 886, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x200ULL, nullptr, nullptr, OperandInfo257, -1 ,nullptr }, // Inst #1657 = QSUB16
7491 { 1658, 5, 1, 4, 886, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x200ULL, nullptr, nullptr, OperandInfo257, -1 ,nullptr }, // Inst #1658 = QSUB8
7512 { 1679, 5, 1, 4, 882, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x200ULL, nullptr, nullptr, OperandInfo257, -1 ,nullptr }, // Inst #1679 = SADD16
7513 { 1680, 5, 1, 4, 882, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x200ULL, nullptr, nullptr, OperandInfo257, -1 ,nullptr }, // Inst #1680 = SADD8
7514 { 1681, 5, 1, 4, 363, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x200ULL, nullptr, nullptr, OperandInfo257, -1 ,nullptr }, // Inst #1681 = SASX
7535 { 1702, 5, 1, 4, 884, 0|(1ULL<<MCID::Predicable), 0x200ULL, nullptr, nullptr, OperandInfo257, -1 ,nullptr }, // Inst #1702 = SHADD16
7536 { 1703, 5, 1, 4, 884, 0|(1ULL<<MCID::Predicable), 0x200ULL, nullptr, nullptr, OperandInfo257, -1 ,nullptr }, // Inst #1703 = SHADD8
7537 { 1704, 5, 1, 4, 365, 0|(1ULL<<MCID::Predicable), 0x200ULL, nullptr, nullptr, OperandInfo257, -1 ,nullptr }, // Inst #1704 = SHASX
7538 { 1705, 5, 1, 4, 365, 0|(1ULL<<MCID::Predicable), 0x200ULL, nullptr, nullptr, OperandInfo257, -1 ,nullptr }, // Inst #1705 = SHSAX
7539 { 1706, 5, 1, 4, 884, 0|(1ULL<<MCID::Predicable), 0x200ULL, nullptr, nullptr, OperandInfo257, -1 ,nullptr }, // Inst #1706 = SHSUB16
7540 { 1707, 5, 1, 4, 884, 0|(1ULL<<MCID::Predicable), 0x200ULL, nullptr, nullptr, OperandInfo257, -1 ,nullptr }, // Inst #1707 = SHSUB8
7567 { 1734, 5, 1, 4, 344, 0|(1ULL<<MCID::Predicable), 0x80ULL, nullptr, nullptr, OperandInfo257, -1 ,nullptr }, // Inst #1734 = SMUAD
7568 { 1735, 5, 1, 4, 344, 0|(1ULL<<MCID::Predicable), 0x80ULL, nullptr, nullptr, OperandInfo257, -1 ,nullptr }, // Inst #1735 = SMUADX
7576 { 1743, 5, 1, 4, 371, 0|(1ULL<<MCID::Predicable), 0x80ULL, nullptr, nullptr, OperandInfo257, -1 ,nullptr }, // Inst #1743 = SMUSD
7577 { 1744, 5, 1, 4, 371, 0|(1ULL<<MCID::Predicable), 0x80ULL, nullptr, nullptr, OperandInfo257, -1 ,nullptr }, // Inst #1744 = SMUSDX
7588 { 1755, 5, 1, 4, 363, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x200ULL, nullptr, nullptr, OperandInfo257, -1 ,nullptr }, // Inst #1755 = SSAX
7589 { 1756, 5, 1, 4, 882, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x200ULL, nullptr, nullptr, OperandInfo257, -1 ,nullptr }, // Inst #1756 = SSUB16
7590 { 1757, 5, 1, 4, 882, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x200ULL, nullptr, nullptr, OperandInfo257, -1 ,nullptr }, // Inst #1757 = SSUB8
7674 { 1841, 5, 1, 4, 882, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x200ULL, nullptr, nullptr, OperandInfo257, -1 ,nullptr }, // Inst #1841 = UADD16
7675 { 1842, 5, 1, 4, 882, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x200ULL, nullptr, nullptr, OperandInfo257, -1 ,nullptr }, // Inst #1842 = UADD8
7676 { 1843, 5, 1, 4, 363, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x200ULL, nullptr, nullptr, OperandInfo257, -1 ,nullptr }, // Inst #1843 = UASX
7680 { 1847, 5, 1, 4, 884, 0|(1ULL<<MCID::Predicable), 0x200ULL, nullptr, nullptr, OperandInfo257, -1 ,nullptr }, // Inst #1847 = UHADD16
7681 { 1848, 5, 1, 4, 884, 0|(1ULL<<MCID::Predicable), 0x200ULL, nullptr, nullptr, OperandInfo257, -1 ,nullptr }, // Inst #1848 = UHADD8
7682 { 1849, 5, 1, 4, 365, 0|(1ULL<<MCID::Predicable), 0x200ULL, nullptr, nullptr, OperandInfo257, -1 ,nullptr }, // Inst #1849 = UHASX
7683 { 1850, 5, 1, 4, 365, 0|(1ULL<<MCID::Predicable), 0x200ULL, nullptr, nullptr, OperandInfo257, -1 ,nullptr }, // Inst #1850 = UHSAX
7684 { 1851, 5, 1, 4, 884, 0|(1ULL<<MCID::Predicable), 0x200ULL, nullptr, nullptr, OperandInfo257, -1 ,nullptr }, // Inst #1851 = UHSUB16
7685 { 1852, 5, 1, 4, 884, 0|(1ULL<<MCID::Predicable), 0x200ULL, nullptr, nullptr, OperandInfo257, -1 ,nullptr }, // Inst #1852 = UHSUB8
7689 { 1856, 5, 1, 4, 886, 0|(1ULL<<MCID::Predicable), 0x200ULL, nullptr, nullptr, OperandInfo257, -1 ,nullptr }, // Inst #1856 = UQADD16
7690 { 1857, 5, 1, 4, 886, 0|(1ULL<<MCID::Predicable), 0x200ULL, nullptr, nullptr, OperandInfo257, -1 ,nullptr }, // Inst #1857 = UQADD8
7691 { 1858, 5, 1, 4, 888, 0|(1ULL<<MCID::Predicable), 0x200ULL, nullptr, nullptr, OperandInfo257, -1 ,nullptr }, // Inst #1858 = UQASX
7692 { 1859, 5, 1, 4, 888, 0|(1ULL<<MCID::Predicable), 0x200ULL, nullptr, nullptr, OperandInfo257, -1 ,nullptr }, // Inst #1859 = UQSAX
7693 { 1860, 5, 1, 4, 886, 0|(1ULL<<MCID::Predicable), 0x200ULL, nullptr, nullptr, OperandInfo257, -1 ,nullptr }, // Inst #1860 = UQSUB16
7694 { 1861, 5, 1, 4, 886, 0|(1ULL<<MCID::Predicable), 0x200ULL, nullptr, nullptr, OperandInfo257, -1 ,nullptr }, // Inst #1861 = UQSUB8
7699 { 1866, 5, 1, 4, 363, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x200ULL, nullptr, nullptr, OperandInfo257, -1 ,nullptr }, // Inst #1866 = USAX
7700 { 1867, 5, 1, 4, 882, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x200ULL, nullptr, nullptr, OperandInfo257, -1 ,nullptr }, // Inst #1867 = USUB16
7701 { 1868, 5, 1, 4, 882, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x200ULL, nullptr, nullptr, OperandInfo257, -1 ,nullptr }, // Inst #1868 = USUB8