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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/ARM/ARMGenInstrInfo.inc 6596 { 763, 3, 1, 4, 724, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo177, -1 ,nullptr }, // Inst #763 = MRS
6598 { 765, 3, 1, 4, 724, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo177, -1 ,nullptr }, // Inst #765 = MRSsys
8488 { 2655, 3, 0, 4, 930, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8b84ULL, nullptr, nullptr, OperandInfo177, -1 ,nullptr }, // Inst #2655 = VLLDM
8489 { 2656, 3, 0, 4, 947, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8b84ULL, nullptr, nullptr, OperandInfo177, -1 ,nullptr }, // Inst #2656 = VLSTM
8614 { 2781, 3, 1, 4, 582, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8c00ULL, ImplicitList13, nullptr, OperandInfo177, -1 ,nullptr }, // Inst #2781 = VMRS
8617 { 2784, 3, 1, 4, 582, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8c00ULL, ImplicitList13, nullptr, OperandInfo177, -1 ,nullptr }, // Inst #2784 = VMRS_FPEXC
8618 { 2785, 3, 1, 4, 582, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8c00ULL, ImplicitList13, nullptr, OperandInfo177, -1 ,nullptr }, // Inst #2785 = VMRS_FPINST
8619 { 2786, 3, 1, 4, 582, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8c00ULL, ImplicitList13, nullptr, OperandInfo177, -1 ,nullptr }, // Inst #2786 = VMRS_FPINST2
8621 { 2788, 3, 1, 4, 582, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8c00ULL, ImplicitList13, nullptr, OperandInfo177, -1 ,nullptr }, // Inst #2788 = VMRS_FPSID
8622 { 2789, 3, 1, 4, 582, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8c00ULL, ImplicitList13, nullptr, OperandInfo177, -1 ,nullptr }, // Inst #2789 = VMRS_MVFR0
8623 { 2790, 3, 1, 4, 582, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8c00ULL, ImplicitList13, nullptr, OperandInfo177, -1 ,nullptr }, // Inst #2790 = VMRS_MVFR1
8624 { 2791, 3, 1, 4, 582, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8c00ULL, ImplicitList13, nullptr, OperandInfo177, -1 ,nullptr }, // Inst #2791 = VMRS_MVFR2
8627 { 2794, 3, 0, 4, 583, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8c00ULL, nullptr, ImplicitList13, OperandInfo177, -1 ,nullptr }, // Inst #2794 = VMSR
8630 { 2797, 3, 0, 4, 583, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8c00ULL, nullptr, ImplicitList13, OperandInfo177, -1 ,nullptr }, // Inst #2797 = VMSR_FPEXC
8631 { 2798, 3, 0, 4, 583, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8c00ULL, nullptr, ImplicitList13, OperandInfo177, -1 ,nullptr }, // Inst #2798 = VMSR_FPINST
8632 { 2799, 3, 0, 4, 583, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8c00ULL, nullptr, ImplicitList13, OperandInfo177, -1 ,nullptr }, // Inst #2799 = VMSR_FPINST2
8634 { 2801, 3, 0, 4, 583, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8c00ULL, nullptr, ImplicitList13, OperandInfo177, -1 ,nullptr }, // Inst #2801 = VMSR_FPSID
9596 { 3763, 3, 0, 4, 861, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo177, -1 ,nullptr }, // Inst #3763 = t2BXJ