|
|
reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
|
References
gen/lib/Target/ARM/ARMGenInstrInfo.inc 6543 { 710, 6, 2, 4, 907, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0x322ULL, nullptr, nullptr, OperandInfo153, -1 ,nullptr }, // Inst #710 = LDRB_PRE_IMM
6555 { 722, 6, 2, 4, 920, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0x443ULL, nullptr, nullptr, OperandInfo153, -1 ,nullptr }, // Inst #722 = LDRHTi
6560 { 727, 6, 2, 4, 921, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0x443ULL, nullptr, nullptr, OperandInfo153, -1 ,nullptr }, // Inst #727 = LDRSBTi
6565 { 732, 6, 2, 4, 921, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0x443ULL, nullptr, nullptr, OperandInfo153, -1 ,nullptr }, // Inst #732 = LDRSHTi
6573 { 740, 6, 2, 4, 906, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0x322ULL, nullptr, nullptr, OperandInfo153, -1 ,nullptr }, // Inst #740 = LDR_PRE_IMM
9666 { 3833, 6, 2, 4, 922, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0xcccULL, nullptr, nullptr, OperandInfo153, -1 ,nullptr }, // Inst #3833 = t2LDRB_POST
9667 { 3834, 6, 2, 4, 908, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0xcacULL, nullptr, nullptr, OperandInfo153, -1 ,nullptr }, // Inst #3834 = t2LDRB_PRE
9680 { 3847, 6, 2, 4, 407, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0xcccULL, nullptr, nullptr, OperandInfo153, -1 ,nullptr }, // Inst #3847 = t2LDRH_POST
9681 { 3848, 6, 2, 4, 913, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0xcacULL, nullptr, nullptr, OperandInfo153, -1 ,nullptr }, // Inst #3848 = t2LDRH_PRE
9687 { 3854, 6, 2, 4, 411, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0xcccULL, nullptr, nullptr, OperandInfo153, -1 ,nullptr }, // Inst #3854 = t2LDRSB_POST
9688 { 3855, 6, 2, 4, 914, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0xcacULL, nullptr, nullptr, OperandInfo153, -1 ,nullptr }, // Inst #3855 = t2LDRSB_PRE
9694 { 3861, 6, 2, 4, 411, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0xcccULL, nullptr, nullptr, OperandInfo153, -1 ,nullptr }, // Inst #3861 = t2LDRSH_POST
9695 { 3862, 6, 2, 4, 914, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0xcacULL, nullptr, nullptr, OperandInfo153, -1 ,nullptr }, // Inst #3862 = t2LDRSH_PRE
9701 { 3868, 6, 2, 4, 408, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0xcccULL, nullptr, nullptr, OperandInfo153, -1 ,nullptr }, // Inst #3868 = t2LDR_POST
9702 { 3869, 6, 2, 4, 915, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0xcacULL, nullptr, nullptr, OperandInfo153, -1 ,nullptr }, // Inst #3869 = t2LDR_PRE