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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/ARM/ARMGenInstrInfo.inc 6498 { 665, 4, 0, 4, 848, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x8b04ULL, nullptr, nullptr, OperandInfo146, -1 ,nullptr }, // Inst #665 = FLDMXIA
6502 { 669, 4, 0, 4, 848, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x8b04ULL, nullptr, nullptr, OperandInfo146, -1 ,nullptr }, // Inst #669 = FSTMXIA
6531 { 698, 4, 0, 4, 417, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::VariadicOpsAreDefs), 0x504ULL, nullptr, nullptr, OperandInfo146, -1 ,&getARMLoadDeprecationInfo }, // Inst #698 = LDMDA
6533 { 700, 4, 0, 4, 417, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::VariadicOpsAreDefs), 0x504ULL, nullptr, nullptr, OperandInfo146, -1 ,&getARMLoadDeprecationInfo }, // Inst #700 = LDMDB
6535 { 702, 4, 0, 4, 417, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::VariadicOpsAreDefs), 0x504ULL, nullptr, nullptr, OperandInfo146, -1 ,&getARMLoadDeprecationInfo }, // Inst #702 = LDMIA
6537 { 704, 4, 0, 4, 417, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::VariadicOpsAreDefs), 0x504ULL, nullptr, nullptr, OperandInfo146, -1 ,&getARMLoadDeprecationInfo }, // Inst #704 = LDMIB
7614 { 1781, 4, 0, 4, 447, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x504ULL, nullptr, nullptr, OperandInfo146, -1 ,&getARMStoreDeprecationInfo }, // Inst #1781 = STMDA
7616 { 1783, 4, 0, 4, 447, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x504ULL, nullptr, nullptr, OperandInfo146, -1 ,&getARMStoreDeprecationInfo }, // Inst #1783 = STMDB
7618 { 1785, 4, 0, 4, 447, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x504ULL, nullptr, nullptr, OperandInfo146, -1 ,&getARMStoreDeprecationInfo }, // Inst #1785 = STMIA
7620 { 1787, 4, 0, 4, 447, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x504ULL, nullptr, nullptr, OperandInfo146, -1 ,&getARMStoreDeprecationInfo }, // Inst #1787 = STMIB
8461 { 2628, 4, 0, 4, 591, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x8b84ULL, nullptr, nullptr, OperandInfo146, -1 ,nullptr }, // Inst #2628 = VLDMDIA
8465 { 2632, 4, 0, 4, 591, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x18b84ULL, nullptr, nullptr, OperandInfo146, -1 ,nullptr }, // Inst #2632 = VLDMSIA
9426 { 3593, 4, 0, 4, 593, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x8b84ULL, nullptr, nullptr, OperandInfo146, -1 ,nullptr }, // Inst #3593 = VSTMDIA
9430 { 3597, 4, 0, 4, 960, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x18b84ULL, nullptr, nullptr, OperandInfo146, -1 ,nullptr }, // Inst #3597 = VSTMSIA
9556 { 3723, 4, 0, 4, 417, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x504ULL, nullptr, nullptr, OperandInfo146, -1 ,nullptr }, // Inst #3723 = sysLDMDA
9558 { 3725, 4, 0, 4, 417, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x504ULL, nullptr, nullptr, OperandInfo146, -1 ,nullptr }, // Inst #3725 = sysLDMDB
9560 { 3727, 4, 0, 4, 417, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x504ULL, nullptr, nullptr, OperandInfo146, -1 ,nullptr }, // Inst #3727 = sysLDMIA
9562 { 3729, 4, 0, 4, 417, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x504ULL, nullptr, nullptr, OperandInfo146, -1 ,nullptr }, // Inst #3729 = sysLDMIB
9564 { 3731, 4, 0, 4, 447, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x504ULL, nullptr, nullptr, OperandInfo146, -1 ,nullptr }, // Inst #3731 = sysSTMDA
9566 { 3733, 4, 0, 4, 447, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x504ULL, nullptr, nullptr, OperandInfo146, -1 ,nullptr }, // Inst #3733 = sysSTMDB
9568 { 3735, 4, 0, 4, 447, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x504ULL, nullptr, nullptr, OperandInfo146, -1 ,nullptr }, // Inst #3735 = sysSTMIA
9570 { 3737, 4, 0, 4, 447, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x504ULL, nullptr, nullptr, OperandInfo146, -1 ,nullptr }, // Inst #3737 = sysSTMIB
9661 { 3828, 4, 0, 4, 1009, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::VariadicOpsAreDefs), 0xc80ULL, nullptr, nullptr, OperandInfo146, -1 ,nullptr }, // Inst #3828 = t2LDMDB
9663 { 3830, 4, 0, 4, 1009, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::VariadicOpsAreDefs), 0xc80ULL, nullptr, nullptr, OperandInfo146, -1 ,nullptr }, // Inst #3830 = t2LDMIA
9870 { 4037, 4, 0, 4, 1014, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc80ULL, nullptr, nullptr, OperandInfo146, -1 ,nullptr }, // Inst #4037 = t2STMDB
9872 { 4039, 4, 0, 4, 1014, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc80ULL, nullptr, nullptr, OperandInfo146, -1 ,nullptr }, // Inst #4039 = t2STMIA