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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/ARM/ARMGenInstrInfo.inc 6486 { 653, 3, 0, 4, 841, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xd00ULL, nullptr, nullptr, OperandInfo142, -1 ,nullptr }, // Inst #653 = DBG
6504 { 671, 3, 0, 4, 841, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xd00ULL, nullptr, nullptr, OperandInfo142, -1 ,nullptr }, // Inst #671 = HINT
7541 { 1708, 3, 0, 4, 841, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo142, -1 ,nullptr }, // Inst #1708 = SMC
7654 { 1821, 3, 0, 4, 842, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL, ImplicitList2, nullptr, OperandInfo142, -1 ,nullptr }, // Inst #1821 = SVC
9622 { 3789, 3, 0, 4, 1027, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo142, -1 ,nullptr }, // Inst #3789 = t2DBG
9627 { 3794, 3, 0, 4, 1025, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo142, -1 ,nullptr }, // Inst #3794 = t2DMB
9628 { 3795, 3, 0, 4, 1025, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo142, -1 ,nullptr }, // Inst #3795 = t2DSB
9632 { 3799, 3, 0, 4, 1025, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo142, -1 ,nullptr }, // Inst #3799 = t2HINT
9634 { 3801, 3, 0, 4, 1025, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo142, -1 ,nullptr }, // Inst #3801 = t2ISB
9753 { 3920, 3, 0, 4, 928, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0xc8dULL, nullptr, nullptr, OperandInfo142, -1 ,nullptr }, // Inst #3920 = t2PLDpci
9757 { 3924, 3, 0, 4, 928, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0xc8dULL, nullptr, nullptr, OperandInfo142, -1 ,nullptr }, // Inst #3924 = t2PLIpci
9801 { 3968, 3, 0, 4, 841, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, ImplicitList2, nullptr, OperandInfo142, -1 ,nullptr }, // Inst #3968 = t2SMC
9838 { 4005, 3, 0, 4, 726, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo142, -1 ,nullptr }, // Inst #4005 = t2SRSDB
9839 { 4006, 3, 0, 4, 726, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo142, -1 ,nullptr }, // Inst #4006 = t2SRSDB_UPD
9840 { 4007, 3, 0, 4, 726, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo142, -1 ,nullptr }, // Inst #4007 = t2SRSIA
9841 { 4008, 3, 0, 4, 726, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo142, -1 ,nullptr }, // Inst #4008 = t2SRSIA_UPD
9899 { 4066, 3, 0, 4, 849, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Terminator), 0xc80ULL, nullptr, ImplicitList10, OperandInfo142, -1 ,nullptr }, // Inst #4066 = t2SUBS_PC_LR
9915 { 4082, 3, 0, 4, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo142, -1 ,nullptr }, // Inst #4082 = t2TSB
9989 { 4156, 3, 0, 2, 1025, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo142, -1 ,nullptr }, // Inst #4156 = tHINT
10037 { 4204, 3, 0, 2, 842, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, ImplicitList2, nullptr, OperandInfo142, -1 ,nullptr }, // Inst #4204 = tSVC