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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/ARM/ARMGenInstrInfo.inc 6432 { 599, 6, 1, 4, 697, 0|(1ULL<<MCID::Add)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasOptionalDef)|(1ULL<<MCID::HasPostISelHook), 0x201ULL, ImplicitList1, ImplicitList1, OperandInfo128, -1 ,nullptr }, // Inst #599 = ADCrr
6436 { 603, 6, 1, 4, 697, 0|(1ULL<<MCID::Add)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasOptionalDef), 0x201ULL, nullptr, nullptr, OperandInfo128, -1 ,nullptr }, // Inst #603 = ADDrr
6445 { 612, 6, 1, 4, 322, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasOptionalDef), 0x201ULL, nullptr, nullptr, OperandInfo128, -1 ,nullptr }, // Inst #612 = ANDrr
6451 { 618, 6, 1, 4, 322, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0x201ULL, nullptr, nullptr, OperandInfo128, -1 ,nullptr }, // Inst #618 = BICrr
6490 { 657, 6, 1, 4, 322, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasOptionalDef), 0x201ULL, nullptr, nullptr, OperandInfo128, -1 ,nullptr }, // Inst #657 = EORrr
7471 { 1638, 6, 1, 4, 322, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasOptionalDef), 0x201ULL, nullptr, nullptr, OperandInfo128, -1 ,nullptr }, // Inst #1638 = ORRrr
7505 { 1672, 6, 1, 4, 697, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef)|(1ULL<<MCID::UnmodeledSideEffects), 0x201ULL, nullptr, nullptr, OperandInfo128, -1 ,nullptr }, // Inst #1672 = RSBrr
7509 { 1676, 6, 1, 4, 697, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x201ULL, ImplicitList1, ImplicitList1, OperandInfo128, -1 ,nullptr }, // Inst #1676 = RSCrr
7517 { 1684, 6, 1, 4, 697, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef)|(1ULL<<MCID::HasPostISelHook), 0x201ULL, ImplicitList1, ImplicitList1, OperandInfo128, -1 ,nullptr }, // Inst #1684 = SBCrr
7651 { 1818, 6, 1, 4, 2, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0x201ULL, nullptr, nullptr, OperandInfo128, -1 ,nullptr }, // Inst #1818 = SUBrr