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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/ARM/ARMGenInstrInfo.inc 6403 { 570, 3, 0, 2, 860, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo114, -1 ,nullptr }, // Inst #570 = tBRIND
6457 { 624, 3, 0, 4, 857, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::Predicable), 0x180ULL, ImplicitList2, ImplicitList3, OperandInfo114, -1 ,nullptr }, // Inst #624 = BLX_pred
6461 { 628, 3, 0, 4, 852, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo114, -1 ,nullptr }, // Inst #628 = BXJ
6463 { 630, 3, 0, 4, 851, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x180ULL, nullptr, nullptr, OperandInfo114, -1 ,nullptr }, // Inst #630 = BX_pred
8615 { 2782, 3, 1, 4, 582, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8c00ULL, nullptr, nullptr, OperandInfo114, -1 ,nullptr }, // Inst #2782 = VMRS_FPCXTNS
8616 { 2783, 3, 1, 4, 582, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8c00ULL, nullptr, nullptr, OperandInfo114, -1 ,nullptr }, // Inst #2783 = VMRS_FPCXTS
8626 { 2793, 3, 1, 4, 582, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8c00ULL, ImplicitList12, nullptr, OperandInfo114, -1 ,nullptr }, // Inst #2793 = VMRS_VPR
8628 { 2795, 3, 0, 4, 583, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8c00ULL, nullptr, nullptr, OperandInfo114, -1 ,nullptr }, // Inst #2795 = VMSR_FPCXTNS
8629 { 2796, 3, 0, 4, 583, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8c00ULL, nullptr, nullptr, OperandInfo114, -1 ,nullptr }, // Inst #2796 = VMSR_FPCXTS
8636 { 2803, 3, 0, 4, 583, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8c00ULL, nullptr, ImplicitList12, OperandInfo114, -1 ,nullptr }, // Inst #2803 = VMSR_VPR
9729 { 3896, 3, 1, 4, 1018, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo114, -1 ,nullptr }, // Inst #3896 = t2MRS_AR
9732 { 3899, 3, 1, 4, 1018, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo114, -1 ,nullptr }, // Inst #3899 = t2MRSsys_AR
9773 { 3940, 3, 0, 4, 726, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, ImplicitList10, OperandInfo114, -1 ,nullptr }, // Inst #3940 = t2RFEDB
9774 { 3941, 3, 0, 4, 726, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, ImplicitList10, OperandInfo114, -1 ,nullptr }, // Inst #3941 = t2RFEDBW
9775 { 3942, 3, 0, 4, 726, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, ImplicitList10, OperandInfo114, -1 ,nullptr }, // Inst #3942 = t2RFEIA
9776 { 3943, 3, 0, 4, 726, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, ImplicitList10, OperandInfo114, -1 ,nullptr }, // Inst #3943 = t2RFEIAW
9978 { 4145, 3, 0, 2, 851, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo114, -1 ,nullptr }, // Inst #4145 = tBX
9979 { 4146, 3, 0, 2, 851, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo114, -1 ,nullptr }, // Inst #4146 = tBXNS