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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/ARM/ARMGenInstrInfo.inc 6019 { 186, 2, 0, 4, 5, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList2, ImplicitList3, OperandInfo47, -1 ,nullptr }, // Inst #186 = BL_PUSHLR
6020 { 187, 1, 0, 8, 867, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call), 0x0ULL, ImplicitList2, ImplicitList3, OperandInfo44, -1 ,nullptr }, // Inst #187 = BMOVPCB_CALL
6021 { 188, 1, 0, 8, 867, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call), 0x0ULL, ImplicitList2, ImplicitList3, OperandInfo48, -1 ,nullptr }, // Inst #188 = BMOVPCRX_CALL
6026 { 193, 1, 0, 8, 851, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call), 0x0ULL, ImplicitList2, ImplicitList3, OperandInfo48, -1 ,nullptr }, // Inst #193 = BX_CALL
6402 { 569, 4, 0, 4, 5, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList2, ImplicitList3, OperandInfo113, -1 ,nullptr }, // Inst #569 = tBL_PUSHLR
6405 { 572, 1, 0, 4, 851, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call), 0x0ULL, ImplicitList2, ImplicitList3, OperandInfo48, -1 ,nullptr }, // Inst #572 = tBX_CALL
6408 { 575, 3, 0, 4, 853, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList3, OperandInfo118, -1 ,nullptr }, // Inst #575 = tBfar
6455 { 622, 1, 0, 4, 854, 0|(1ULL<<MCID::Call), 0x100ULL, ImplicitList2, ImplicitList3, OperandInfo44, -1 ,nullptr }, // Inst #622 = BL
6456 { 623, 1, 0, 4, 857, 0|(1ULL<<MCID::Call), 0x180ULL, ImplicitList2, ImplicitList3, OperandInfo67, -1 ,nullptr }, // Inst #623 = BLX
6457 { 624, 3, 0, 4, 857, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::Predicable), 0x180ULL, ImplicitList2, ImplicitList3, OperandInfo114, -1 ,nullptr }, // Inst #624 = BLX_pred
6459 { 626, 3, 0, 4, 854, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::Predicable), 0x100ULL, ImplicitList2, ImplicitList3, OperandInfo118, -1 ,nullptr }, // Inst #626 = BL_pred
9974 { 4141, 3, 0, 4, 854, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::Predicable), 0xc80ULL, ImplicitList2, ImplicitList3, OperandInfo506, -1 ,nullptr }, // Inst #4141 = tBL
9975 { 4142, 3, 0, 2, 857, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, ImplicitList2, ImplicitList3, OperandInfo507, -1 ,nullptr }, // Inst #4142 = tBLXNSr
9976 { 4143, 3, 0, 4, 854, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, ImplicitList2, ImplicitList3, OperandInfo506, -1 ,nullptr }, // Inst #4143 = tBLXi
9977 { 4144, 3, 0, 2, 857, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::Predicable), 0xc80ULL, ImplicitList2, ImplicitList3, OperandInfo508, -1 ,nullptr }, // Inst #4144 = tBLXr