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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/ARM/ARMGenInstrInfo.inc 6012 { 179, 4, 0, 0, 1028, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList2, ImplicitList2, OperandInfo41, -1 ,nullptr }, // Inst #179 = ADJCALLSTACKDOWN
6012 { 179, 4, 0, 0, 1028, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList2, ImplicitList2, OperandInfo41, -1 ,nullptr }, // Inst #179 = ADJCALLSTACKDOWN
6013 { 180, 4, 0, 0, 1028, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList2, ImplicitList2, OperandInfo41, -1 ,nullptr }, // Inst #180 = ADJCALLSTACKUP
6013 { 180, 4, 0, 0, 1028, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList2, ImplicitList2, OperandInfo41, -1 ,nullptr }, // Inst #180 = ADJCALLSTACKUP
6019 { 186, 2, 0, 4, 5, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList2, ImplicitList3, OperandInfo47, -1 ,nullptr }, // Inst #186 = BL_PUSHLR
6020 { 187, 1, 0, 8, 867, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call), 0x0ULL, ImplicitList2, ImplicitList3, OperandInfo44, -1 ,nullptr }, // Inst #187 = BMOVPCB_CALL
6021 { 188, 1, 0, 8, 867, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call), 0x0ULL, ImplicitList2, ImplicitList3, OperandInfo48, -1 ,nullptr }, // Inst #188 = BMOVPCRX_CALL
6026 { 193, 1, 0, 8, 851, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call), 0x0ULL, ImplicitList2, ImplicitList3, OperandInfo48, -1 ,nullptr }, // Inst #193 = BX_CALL
6118 { 285, 1, 0, 4, 851, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList2, nullptr, OperandInfo44, -1 ,nullptr }, // Inst #285 = TAILJMPd
6119 { 286, 1, 0, 4, 851, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList2, nullptr, OperandInfo80, -1 ,nullptr }, // Inst #286 = TAILJMPr
6120 { 287, 1, 0, 4, 851, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList2, nullptr, OperandInfo67, -1 ,nullptr }, // Inst #287 = TAILJMPr4
6121 { 288, 1, 0, 0, 851, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator), 0x0ULL, ImplicitList2, nullptr, OperandInfo3, -1 ,nullptr }, // Inst #288 = TCRETURNdi
6122 { 289, 1, 0, 0, 851, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator), 0x0ULL, ImplicitList2, nullptr, OperandInfo80, -1 ,nullptr }, // Inst #289 = TCRETURNri
6123 { 290, 0, 0, 4, 856, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call), 0x0ULL, ImplicitList2, ImplicitList7, nullptr, -1 ,nullptr }, // Inst #290 = TPsoft
6400 { 567, 2, 0, 0, 1028, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList2, ImplicitList2, OperandInfo8, -1 ,nullptr }, // Inst #567 = tADJCALLSTACKDOWN
6400 { 567, 2, 0, 0, 1028, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList2, ImplicitList2, OperandInfo8, -1 ,nullptr }, // Inst #567 = tADJCALLSTACKDOWN
6401 { 568, 2, 0, 0, 1028, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList2, ImplicitList2, OperandInfo8, -1 ,nullptr }, // Inst #568 = tADJCALLSTACKUP
6401 { 568, 2, 0, 0, 1028, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList2, ImplicitList2, OperandInfo8, -1 ,nullptr }, // Inst #568 = tADJCALLSTACKUP
6402 { 569, 4, 0, 4, 5, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList2, ImplicitList3, OperandInfo113, -1 ,nullptr }, // Inst #569 = tBL_PUSHLR
6405 { 572, 1, 0, 4, 851, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call), 0x0ULL, ImplicitList2, ImplicitList3, OperandInfo48, -1 ,nullptr }, // Inst #572 = tBX_CALL
6425 { 592, 3, 0, 4, 851, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList2, nullptr, OperandInfo118, -1 ,nullptr }, // Inst #592 = tTAILJMPd
6426 { 593, 3, 0, 4, 851, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList2, nullptr, OperandInfo118, -1 ,nullptr }, // Inst #593 = tTAILJMPdND
6427 { 594, 1, 0, 4, 851, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList2, nullptr, OperandInfo80, -1 ,nullptr }, // Inst #594 = tTAILJMPr
6430 { 597, 0, 0, 4, 856, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call), 0x0ULL, ImplicitList2, ImplicitList7, nullptr, -1 ,nullptr }, // Inst #597 = tTPsoft
6455 { 622, 1, 0, 4, 854, 0|(1ULL<<MCID::Call), 0x100ULL, ImplicitList2, ImplicitList3, OperandInfo44, -1 ,nullptr }, // Inst #622 = BL
6456 { 623, 1, 0, 4, 857, 0|(1ULL<<MCID::Call), 0x180ULL, ImplicitList2, ImplicitList3, OperandInfo67, -1 ,nullptr }, // Inst #623 = BLX
6457 { 624, 3, 0, 4, 857, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::Predicable), 0x180ULL, ImplicitList2, ImplicitList3, OperandInfo114, -1 ,nullptr }, // Inst #624 = BLX_pred
6459 { 626, 3, 0, 4, 854, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::Predicable), 0x100ULL, ImplicitList2, ImplicitList3, OperandInfo118, -1 ,nullptr }, // Inst #626 = BL_pred
7654 { 1821, 3, 0, 4, 842, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL, ImplicitList2, nullptr, OperandInfo142, -1 ,nullptr }, // Inst #1821 = SVC
9801 { 3968, 3, 0, 4, 841, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, ImplicitList2, nullptr, OperandInfo142, -1 ,nullptr }, // Inst #3968 = t2SMC
9974 { 4141, 3, 0, 4, 854, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::Predicable), 0xc80ULL, ImplicitList2, ImplicitList3, OperandInfo506, -1 ,nullptr }, // Inst #4141 = tBL
9975 { 4142, 3, 0, 2, 857, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, ImplicitList2, ImplicitList3, OperandInfo507, -1 ,nullptr }, // Inst #4142 = tBLXNSr
9976 { 4143, 3, 0, 4, 854, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, ImplicitList2, ImplicitList3, OperandInfo506, -1 ,nullptr }, // Inst #4143 = tBLXi
9977 { 4144, 3, 0, 2, 857, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::Predicable), 0xc80ULL, ImplicitList2, ImplicitList3, OperandInfo508, -1 ,nullptr }, // Inst #4144 = tBLXr
10016 { 4183, 3, 0, 2, 421, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::VariadicOpsAreDefs), 0xc80ULL, ImplicitList2, ImplicitList2, OperandInfo125, -1 ,nullptr }, // Inst #4183 = tPOP
10016 { 4183, 3, 0, 2, 421, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::VariadicOpsAreDefs), 0xc80ULL, ImplicitList2, ImplicitList2, OperandInfo125, -1 ,nullptr }, // Inst #4183 = tPOP
10017 { 4184, 3, 0, 2, 449, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc80ULL, ImplicitList2, ImplicitList2, OperandInfo125, -1 ,nullptr }, // Inst #4184 = tPUSH
10017 { 4184, 3, 0, 2, 449, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc80ULL, ImplicitList2, ImplicitList2, OperandInfo125, -1 ,nullptr }, // Inst #4184 = tPUSH
10037 { 4204, 3, 0, 2, 842, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, ImplicitList2, nullptr, OperandInfo142, -1 ,nullptr }, // Inst #4204 = tSVC