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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/ARM/ARMGenInstrInfo.inc 8470 { 2637, 4, 0, 4, 745, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8b53ULL, ImplicitList13, nullptr, OperandInfo364, -1 ,nullptr }, // Inst #2637 = VLDR_FPCXTNS_off
8471 { 2638, 5, 1, 4, 745, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8b53ULL, ImplicitList13, nullptr, OperandInfo365, -1 ,nullptr }, // Inst #2638 = VLDR_FPCXTNS_post
8472 { 2639, 5, 1, 4, 745, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8b33ULL, ImplicitList13, nullptr, OperandInfo365, -1 ,nullptr }, // Inst #2639 = VLDR_FPCXTNS_pre
8473 { 2640, 4, 0, 4, 745, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8b53ULL, ImplicitList13, nullptr, OperandInfo364, -1 ,nullptr }, // Inst #2640 = VLDR_FPCXTS_off
8474 { 2641, 5, 1, 4, 745, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8b53ULL, ImplicitList13, nullptr, OperandInfo365, -1 ,nullptr }, // Inst #2641 = VLDR_FPCXTS_post
8475 { 2642, 5, 1, 4, 745, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8b33ULL, ImplicitList13, nullptr, OperandInfo365, -1 ,nullptr }, // Inst #2642 = VLDR_FPCXTS_pre
8476 { 2643, 4, 0, 4, 745, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8b53ULL, ImplicitList13, nullptr, OperandInfo364, -1 ,nullptr }, // Inst #2643 = VLDR_FPSCR_NZCVQC_off
8477 { 2644, 5, 1, 4, 745, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8b53ULL, ImplicitList13, nullptr, OperandInfo365, -1 ,nullptr }, // Inst #2644 = VLDR_FPSCR_NZCVQC_post
8478 { 2645, 5, 1, 4, 745, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8b33ULL, ImplicitList13, nullptr, OperandInfo365, -1 ,nullptr }, // Inst #2645 = VLDR_FPSCR_NZCVQC_pre
8479 { 2646, 4, 0, 4, 745, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8b53ULL, ImplicitList13, nullptr, OperandInfo364, -1 ,nullptr }, // Inst #2646 = VLDR_FPSCR_off
8480 { 2647, 5, 1, 4, 745, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8b53ULL, ImplicitList13, nullptr, OperandInfo365, -1 ,nullptr }, // Inst #2647 = VLDR_FPSCR_post
8481 { 2648, 5, 1, 4, 745, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8b33ULL, ImplicitList13, nullptr, OperandInfo365, -1 ,nullptr }, // Inst #2648 = VLDR_FPSCR_pre
8614 { 2781, 3, 1, 4, 582, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8c00ULL, ImplicitList13, nullptr, OperandInfo177, -1 ,nullptr }, // Inst #2781 = VMRS
8617 { 2784, 3, 1, 4, 582, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8c00ULL, ImplicitList13, nullptr, OperandInfo177, -1 ,nullptr }, // Inst #2784 = VMRS_FPEXC
8618 { 2785, 3, 1, 4, 582, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8c00ULL, ImplicitList13, nullptr, OperandInfo177, -1 ,nullptr }, // Inst #2785 = VMRS_FPINST
8619 { 2786, 3, 1, 4, 582, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8c00ULL, ImplicitList13, nullptr, OperandInfo177, -1 ,nullptr }, // Inst #2786 = VMRS_FPINST2
8620 { 2787, 4, 1, 4, 582, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8c00ULL, ImplicitList13, nullptr, OperandInfo383, -1 ,nullptr }, // Inst #2787 = VMRS_FPSCR_NZCVQC
8621 { 2788, 3, 1, 4, 582, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8c00ULL, ImplicitList13, nullptr, OperandInfo177, -1 ,nullptr }, // Inst #2788 = VMRS_FPSID
8622 { 2789, 3, 1, 4, 582, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8c00ULL, ImplicitList13, nullptr, OperandInfo177, -1 ,nullptr }, // Inst #2789 = VMRS_MVFR0
8623 { 2790, 3, 1, 4, 582, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8c00ULL, ImplicitList13, nullptr, OperandInfo177, -1 ,nullptr }, // Inst #2790 = VMRS_MVFR1
8624 { 2791, 3, 1, 4, 582, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8c00ULL, ImplicitList13, nullptr, OperandInfo177, -1 ,nullptr }, // Inst #2791 = VMRS_MVFR2
8627 { 2794, 3, 0, 4, 583, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8c00ULL, nullptr, ImplicitList13, OperandInfo177, -1 ,nullptr }, // Inst #2794 = VMSR
8630 { 2797, 3, 0, 4, 583, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8c00ULL, nullptr, ImplicitList13, OperandInfo177, -1 ,nullptr }, // Inst #2797 = VMSR_FPEXC
8631 { 2798, 3, 0, 4, 583, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8c00ULL, nullptr, ImplicitList13, OperandInfo177, -1 ,nullptr }, // Inst #2798 = VMSR_FPINST
8632 { 2799, 3, 0, 4, 583, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8c00ULL, nullptr, ImplicitList13, OperandInfo177, -1 ,nullptr }, // Inst #2799 = VMSR_FPINST2
8634 { 2801, 3, 0, 4, 583, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8c00ULL, nullptr, ImplicitList13, OperandInfo177, -1 ,nullptr }, // Inst #2801 = VMSR_FPSID
9435 { 3602, 4, 0, 4, 747, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8b53ULL, nullptr, ImplicitList13, OperandInfo364, -1 ,nullptr }, // Inst #3602 = VSTR_FPCXTNS_off
9436 { 3603, 5, 1, 4, 747, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8b53ULL, nullptr, ImplicitList13, OperandInfo365, -1 ,nullptr }, // Inst #3603 = VSTR_FPCXTNS_post
9437 { 3604, 5, 1, 4, 747, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8b33ULL, nullptr, ImplicitList13, OperandInfo365, -1 ,nullptr }, // Inst #3604 = VSTR_FPCXTNS_pre
9438 { 3605, 4, 0, 4, 747, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8b53ULL, nullptr, ImplicitList13, OperandInfo364, -1 ,nullptr }, // Inst #3605 = VSTR_FPCXTS_off
9439 { 3606, 5, 1, 4, 747, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8b53ULL, nullptr, ImplicitList13, OperandInfo365, -1 ,nullptr }, // Inst #3606 = VSTR_FPCXTS_post
9440 { 3607, 5, 1, 4, 747, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8b33ULL, nullptr, ImplicitList13, OperandInfo365, -1 ,nullptr }, // Inst #3607 = VSTR_FPCXTS_pre
9441 { 3608, 4, 0, 4, 747, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8b53ULL, nullptr, ImplicitList13, OperandInfo364, -1 ,nullptr }, // Inst #3608 = VSTR_FPSCR_NZCVQC_off
9442 { 3609, 5, 1, 4, 747, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8b53ULL, nullptr, ImplicitList13, OperandInfo365, -1 ,nullptr }, // Inst #3609 = VSTR_FPSCR_NZCVQC_post
9443 { 3610, 5, 1, 4, 747, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8b33ULL, nullptr, ImplicitList13, OperandInfo365, -1 ,nullptr }, // Inst #3610 = VSTR_FPSCR_NZCVQC_pre
9444 { 3611, 4, 0, 4, 747, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8b53ULL, nullptr, ImplicitList13, OperandInfo364, -1 ,nullptr }, // Inst #3611 = VSTR_FPSCR_off
9445 { 3612, 5, 1, 4, 747, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8b53ULL, nullptr, ImplicitList13, OperandInfo365, -1 ,nullptr }, // Inst #3612 = VSTR_FPSCR_post
9446 { 3613, 5, 1, 4, 747, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8b33ULL, nullptr, ImplicitList13, OperandInfo365, -1 ,nullptr }, // Inst #3613 = VSTR_FPSCR_pre
9500 { 3667, 4, 1, 4, 561, 0|(1ULL<<MCID::Predicable), 0x8880ULL, ImplicitList13, nullptr, OperandInfo309, -1 ,nullptr }, // Inst #3667 = VTOSIRD
9501 { 3668, 4, 1, 4, 562, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x8880ULL, ImplicitList13, nullptr, OperandInfo286, -1 ,nullptr }, // Inst #3668 = VTOSIRH
9502 { 3669, 4, 1, 4, 563, 0|(1ULL<<MCID::Predicable), 0x8880ULL, ImplicitList13, nullptr, OperandInfo286, -1 ,nullptr }, // Inst #3669 = VTOSIRS
9512 { 3679, 4, 1, 4, 561, 0|(1ULL<<MCID::Predicable), 0x8880ULL, ImplicitList13, nullptr, OperandInfo309, -1 ,nullptr }, // Inst #3679 = VTOUIRD
9513 { 3680, 4, 1, 4, 562, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x8880ULL, ImplicitList13, nullptr, OperandInfo286, -1 ,nullptr }, // Inst #3680 = VTOUIRH
9514 { 3681, 4, 1, 4, 563, 0|(1ULL<<MCID::Predicable), 0x8880ULL, ImplicitList13, nullptr, OperandInfo286, -1 ,nullptr }, // Inst #3681 = VTOUIRS