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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/ARM/ARMGenInstrInfo.inc 7085 { 1252, 1, 0, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x140c80ULL, ImplicitList12, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #1252 = MVE_VPST
7086 { 1253, 4, 0, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x140c80ULL, nullptr, ImplicitList12, OperandInfo235, -1 ,nullptr }, // Inst #1253 = MVE_VPTv16i8
7087 { 1254, 4, 0, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x140c80ULL, nullptr, ImplicitList12, OperandInfo236, -1 ,nullptr }, // Inst #1254 = MVE_VPTv16i8r
7088 { 1255, 4, 0, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x140c80ULL, nullptr, ImplicitList12, OperandInfo235, -1 ,nullptr }, // Inst #1255 = MVE_VPTv16s8
7089 { 1256, 4, 0, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x140c80ULL, nullptr, ImplicitList12, OperandInfo236, -1 ,nullptr }, // Inst #1256 = MVE_VPTv16s8r
7090 { 1257, 4, 0, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x140c80ULL, nullptr, ImplicitList12, OperandInfo235, -1 ,nullptr }, // Inst #1257 = MVE_VPTv16u8
7091 { 1258, 4, 0, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x140c80ULL, nullptr, ImplicitList12, OperandInfo236, -1 ,nullptr }, // Inst #1258 = MVE_VPTv16u8r
7092 { 1259, 4, 0, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x140c80ULL, nullptr, ImplicitList12, OperandInfo235, -1 ,nullptr }, // Inst #1259 = MVE_VPTv4f32
7093 { 1260, 4, 0, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x140c80ULL, nullptr, ImplicitList12, OperandInfo236, -1 ,nullptr }, // Inst #1260 = MVE_VPTv4f32r
7094 { 1261, 4, 0, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x140c80ULL, nullptr, ImplicitList12, OperandInfo235, -1 ,nullptr }, // Inst #1261 = MVE_VPTv4i32
7095 { 1262, 4, 0, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x140c80ULL, nullptr, ImplicitList12, OperandInfo236, -1 ,nullptr }, // Inst #1262 = MVE_VPTv4i32r
7096 { 1263, 4, 0, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x140c80ULL, nullptr, ImplicitList12, OperandInfo235, -1 ,nullptr }, // Inst #1263 = MVE_VPTv4s32
7097 { 1264, 4, 0, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x140c80ULL, nullptr, ImplicitList12, OperandInfo236, -1 ,nullptr }, // Inst #1264 = MVE_VPTv4s32r
7098 { 1265, 4, 0, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x140c80ULL, nullptr, ImplicitList12, OperandInfo235, -1 ,nullptr }, // Inst #1265 = MVE_VPTv4u32
7099 { 1266, 4, 0, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x140c80ULL, nullptr, ImplicitList12, OperandInfo236, -1 ,nullptr }, // Inst #1266 = MVE_VPTv4u32r
7100 { 1267, 4, 0, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x140c80ULL, nullptr, ImplicitList12, OperandInfo235, -1 ,nullptr }, // Inst #1267 = MVE_VPTv8f16
7101 { 1268, 4, 0, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x140c80ULL, nullptr, ImplicitList12, OperandInfo236, -1 ,nullptr }, // Inst #1268 = MVE_VPTv8f16r
7102 { 1269, 4, 0, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x140c80ULL, nullptr, ImplicitList12, OperandInfo235, -1 ,nullptr }, // Inst #1269 = MVE_VPTv8i16
7103 { 1270, 4, 0, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x140c80ULL, nullptr, ImplicitList12, OperandInfo236, -1 ,nullptr }, // Inst #1270 = MVE_VPTv8i16r
7104 { 1271, 4, 0, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x140c80ULL, nullptr, ImplicitList12, OperandInfo235, -1 ,nullptr }, // Inst #1271 = MVE_VPTv8s16
7105 { 1272, 4, 0, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x140c80ULL, nullptr, ImplicitList12, OperandInfo236, -1 ,nullptr }, // Inst #1272 = MVE_VPTv8s16r
7106 { 1273, 4, 0, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x140c80ULL, nullptr, ImplicitList12, OperandInfo235, -1 ,nullptr }, // Inst #1273 = MVE_VPTv8u16
7107 { 1274, 4, 0, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x140c80ULL, nullptr, ImplicitList12, OperandInfo236, -1 ,nullptr }, // Inst #1274 = MVE_VPTv8u16r
8485 { 2652, 4, 0, 4, 745, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8b53ULL, nullptr, ImplicitList12, OperandInfo364, -1 ,nullptr }, // Inst #2652 = VLDR_VPR_off
8486 { 2653, 5, 1, 4, 745, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8b53ULL, nullptr, ImplicitList12, OperandInfo365, -1 ,nullptr }, // Inst #2653 = VLDR_VPR_post
8487 { 2654, 5, 1, 4, 745, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8b33ULL, nullptr, ImplicitList12, OperandInfo365, -1 ,nullptr }, // Inst #2654 = VLDR_VPR_pre
8626 { 2793, 3, 1, 4, 582, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8c00ULL, ImplicitList12, nullptr, OperandInfo114, -1 ,nullptr }, // Inst #2793 = VMRS_VPR
8636 { 2803, 3, 0, 4, 583, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8c00ULL, nullptr, ImplicitList12, OperandInfo114, -1 ,nullptr }, // Inst #2803 = VMSR_VPR
9450 { 3617, 4, 0, 4, 747, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8b53ULL, ImplicitList12, nullptr, OperandInfo364, -1 ,nullptr }, // Inst #3617 = VSTR_VPR_off
9451 { 3618, 5, 1, 4, 747, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8b53ULL, ImplicitList12, nullptr, OperandInfo365, -1 ,nullptr }, // Inst #3618 = VSTR_VPR_post
9452 { 3619, 5, 1, 4, 747, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8b33ULL, ImplicitList12, nullptr, OperandInfo365, -1 ,nullptr }, // Inst #3619 = VSTR_VPR_pre