|
|
reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
|
References
gen/lib/Target/ARM/ARMGenInstrInfo.inc 6007 { 174, 2, 1, 8, 676, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList1, OperandInfo36, -1 ,nullptr }, // Inst #174 = ABS
6008 { 175, 5, 1, 4, 690, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Add)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasPostISelHook), 0x0ULL, nullptr, ImplicitList1, OperandInfo37, -1 ,nullptr }, // Inst #175 = ADDSri
6009 { 176, 5, 1, 4, 697, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Add)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook), 0x0ULL, nullptr, ImplicitList1, OperandInfo38, -1 ,nullptr }, // Inst #176 = ADDSrr
6010 { 177, 6, 1, 4, 700, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Add)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasPostISelHook), 0x0ULL, nullptr, ImplicitList1, OperandInfo39, -1 ,nullptr }, // Inst #177 = ADDSrsi
6011 { 178, 7, 1, 4, 705, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Add)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasPostISelHook), 0x0ULL, nullptr, ImplicitList1, OperandInfo40, -1 ,nullptr }, // Inst #178 = ADDSrsr
6017 { 184, 4, 0, 0, 858, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, ImplicitList1, OperandInfo45, -1 ,nullptr }, // Inst #184 = BCCZi64
6018 { 185, 6, 0, 0, 858, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, ImplicitList1, OperandInfo46, -1 ,nullptr }, // Inst #185 = BCCi64
6032 { 199, 4, 0, 0, 841, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, ImplicitList1, OperandInfo55, -1 ,nullptr }, // Inst #199 = COPY_STRUCT_BYVAL_I32
6071 { 238, 2, 1, 0, 325, 0|(1ULL<<MCID::Pseudo), 0x2000ULL, nullptr, ImplicitList1, OperandInfo36, -1 ,nullptr }, // Inst #238 = MOVsra_flag
6072 { 239, 2, 1, 0, 325, 0|(1ULL<<MCID::Pseudo), 0x2000ULL, nullptr, ImplicitList1, OperandInfo36, -1 ,nullptr }, // Inst #239 = MOVsrl_flag
6098 { 265, 2, 1, 0, 719, 0|(1ULL<<MCID::Pseudo), 0x2000ULL, ImplicitList1, nullptr, OperandInfo36, -1 ,nullptr }, // Inst #265 = RRX
6100 { 267, 5, 1, 4, 690, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasPostISelHook), 0x0ULL, nullptr, ImplicitList1, OperandInfo37, -1 ,nullptr }, // Inst #267 = RSBSri
6101 { 268, 6, 1, 4, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasPostISelHook), 0x0ULL, nullptr, ImplicitList1, OperandInfo39, -1 ,nullptr }, // Inst #268 = RSBSrsi
6102 { 269, 7, 1, 4, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasPostISelHook), 0x0ULL, nullptr, ImplicitList1, OperandInfo40, -1 ,nullptr }, // Inst #269 = RSBSrsr
6114 { 281, 5, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasPostISelHook), 0x0ULL, nullptr, ImplicitList1, OperandInfo37, -1 ,nullptr }, // Inst #281 = SUBSri
6115 { 282, 5, 1, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasPostISelHook), 0x0ULL, nullptr, ImplicitList1, OperandInfo38, -1 ,nullptr }, // Inst #282 = SUBSrr
6116 { 283, 6, 1, 4, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasPostISelHook), 0x0ULL, nullptr, ImplicitList1, OperandInfo39, -1 ,nullptr }, // Inst #283 = SUBSrsi
6117 { 284, 7, 1, 4, 4, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasPostISelHook), 0x0ULL, nullptr, ImplicitList1, OperandInfo40, -1 ,nullptr }, // Inst #284 = SUBSrsr
6347 { 514, 1, 0, 0, 849, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList1, OperandInfo48, -1 ,nullptr }, // Inst #514 = WIN__DBZCHK
6348 { 515, 2, 1, 0, 680, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList1, OperandInfo89, -1 ,nullptr }, // Inst #515 = t2ABS
6349 { 516, 5, 1, 4, 690, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasPostISelHook), 0x0ULL, nullptr, ImplicitList1, OperandInfo90, -1 ,nullptr }, // Inst #516 = t2ADDSri
6350 { 517, 5, 1, 4, 697, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook), 0x0ULL, nullptr, ImplicitList1, OperandInfo91, -1 ,nullptr }, // Inst #517 = t2ADDSrr
6351 { 518, 6, 1, 4, 701, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasPostISelHook), 0x0ULL, nullptr, ImplicitList1, OperandInfo92, -1 ,nullptr }, // Inst #518 = t2ADDSrs
6366 { 533, 2, 0, 8, 5, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList1, OperandInfo47, -1 ,nullptr }, // Inst #533 = t2LoopEnd
6384 { 551, 5, 1, 4, 690, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasPostISelHook), 0x0ULL, nullptr, ImplicitList1, OperandInfo106, -1 ,nullptr }, // Inst #551 = t2RSBSri
6385 { 552, 6, 1, 4, 35, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasPostISelHook), 0x0ULL, nullptr, ImplicitList1, OperandInfo107, -1 ,nullptr }, // Inst #552 = t2RSBSrs
6389 { 556, 5, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasPostISelHook), 0x0ULL, nullptr, ImplicitList1, OperandInfo90, -1 ,nullptr }, // Inst #556 = t2SUBSri
6390 { 557, 5, 1, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasPostISelHook), 0x0ULL, nullptr, ImplicitList1, OperandInfo91, -1 ,nullptr }, // Inst #557 = t2SUBSrr
6391 { 558, 6, 1, 4, 33, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasPostISelHook), 0x0ULL, nullptr, ImplicitList1, OperandInfo92, -1 ,nullptr }, // Inst #558 = t2SUBSrs
6394 { 561, 2, 0, 8, 5, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList1, OperandInfo109, -1 ,nullptr }, // Inst #561 = t2WhileLoopStart
6395 { 562, 3, 1, 2, 37, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Add)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo110, -1 ,nullptr }, // Inst #562 = tADCS
6395 { 562, 3, 1, 2, 37, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Add)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo110, -1 ,nullptr }, // Inst #562 = tADCS
6396 { 563, 3, 1, 2, 38, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Add)|(1ULL<<MCID::HasPostISelHook), 0x0ULL, nullptr, ImplicitList1, OperandInfo111, -1 ,nullptr }, // Inst #563 = tADDSi3
6397 { 564, 3, 1, 2, 38, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Add)|(1ULL<<MCID::HasPostISelHook), 0x0ULL, nullptr, ImplicitList1, OperandInfo111, -1 ,nullptr }, // Inst #564 = tADDSi8
6398 { 565, 3, 1, 2, 37, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Add)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook), 0x0ULL, nullptr, ImplicitList1, OperandInfo110, -1 ,nullptr }, // Inst #565 = tADDSrr
6399 { 566, 3, 1, 0, 863, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList1, OperandInfo112, -1 ,nullptr }, // Inst #566 = tADDframe
6417 { 584, 3, 1, 2, 37, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook), 0x0ULL, nullptr, ImplicitList1, OperandInfo111, -1 ,nullptr }, // Inst #584 = tLSLSri
6420 { 587, 2, 1, 2, 37, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook), 0x0ULL, nullptr, ImplicitList1, OperandInfo126, -1 ,nullptr }, // Inst #587 = tRSBS
6421 { 588, 3, 1, 2, 37, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo110, -1 ,nullptr }, // Inst #588 = tSBCS
6421 { 588, 3, 1, 2, 37, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo110, -1 ,nullptr }, // Inst #588 = tSBCS
6422 { 589, 3, 1, 2, 38, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook), 0x0ULL, nullptr, ImplicitList1, OperandInfo111, -1 ,nullptr }, // Inst #589 = tSUBSi3
6423 { 590, 3, 1, 2, 38, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook), 0x0ULL, nullptr, ImplicitList1, OperandInfo111, -1 ,nullptr }, // Inst #590 = tSUBSi8
6424 { 591, 3, 1, 2, 37, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::HasPostISelHook), 0x0ULL, nullptr, ImplicitList1, OperandInfo110, -1 ,nullptr }, // Inst #591 = tSUBSrr
6431 { 598, 6, 1, 4, 690, 0|(1ULL<<MCID::Add)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef)|(1ULL<<MCID::HasPostISelHook), 0x201ULL, ImplicitList1, ImplicitList1, OperandInfo42, -1 ,nullptr }, // Inst #598 = ADCri
6431 { 598, 6, 1, 4, 690, 0|(1ULL<<MCID::Add)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef)|(1ULL<<MCID::HasPostISelHook), 0x201ULL, ImplicitList1, ImplicitList1, OperandInfo42, -1 ,nullptr }, // Inst #598 = ADCri
6432 { 599, 6, 1, 4, 697, 0|(1ULL<<MCID::Add)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasOptionalDef)|(1ULL<<MCID::HasPostISelHook), 0x201ULL, ImplicitList1, ImplicitList1, OperandInfo128, -1 ,nullptr }, // Inst #599 = ADCrr
6432 { 599, 6, 1, 4, 697, 0|(1ULL<<MCID::Add)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasOptionalDef)|(1ULL<<MCID::HasPostISelHook), 0x201ULL, ImplicitList1, ImplicitList1, OperandInfo128, -1 ,nullptr }, // Inst #599 = ADCrr
6433 { 600, 7, 1, 4, 700, 0|(1ULL<<MCID::Add)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef)|(1ULL<<MCID::HasPostISelHook), 0x1501ULL, ImplicitList1, ImplicitList1, OperandInfo129, -1 ,nullptr }, // Inst #600 = ADCrsi
6433 { 600, 7, 1, 4, 700, 0|(1ULL<<MCID::Add)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef)|(1ULL<<MCID::HasPostISelHook), 0x1501ULL, ImplicitList1, ImplicitList1, OperandInfo129, -1 ,nullptr }, // Inst #600 = ADCrsi
6434 { 601, 8, 1, 4, 706, 0|(1ULL<<MCID::Add)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef)|(1ULL<<MCID::HasPostISelHook), 0x281ULL, ImplicitList1, ImplicitList1, OperandInfo130, -1 ,nullptr }, // Inst #601 = ADCrsr
6434 { 601, 8, 1, 4, 706, 0|(1ULL<<MCID::Add)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef)|(1ULL<<MCID::HasPostISelHook), 0x281ULL, ImplicitList1, ImplicitList1, OperandInfo130, -1 ,nullptr }, // Inst #601 = ADCrsr
6469 { 636, 4, 0, 4, 713, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Predicable), 0x201ULL, nullptr, ImplicitList1, OperandInfo58, -1 ,nullptr }, // Inst #636 = CMNri
6470 { 637, 4, 0, 4, 714, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x201ULL, nullptr, ImplicitList1, OperandInfo137, -1 ,nullptr }, // Inst #637 = CMNzrr
6471 { 638, 5, 0, 4, 715, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Predicable), 0x1501ULL, nullptr, ImplicitList1, OperandInfo138, -1 ,nullptr }, // Inst #638 = CMNzrsi
6472 { 639, 6, 0, 4, 716, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Predicable), 0x281ULL, nullptr, ImplicitList1, OperandInfo139, -1 ,nullptr }, // Inst #639 = CMNzrsr
6473 { 640, 4, 0, 4, 713, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Predicable), 0x201ULL, nullptr, ImplicitList1, OperandInfo58, -1 ,nullptr }, // Inst #640 = CMPri
6474 { 641, 4, 0, 4, 714, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Predicable), 0x201ULL, nullptr, ImplicitList1, OperandInfo137, -1 ,nullptr }, // Inst #641 = CMPrr
6475 { 642, 5, 0, 4, 715, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Predicable), 0x1501ULL, nullptr, ImplicitList1, OperandInfo138, -1 ,nullptr }, // Inst #642 = CMPrsi
6476 { 643, 6, 0, 4, 716, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Predicable), 0x281ULL, nullptr, ImplicitList1, OperandInfo139, -1 ,nullptr }, // Inst #643 = CMPrsr
6500 { 667, 2, 0, 4, 584, 0|(1ULL<<MCID::Predicable), 0x8c00ULL, ImplicitList11, ImplicitList1, OperandInfo116, -1 ,nullptr }, // Inst #667 = FMSTAT
6599 { 766, 4, 0, 4, 725, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL, nullptr, ImplicitList1, OperandInfo178, -1 ,nullptr }, // Inst #766 = MSR
6601 { 768, 4, 0, 4, 725, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL, nullptr, ImplicitList1, OperandInfo180, -1 ,nullptr }, // Inst #768 = MSRi
7508 { 1675, 6, 1, 4, 690, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef)|(1ULL<<MCID::HasPostISelHook), 0x201ULL, ImplicitList1, ImplicitList1, OperandInfo42, -1 ,nullptr }, // Inst #1675 = RSCri
7508 { 1675, 6, 1, 4, 690, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef)|(1ULL<<MCID::HasPostISelHook), 0x201ULL, ImplicitList1, ImplicitList1, OperandInfo42, -1 ,nullptr }, // Inst #1675 = RSCri
7509 { 1676, 6, 1, 4, 697, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x201ULL, ImplicitList1, ImplicitList1, OperandInfo128, -1 ,nullptr }, // Inst #1676 = RSCrr
7509 { 1676, 6, 1, 4, 697, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x201ULL, ImplicitList1, ImplicitList1, OperandInfo128, -1 ,nullptr }, // Inst #1676 = RSCrr
7510 { 1677, 7, 1, 4, 700, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef)|(1ULL<<MCID::HasPostISelHook), 0x1501ULL, ImplicitList1, ImplicitList1, OperandInfo129, -1 ,nullptr }, // Inst #1677 = RSCrsi
7510 { 1677, 7, 1, 4, 700, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef)|(1ULL<<MCID::HasPostISelHook), 0x1501ULL, ImplicitList1, ImplicitList1, OperandInfo129, -1 ,nullptr }, // Inst #1677 = RSCrsi
7511 { 1678, 8, 1, 4, 706, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef)|(1ULL<<MCID::HasPostISelHook), 0x281ULL, ImplicitList1, ImplicitList1, OperandInfo131, -1 ,nullptr }, // Inst #1678 = RSCrsr
7511 { 1678, 8, 1, 4, 706, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef)|(1ULL<<MCID::HasPostISelHook), 0x281ULL, ImplicitList1, ImplicitList1, OperandInfo131, -1 ,nullptr }, // Inst #1678 = RSCrsr
7516 { 1683, 6, 1, 4, 690, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef)|(1ULL<<MCID::HasPostISelHook), 0x201ULL, ImplicitList1, ImplicitList1, OperandInfo42, -1 ,nullptr }, // Inst #1683 = SBCri
7516 { 1683, 6, 1, 4, 690, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef)|(1ULL<<MCID::HasPostISelHook), 0x201ULL, ImplicitList1, ImplicitList1, OperandInfo42, -1 ,nullptr }, // Inst #1683 = SBCri
7517 { 1684, 6, 1, 4, 697, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef)|(1ULL<<MCID::HasPostISelHook), 0x201ULL, ImplicitList1, ImplicitList1, OperandInfo128, -1 ,nullptr }, // Inst #1684 = SBCrr
7517 { 1684, 6, 1, 4, 697, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef)|(1ULL<<MCID::HasPostISelHook), 0x201ULL, ImplicitList1, ImplicitList1, OperandInfo128, -1 ,nullptr }, // Inst #1684 = SBCrr
7518 { 1685, 7, 1, 4, 700, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef)|(1ULL<<MCID::HasPostISelHook), 0x1501ULL, ImplicitList1, ImplicitList1, OperandInfo129, -1 ,nullptr }, // Inst #1685 = SBCrsi
7518 { 1685, 7, 1, 4, 700, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef)|(1ULL<<MCID::HasPostISelHook), 0x1501ULL, ImplicitList1, ImplicitList1, OperandInfo129, -1 ,nullptr }, // Inst #1685 = SBCrsi
7519 { 1686, 8, 1, 4, 706, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef)|(1ULL<<MCID::HasPostISelHook), 0x281ULL, ImplicitList1, ImplicitList1, OperandInfo130, -1 ,nullptr }, // Inst #1686 = SBCrsr
7519 { 1686, 8, 1, 4, 706, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef)|(1ULL<<MCID::HasPostISelHook), 0x281ULL, ImplicitList1, ImplicitList1, OperandInfo130, -1 ,nullptr }, // Inst #1686 = SBCrsr
7663 { 1830, 4, 0, 4, 91, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Predicable), 0x201ULL, nullptr, ImplicitList1, OperandInfo58, -1 ,nullptr }, // Inst #1830 = TEQri
7664 { 1831, 4, 0, 4, 92, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x201ULL, nullptr, ImplicitList1, OperandInfo137, -1 ,nullptr }, // Inst #1831 = TEQrr
7665 { 1832, 5, 0, 4, 93, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Predicable), 0x1501ULL, nullptr, ImplicitList1, OperandInfo138, -1 ,nullptr }, // Inst #1832 = TEQrsi
7666 { 1833, 6, 0, 4, 94, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Predicable), 0x281ULL, nullptr, ImplicitList1, OperandInfo139, -1 ,nullptr }, // Inst #1833 = TEQrsr
7670 { 1837, 4, 0, 4, 720, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Predicable), 0x201ULL, nullptr, ImplicitList1, OperandInfo58, -1 ,nullptr }, // Inst #1837 = TSTri
7671 { 1838, 4, 0, 4, 721, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x201ULL, nullptr, ImplicitList1, OperandInfo137, -1 ,nullptr }, // Inst #1838 = TSTrr
7672 { 1839, 5, 0, 4, 722, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Predicable), 0x1501ULL, nullptr, ImplicitList1, OperandInfo138, -1 ,nullptr }, // Inst #1839 = TSTrsi
7673 { 1840, 6, 0, 4, 723, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Predicable), 0x281ULL, nullptr, ImplicitList1, OperandInfo139, -1 ,nullptr }, // Inst #1840 = TSTrsr
9076 { 3243, 3, 1, 4, 770, 0, 0x8800ULL, ImplicitList1, nullptr, OperandInfo252, -1 ,nullptr }, // Inst #3243 = VSELEQD
9077 { 3244, 3, 1, 4, 770, 0, 0x8800ULL, ImplicitList1, nullptr, OperandInfo326, -1 ,nullptr }, // Inst #3244 = VSELEQH
9078 { 3245, 3, 1, 4, 770, 0, 0x8800ULL, ImplicitList1, nullptr, OperandInfo327, -1 ,nullptr }, // Inst #3245 = VSELEQS
9079 { 3246, 3, 1, 4, 770, 0, 0x8800ULL, ImplicitList1, nullptr, OperandInfo252, -1 ,nullptr }, // Inst #3246 = VSELGED
9080 { 3247, 3, 1, 4, 770, 0, 0x8800ULL, ImplicitList1, nullptr, OperandInfo326, -1 ,nullptr }, // Inst #3247 = VSELGEH
9081 { 3248, 3, 1, 4, 770, 0, 0x8800ULL, ImplicitList1, nullptr, OperandInfo327, -1 ,nullptr }, // Inst #3248 = VSELGES
9082 { 3249, 3, 1, 4, 770, 0, 0x8800ULL, ImplicitList1, nullptr, OperandInfo252, -1 ,nullptr }, // Inst #3249 = VSELGTD
9083 { 3250, 3, 1, 4, 770, 0, 0x8800ULL, ImplicitList1, nullptr, OperandInfo326, -1 ,nullptr }, // Inst #3250 = VSELGTH
9084 { 3251, 3, 1, 4, 770, 0, 0x8800ULL, ImplicitList1, nullptr, OperandInfo327, -1 ,nullptr }, // Inst #3251 = VSELGTS
9085 { 3252, 3, 1, 4, 770, 0, 0x8800ULL, ImplicitList1, nullptr, OperandInfo252, -1 ,nullptr }, // Inst #3252 = VSELVSD
9086 { 3253, 3, 1, 4, 770, 0, 0x8800ULL, ImplicitList1, nullptr, OperandInfo326, -1 ,nullptr }, // Inst #3253 = VSELVSH
9087 { 3254, 3, 1, 4, 770, 0, 0x8800ULL, ImplicitList1, nullptr, OperandInfo327, -1 ,nullptr }, // Inst #3254 = VSELVSS
9572 { 3739, 6, 1, 4, 690, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef)|(1ULL<<MCID::HasPostISelHook), 0xc80ULL, ImplicitList1, ImplicitList1, OperandInfo447, -1 ,nullptr }, // Inst #3739 = t2ADCri
9572 { 3739, 6, 1, 4, 690, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef)|(1ULL<<MCID::HasPostISelHook), 0xc80ULL, ImplicitList1, ImplicitList1, OperandInfo447, -1 ,nullptr }, // Inst #3739 = t2ADCri
9573 { 3740, 6, 1, 4, 697, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasOptionalDef)|(1ULL<<MCID::HasPostISelHook), 0xc80ULL, ImplicitList1, ImplicitList1, OperandInfo448, -1 ,nullptr }, // Inst #3740 = t2ADCrr
9573 { 3740, 6, 1, 4, 697, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasOptionalDef)|(1ULL<<MCID::HasPostISelHook), 0xc80ULL, ImplicitList1, ImplicitList1, OperandInfo448, -1 ,nullptr }, // Inst #3740 = t2ADCrr
9574 { 3741, 7, 1, 4, 702, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef)|(1ULL<<MCID::HasPostISelHook), 0xc80ULL, ImplicitList1, ImplicitList1, OperandInfo449, -1 ,nullptr }, // Inst #3741 = t2ADCrs
9574 { 3741, 7, 1, 4, 702, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef)|(1ULL<<MCID::HasPostISelHook), 0xc80ULL, ImplicitList1, ImplicitList1, OperandInfo449, -1 ,nullptr }, // Inst #3741 = t2ADCrs
9603 { 3770, 4, 0, 4, 51, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, ImplicitList1, OperandInfo94, -1 ,nullptr }, // Inst #3770 = t2CMNri
9604 { 3771, 4, 0, 4, 52, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, ImplicitList1, OperandInfo460, -1 ,nullptr }, // Inst #3771 = t2CMNzrr
9605 { 3772, 5, 0, 4, 280, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, ImplicitList1, OperandInfo461, -1 ,nullptr }, // Inst #3772 = t2CMNzrs
9606 { 3773, 4, 0, 4, 281, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, ImplicitList1, OperandInfo94, -1 ,nullptr }, // Inst #3773 = t2CMPri
9607 { 3774, 4, 0, 4, 282, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, ImplicitList1, OperandInfo460, -1 ,nullptr }, // Inst #3774 = t2CMPrr
9608 { 3775, 5, 0, 4, 283, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, ImplicitList1, OperandInfo461, -1 ,nullptr }, // Inst #3775 = t2CMPrs
9618 { 3785, 4, 1, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, ImplicitList1, nullptr, OperandInfo463, -1 ,nullptr }, // Inst #3785 = t2CSEL
9619 { 3786, 4, 1, 4, 0, 0, 0xc80ULL, ImplicitList1, nullptr, OperandInfo463, -1 ,nullptr }, // Inst #3786 = t2CSINC
9620 { 3787, 4, 1, 4, 0, 0, 0xc80ULL, ImplicitList1, nullptr, OperandInfo463, -1 ,nullptr }, // Inst #3787 = t2CSINV
9621 { 3788, 4, 1, 4, 0, 0, 0xc80ULL, ImplicitList1, nullptr, OperandInfo463, -1 ,nullptr }, // Inst #3788 = t2CSNEG
9723 { 3890, 4, 1, 4, 688, 0|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, ImplicitList1, OperandInfo459, -1 ,nullptr }, // Inst #3890 = t2MOVsra_flag
9724 { 3891, 4, 1, 4, 688, 0|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, ImplicitList1, OperandInfo459, -1 ,nullptr }, // Inst #3891 = t2MOVsrl_flag
9733 { 3900, 4, 0, 4, 1018, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, ImplicitList1, OperandInfo477, -1 ,nullptr }, // Inst #3900 = t2MSR_AR
9734 { 3901, 4, 0, 4, 1018, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, ImplicitList1, OperandInfo477, -1 ,nullptr }, // Inst #3901 = t2MSR_M
9779 { 3946, 5, 1, 4, 872, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0xc80ULL, ImplicitList1, nullptr, OperandInfo479, -1 ,nullptr }, // Inst #3946 = t2RRX
9787 { 3954, 6, 1, 4, 690, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef)|(1ULL<<MCID::HasPostISelHook), 0xc80ULL, ImplicitList1, ImplicitList1, OperandInfo447, -1 ,nullptr }, // Inst #3954 = t2SBCri
9787 { 3954, 6, 1, 4, 690, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef)|(1ULL<<MCID::HasPostISelHook), 0xc80ULL, ImplicitList1, ImplicitList1, OperandInfo447, -1 ,nullptr }, // Inst #3954 = t2SBCri
9788 { 3955, 6, 1, 4, 697, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef)|(1ULL<<MCID::HasPostISelHook), 0xc80ULL, ImplicitList1, ImplicitList1, OperandInfo448, -1 ,nullptr }, // Inst #3955 = t2SBCrr
9788 { 3955, 6, 1, 4, 697, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef)|(1ULL<<MCID::HasPostISelHook), 0xc80ULL, ImplicitList1, ImplicitList1, OperandInfo448, -1 ,nullptr }, // Inst #3955 = t2SBCrr
9789 { 3956, 7, 1, 4, 702, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef)|(1ULL<<MCID::HasPostISelHook), 0xc80ULL, ImplicitList1, ImplicitList1, OperandInfo449, -1 ,nullptr }, // Inst #3956 = t2SBCrs
9789 { 3956, 7, 1, 4, 702, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef)|(1ULL<<MCID::HasPostISelHook), 0xc80ULL, ImplicitList1, ImplicitList1, OperandInfo449, -1 ,nullptr }, // Inst #3956 = t2SBCrs
9912 { 4079, 4, 0, 4, 310, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, ImplicitList1, OperandInfo454, -1 ,nullptr }, // Inst #4079 = t2TEQri
9913 { 4080, 4, 0, 4, 311, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, ImplicitList1, OperandInfo459, -1 ,nullptr }, // Inst #4080 = t2TEQrr
9914 { 4081, 5, 0, 4, 312, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, ImplicitList1, OperandInfo102, -1 ,nullptr }, // Inst #4081 = t2TEQrs
9916 { 4083, 4, 0, 4, 310, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, ImplicitList1, OperandInfo454, -1 ,nullptr }, // Inst #4083 = t2TSTri
9917 { 4084, 4, 0, 4, 311, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, ImplicitList1, OperandInfo459, -1 ,nullptr }, // Inst #4084 = t2TSTrr
9918 { 4085, 5, 0, 4, 312, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, ImplicitList1, OperandInfo102, -1 ,nullptr }, // Inst #4085 = t2TSTrs
9958 { 4125, 6, 2, 2, 37, 0|(1ULL<<MCID::Add)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasOptionalDef)|(1ULL<<MCID::UnmodeledSideEffects), 0x80c80ULL, ImplicitList1, nullptr, OperandInfo497, -1 ,nullptr }, // Inst #4125 = tADC
9983 { 4150, 4, 0, 2, 282, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, ImplicitList1, OperandInfo510, -1 ,nullptr }, // Inst #4150 = tCMNz
9984 { 4151, 4, 0, 2, 282, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, ImplicitList1, OperandInfo137, -1 ,nullptr }, // Inst #4151 = tCMPhir
9985 { 4152, 4, 0, 2, 281, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, ImplicitList1, OperandInfo120, -1 ,nullptr }, // Inst #4152 = tCMPi8
9986 { 4153, 4, 0, 2, 282, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, ImplicitList1, OperandInfo510, -1 ,nullptr }, // Inst #4153 = tCMPr
10009 { 4176, 2, 1, 2, 1016, 0|(1ULL<<MCID::MoveReg), 0xc80ULL, nullptr, ImplicitList1, OperandInfo126, -1 ,nullptr }, // Inst #4176 = tMOVSr
10023 { 4190, 6, 2, 2, 37, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef)|(1ULL<<MCID::UnmodeledSideEffects), 0x80c80ULL, ImplicitList1, nullptr, OperandInfo497, -1 ,nullptr }, // Inst #4190 = tSBC
10041 { 4208, 4, 0, 2, 320, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0xc80ULL, nullptr, ImplicitList1, OperandInfo510, -1 ,nullptr }, // Inst #4208 = tTST