|
|
reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
|
References
gen/lib/Target/ARM/ARMGenAsmMatcher.inc10283 { 50 /* and */, ARM::ANDri, Convert__Reg1_2__Reg1_2__ModImm1_3__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_ModImm }, },
10296 { 50 /* and */, ARM::ANDri, Convert__Reg1_2__Reg1_3__ModImm1_4__CondCode2_1__CCOut1_0, AMFBS_IsARM, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_ModImm }, },
10342 { 96 /* bic */, ARM::ANDri, Convert__Reg1_2__Reg1_2__ModImmNot1_3__CondCode2_1__CCOut1_0, AMFBS_IsARM_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_ModImmNot }, },
10355 { 96 /* bic */, ARM::ANDri, Convert__Reg1_2__Reg1_3__ModImmNot1_4__CondCode2_1__CCOut1_0, AMFBS_IsARM_UseNegativeImmediates, { MCK_CCOut, MCK_CondCode, MCK_GPR, MCK_GPR, MCK_ModImmNot }, },
gen/lib/Target/ARM/ARMGenDAGISel.inc 9503 /* 20102*/ OPC_MorphNodeTo1, TARGET_VAL(ARM::ANDri), 0,
gen/lib/Target/ARM/ARMGenFastISel.inc 6292 return fastEmitInst_ri(ARM::ANDri, &ARM::GPRRegClass, Op0, Op0IsKill, imm1);
gen/lib/Target/ARM/ARMGenGlobalISel.inc 5323 GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::ANDri,
gen/lib/Target/ARM/ARMGenMCCodeEmitter.inc14315 case ARM::ANDri:
lib/Target/ARM/ARMBaseInstrInfo.cpp 2717 case ARM::ANDri:
2877 case ARM::ANDri:
lib/Target/ARM/ARMFastISel.cpp 1065 unsigned Opc = isThumb2 ? ARM::t2ANDri : ARM::ANDri;
2655 /* 1 bit zext */ { ARM::ANDri , 1, ARM_AM::no_shift, 1 } },
2657 /* 8 bit zext */ { ARM::ANDri , 1, ARM_AM::no_shift, 255 } },
2900 { { ARM::ANDri, ARM::t2ANDri }, 255, 1, MVT::i8 },
lib/Target/ARM/ARMInstructionSelector.cpp 305 STORE_OPCODE(AND, ANDri);
lib/Target/ARM/ARMMCInstLower.cpp 144 case ARM::ANDri: