|
|
reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
|
References
gen/lib/Target/ARM/ARMGenDisassemblerTables.inc16765 tmp = fieldFromInstruction(insn, 12, 4);
16766 if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
16767 tmp = fieldFromInstruction(insn, 16, 4);
16768 if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
16769 tmp = fieldFromInstruction(insn, 0, 4);
16770 if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
16771 tmp = fieldFromInstruction(insn, 28, 4);
16772 if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
16773 tmp = fieldFromInstruction(insn, 20, 1);
16774 if (!Check(S, DecodeCCOutOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
16777 tmp = fieldFromInstruction(insn, 12, 4);
16778 if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
16779 tmp = fieldFromInstruction(insn, 16, 4);
16780 if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
16781 tmp = 0x0;
16782 tmp |= fieldFromInstruction(insn, 0, 4) << 0;
16783 tmp |= fieldFromInstruction(insn, 5, 7) << 5;
16784 if (!Check(S, DecodeSORegImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
16785 tmp = fieldFromInstruction(insn, 28, 4);
16786 if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
16787 tmp = fieldFromInstruction(insn, 20, 1);
16788 if (!Check(S, DecodeCCOutOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
16791 tmp = fieldFromInstruction(insn, 12, 4);
16792 if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
16793 tmp = fieldFromInstruction(insn, 16, 4);
16794 if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
16795 tmp = 0x0;
16796 tmp |= fieldFromInstruction(insn, 0, 4) << 0;
16797 tmp |= fieldFromInstruction(insn, 5, 2) << 5;
16798 tmp |= fieldFromInstruction(insn, 8, 4) << 8;
16799 if (!Check(S, DecodeSORegRegOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
16800 tmp = fieldFromInstruction(insn, 28, 4);
16801 if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
16802 tmp = fieldFromInstruction(insn, 20, 1);
16803 if (!Check(S, DecodeCCOutOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
16806 tmp = fieldFromInstruction(insn, 12, 4);
16807 if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
16808 tmp = fieldFromInstruction(insn, 16, 4);
16809 if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
16810 tmp = 0x0;
16811 tmp |= fieldFromInstruction(insn, 0, 4) << 0;
16812 tmp |= fieldFromInstruction(insn, 5, 2) << 5;
16813 tmp |= fieldFromInstruction(insn, 8, 4) << 8;
16814 if (!Check(S, DecodeSORegRegOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
16815 tmp = fieldFromInstruction(insn, 28, 4);
16816 if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
16817 tmp = fieldFromInstruction(insn, 20, 1);
16818 if (!Check(S, DecodeCCOutOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
16821 tmp = fieldFromInstruction(insn, 16, 4);
16822 if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
16823 tmp = fieldFromInstruction(insn, 0, 4);
16824 if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
16825 tmp = fieldFromInstruction(insn, 8, 4);
16826 if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
16827 tmp = fieldFromInstruction(insn, 28, 4);
16828 if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
16829 tmp = fieldFromInstruction(insn, 20, 1);
16830 if (!Check(S, DecodeCCOutOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
16833 tmp = fieldFromInstruction(insn, 12, 4);
16834 if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
16835 tmp = fieldFromInstruction(insn, 16, 4);
16836 if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
16837 tmp = fieldFromInstruction(insn, 0, 4);
16838 if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
16839 tmp = fieldFromInstruction(insn, 8, 4);
16840 if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
16841 tmp = fieldFromInstruction(insn, 12, 4);
16842 if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
16843 tmp = fieldFromInstruction(insn, 16, 4);
16844 if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
16845 tmp = fieldFromInstruction(insn, 28, 4);
16846 if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
16849 tmp = fieldFromInstruction(insn, 12, 4);
16850 if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
16851 tmp = fieldFromInstruction(insn, 16, 4);
16852 if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
16853 tmp = fieldFromInstruction(insn, 0, 4);
16854 if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
16855 tmp = fieldFromInstruction(insn, 8, 4);
16856 if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
16857 tmp = fieldFromInstruction(insn, 28, 4);
16858 if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
16859 tmp = fieldFromInstruction(insn, 20, 1);
16860 if (!Check(S, DecodeCCOutOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
16866 tmp = fieldFromInstruction(insn, 12, 4);
16867 if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
16868 tmp = fieldFromInstruction(insn, 16, 4);
16869 if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
16870 tmp = fieldFromInstruction(insn, 0, 4);
16871 if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
16877 tmp = fieldFromInstruction(insn, 9, 1);
16878 MI.addOperand(MCOperand::createImm(tmp));
16881 tmp = fieldFromInstruction(insn, 12, 4);
16882 if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
16883 tmp = fieldFromInstruction(insn, 28, 4);
16884 if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
16896 tmp = 0x0;
16897 tmp |= fieldFromInstruction(insn, 0, 4) << 0;
16898 tmp |= fieldFromInstruction(insn, 8, 12) << 4;
16899 MI.addOperand(MCOperand::createImm(tmp));
16905 tmp = fieldFromInstruction(insn, 16, 4);
16906 if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
16907 tmp = 0x0;
16908 tmp |= fieldFromInstruction(insn, 0, 4) << 0;
16909 tmp |= fieldFromInstruction(insn, 5, 7) << 5;
16910 if (!Check(S, DecodeSORegImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
16911 tmp = fieldFromInstruction(insn, 28, 4);
16912 if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
16915 tmp = fieldFromInstruction(insn, 16, 4);
16916 if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
16917 tmp = 0x0;
16918 tmp |= fieldFromInstruction(insn, 0, 4) << 0;
16919 tmp |= fieldFromInstruction(insn, 5, 2) << 5;
16920 tmp |= fieldFromInstruction(insn, 8, 4) << 8;
16921 if (!Check(S, DecodeSORegRegOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
16922 tmp = fieldFromInstruction(insn, 28, 4);
16923 if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
16926 tmp = fieldFromInstruction(insn, 12, 4);
16927 if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
16928 tmp = fieldFromInstruction(insn, 16, 4);
16929 if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
16930 tmp = fieldFromInstruction(insn, 0, 4);
16931 if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
16932 tmp = fieldFromInstruction(insn, 8, 4);
16933 if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
16934 tmp = fieldFromInstruction(insn, 12, 4);
16935 if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
16936 tmp = fieldFromInstruction(insn, 16, 4);
16937 if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
16938 tmp = fieldFromInstruction(insn, 28, 4);
16939 if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
16942 tmp = fieldFromInstruction(insn, 16, 4);
16943 if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
16944 tmp = fieldFromInstruction(insn, 0, 4);
16945 if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
16946 tmp = fieldFromInstruction(insn, 28, 4);
16947 if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
16950 tmp = fieldFromInstruction(insn, 12, 4);
16951 if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
16952 tmp = fieldFromInstruction(insn, 0, 4);
16953 if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
16954 tmp = fieldFromInstruction(insn, 16, 4);
16955 if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
16956 tmp = fieldFromInstruction(insn, 28, 4);
16957 if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
16960 tmp = fieldFromInstruction(insn, 0, 4);
16961 if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
16962 tmp = fieldFromInstruction(insn, 16, 4);
16963 if (!Check(S, DecodeAddrMode7Operand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
16964 tmp = fieldFromInstruction(insn, 28, 4);
16965 if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
16968 tmp = fieldFromInstruction(insn, 12, 4);
16969 if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
16970 tmp = fieldFromInstruction(insn, 16, 4);
16971 if (!Check(S, DecodeAddrMode7Operand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
16972 tmp = fieldFromInstruction(insn, 28, 4);
16973 if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
16976 tmp = fieldFromInstruction(insn, 12, 4);
16977 if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
16978 tmp = fieldFromInstruction(insn, 0, 4);
16979 if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
16980 tmp = fieldFromInstruction(insn, 16, 4);
16981 if (!Check(S, DecodeAddrMode7Operand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
16982 tmp = fieldFromInstruction(insn, 28, 4);
16983 if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
16986 tmp = fieldFromInstruction(insn, 12, 4);
16987 if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
16988 tmp = 0x0;
16989 tmp |= fieldFromInstruction(insn, 8, 1) << 4;
16990 tmp |= fieldFromInstruction(insn, 16, 4) << 0;
16991 tmp |= fieldFromInstruction(insn, 22, 1) << 5;
16992 if (!Check(S, DecodeBankedReg(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
16993 tmp = fieldFromInstruction(insn, 28, 4);
16994 if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
16997 tmp = 0x0;
16998 tmp |= fieldFromInstruction(insn, 16, 4) << 0;
16999 tmp |= fieldFromInstruction(insn, 22, 1) << 4;
17000 if (!Check(S, DecodeMSRMask(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
17001 tmp = fieldFromInstruction(insn, 0, 4);
17002 if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
17003 tmp = fieldFromInstruction(insn, 28, 4);
17004 if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
17007 tmp = 0x0;
17008 tmp |= fieldFromInstruction(insn, 8, 1) << 4;
17009 tmp |= fieldFromInstruction(insn, 16, 4) << 0;
17010 tmp |= fieldFromInstruction(insn, 22, 1) << 5;
17011 if (!Check(S, DecodeBankedReg(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
17012 tmp = fieldFromInstruction(insn, 0, 4);
17013 if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
17014 tmp = fieldFromInstruction(insn, 28, 4);
17015 if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
17018 tmp = fieldFromInstruction(insn, 0, 4);
17019 if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
17020 tmp = fieldFromInstruction(insn, 28, 4);
17021 if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
17024 tmp = fieldFromInstruction(insn, 28, 4);
17025 if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
17028 tmp = fieldFromInstruction(insn, 16, 4);
17029 if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
17030 tmp = fieldFromInstruction(insn, 0, 4);
17031 if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
17032 tmp = fieldFromInstruction(insn, 8, 4);
17033 if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
17034 tmp = fieldFromInstruction(insn, 28, 4);
17035 if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
17038 tmp = fieldFromInstruction(insn, 12, 4);
17039 if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
17040 tmp = fieldFromInstruction(insn, 0, 4);
17041 if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
17042 tmp = fieldFromInstruction(insn, 28, 4);
17043 if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
17044 tmp = fieldFromInstruction(insn, 20, 1);
17045 if (!Check(S, DecodeCCOutOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
17048 tmp = fieldFromInstruction(insn, 12, 4);
17049 if (!Check(S, DecodetcGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
17050 tmp = fieldFromInstruction(insn, 0, 4);
17051 if (!Check(S, DecodetcGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
17052 tmp = fieldFromInstruction(insn, 28, 4);
17053 if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
17054 tmp = fieldFromInstruction(insn, 20, 1);
17055 if (!Check(S, DecodeCCOutOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
17058 tmp = fieldFromInstruction(insn, 12, 4);
17059 if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
17060 tmp = 0x0;
17061 tmp |= fieldFromInstruction(insn, 0, 4) << 0;
17062 tmp |= fieldFromInstruction(insn, 5, 7) << 5;
17063 if (!Check(S, DecodeSORegImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
17064 tmp = fieldFromInstruction(insn, 28, 4);
17065 if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
17066 tmp = fieldFromInstruction(insn, 20, 1);
17067 if (!Check(S, DecodeCCOutOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
17070 tmp = fieldFromInstruction(insn, 0, 4);
17071 if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
17074 tmp = fieldFromInstruction(insn, 12, 4);
17075 if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
17076 tmp = fieldFromInstruction(insn, 0, 4);
17077 if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
17078 tmp = fieldFromInstruction(insn, 28, 4);
17079 if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
17082 tmp = fieldFromInstruction(insn, 0, 4);
17083 MI.addOperand(MCOperand::createImm(tmp));
17084 tmp = fieldFromInstruction(insn, 28, 4);
17085 if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
17088 tmp = fieldFromInstruction(insn, 12, 4);
17089 if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
17090 tmp = 0x0;
17091 tmp |= fieldFromInstruction(insn, 0, 4) << 0;
17092 tmp |= fieldFromInstruction(insn, 5, 2) << 5;
17093 tmp |= fieldFromInstruction(insn, 8, 4) << 8;
17094 if (!Check(S, DecodeSORegRegOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
17095 tmp = fieldFromInstruction(insn, 28, 4);
17096 if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
17097 tmp = fieldFromInstruction(insn, 20, 1);
17098 if (!Check(S, DecodeCCOutOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
17101 tmp = fieldFromInstruction(insn, 16, 4);
17102 if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
17103 tmp = fieldFromInstruction(insn, 0, 4);
17104 if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
17105 tmp = fieldFromInstruction(insn, 8, 4);
17106 if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
17107 tmp = fieldFromInstruction(insn, 12, 4);
17108 if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
17109 tmp = fieldFromInstruction(insn, 28, 4);
17110 if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
17111 tmp = fieldFromInstruction(insn, 20, 1);
17112 if (!Check(S, DecodeCCOutOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
17115 tmp = fieldFromInstruction(insn, 16, 4);
17116 if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
17117 tmp = fieldFromInstruction(insn, 0, 4);
17118 if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
17119 tmp = fieldFromInstruction(insn, 8, 4);
17120 if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
17121 tmp = fieldFromInstruction(insn, 12, 4);
17122 if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
17123 tmp = fieldFromInstruction(insn, 28, 4);
17124 if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
17127 tmp = fieldFromInstruction(insn, 12, 4);
17128 if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
17129 tmp = fieldFromInstruction(insn, 16, 4);
17130 if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
17131 tmp = fieldFromInstruction(insn, 0, 4);
17132 if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
17133 tmp = fieldFromInstruction(insn, 8, 4);
17134 if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
17135 tmp = fieldFromInstruction(insn, 12, 4);
17136 if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
17137 tmp = fieldFromInstruction(insn, 16, 4);
17138 if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
17139 tmp = fieldFromInstruction(insn, 28, 4);
17140 if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
17141 tmp = fieldFromInstruction(insn, 20, 1);
17142 if (!Check(S, DecodeCCOutOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
17151 tmp = fieldFromInstruction(insn, 16, 4);
17152 if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
17153 tmp = fieldFromInstruction(insn, 12, 4);
17154 if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
17155 tmp = fieldFromInstruction(insn, 16, 4);
17156 if (!Check(S, DecodeAddrMode7Operand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
17157 tmp = 0x0;
17158 tmp |= fieldFromInstruction(insn, 0, 4) << 0;
17159 tmp |= fieldFromInstruction(insn, 23, 1) << 4;
17160 if (!Check(S, DecodePostIdxReg(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
17161 tmp = fieldFromInstruction(insn, 28, 4);
17162 if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
17165 tmp = fieldFromInstruction(insn, 16, 4);
17166 if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
17167 tmp = fieldFromInstruction(insn, 12, 4);
17168 if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
17169 tmp = fieldFromInstruction(insn, 16, 4);
17170 if (!Check(S, DecodeAddrMode7Operand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
17171 tmp = 0x0;
17172 tmp |= fieldFromInstruction(insn, 0, 4) << 0;
17173 tmp |= fieldFromInstruction(insn, 8, 4) << 4;
17174 tmp |= fieldFromInstruction(insn, 23, 1) << 8;
17175 MI.addOperand(MCOperand::createImm(tmp));
17176 tmp = fieldFromInstruction(insn, 28, 4);
17177 if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
17183 tmp = fieldFromInstruction(insn, 12, 4);
17184 if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
17185 tmp = fieldFromInstruction(insn, 16, 4);
17186 if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
17187 tmp = fieldFromInstruction(insn, 16, 4);
17188 if (!Check(S, DecodeAddrMode7Operand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
17189 tmp = 0x0;
17190 tmp |= fieldFromInstruction(insn, 0, 4) << 0;
17191 tmp |= fieldFromInstruction(insn, 8, 4) << 4;
17192 tmp |= fieldFromInstruction(insn, 23, 1) << 8;
17193 MI.addOperand(MCOperand::createImm(tmp));
17194 tmp = fieldFromInstruction(insn, 28, 4);
17195 if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
17198 tmp = fieldFromInstruction(insn, 12, 4);
17199 if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
17200 tmp = fieldFromInstruction(insn, 16, 4);
17201 if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
17202 tmp = fieldFromInstruction(insn, 0, 12);
17203 MI.addOperand(MCOperand::createImm(tmp));
17204 tmp = fieldFromInstruction(insn, 28, 4);
17205 if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
17206 tmp = fieldFromInstruction(insn, 20, 1);
17207 if (!Check(S, DecodeCCOutOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
17210 tmp = fieldFromInstruction(insn, 12, 4);
17211 if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
17212 tmp = 0x0;
17213 tmp |= fieldFromInstruction(insn, 0, 12) << 0;
17214 tmp |= fieldFromInstruction(insn, 22, 2) << 12;
17215 MI.addOperand(MCOperand::createImm(tmp));
17216 tmp = fieldFromInstruction(insn, 28, 4);
17217 if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
17223 tmp = fieldFromInstruction(insn, 16, 4);
17224 if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
17225 tmp = fieldFromInstruction(insn, 0, 12);
17226 MI.addOperand(MCOperand::createImm(tmp));
17227 tmp = fieldFromInstruction(insn, 28, 4);
17228 if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
17236 tmp = 0x0;
17237 tmp |= fieldFromInstruction(insn, 16, 4) << 0;
17238 tmp |= fieldFromInstruction(insn, 22, 1) << 4;
17239 if (!Check(S, DecodeMSRMask(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
17240 tmp = fieldFromInstruction(insn, 0, 12);
17241 MI.addOperand(MCOperand::createImm(tmp));
17242 tmp = fieldFromInstruction(insn, 28, 4);
17243 if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
17246 tmp = fieldFromInstruction(insn, 12, 4);
17247 if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
17248 tmp = fieldFromInstruction(insn, 0, 12);
17249 MI.addOperand(MCOperand::createImm(tmp));
17250 tmp = fieldFromInstruction(insn, 28, 4);
17251 if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
17252 tmp = fieldFromInstruction(insn, 20, 1);
17253 if (!Check(S, DecodeCCOutOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
17259 tmp = fieldFromInstruction(insn, 12, 4);
17260 if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
17261 tmp = 0x0;
17262 tmp |= fieldFromInstruction(insn, 0, 12) << 0;
17263 tmp |= fieldFromInstruction(insn, 16, 4) << 13;
17264 tmp |= fieldFromInstruction(insn, 23, 1) << 12;
17265 if (!Check(S, DecodeAddrModeImm12Operand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
17266 tmp = fieldFromInstruction(insn, 28, 4);
17267 if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
17270 tmp = 0x0;
17271 tmp |= fieldFromInstruction(insn, 0, 12) << 0;
17272 tmp |= fieldFromInstruction(insn, 16, 4) << 13;
17273 tmp |= fieldFromInstruction(insn, 23, 1) << 12;
17274 if (!Check(S, DecodeAddrModeImm12Operand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
17283 tmp = fieldFromInstruction(insn, 12, 4);
17284 if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
17285 tmp = 0x0;
17286 tmp |= fieldFromInstruction(insn, 0, 12) << 0;
17287 tmp |= fieldFromInstruction(insn, 16, 4) << 13;
17288 tmp |= fieldFromInstruction(insn, 23, 1) << 12;
17289 if (!Check(S, DecodeAddrModeImm12Operand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
17290 tmp = fieldFromInstruction(insn, 28, 4);
17291 if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
17294 tmp = fieldFromInstruction(insn, 0, 4);
17295 if (!Check(S, DecodeMemBarrierOption(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
17298 tmp = fieldFromInstruction(insn, 0, 4);
17299 if (!Check(S, DecodeInstSyncBarrierOption(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
17302 tmp = fieldFromInstruction(insn, 12, 4);
17303 if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
17304 tmp = 0x0;
17305 tmp |= fieldFromInstruction(insn, 0, 4) << 0;
17306 tmp |= fieldFromInstruction(insn, 5, 7) << 5;
17307 tmp |= fieldFromInstruction(insn, 16, 4) << 13;
17308 tmp |= fieldFromInstruction(insn, 23, 1) << 12;
17309 if (!Check(S, DecodeSORegMemOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
17310 tmp = fieldFromInstruction(insn, 28, 4);
17311 if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
17314 tmp = 0x0;
17315 tmp |= fieldFromInstruction(insn, 0, 4) << 0;
17316 tmp |= fieldFromInstruction(insn, 5, 7) << 5;
17317 tmp |= fieldFromInstruction(insn, 16, 4) << 13;
17318 tmp |= fieldFromInstruction(insn, 23, 1) << 12;
17319 if (!Check(S, DecodeSORegMemOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
17322 tmp = fieldFromInstruction(insn, 12, 4);
17323 if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
17324 tmp = fieldFromInstruction(insn, 16, 4);
17325 if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
17326 tmp = fieldFromInstruction(insn, 0, 4);
17327 if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
17328 tmp = fieldFromInstruction(insn, 28, 4);
17329 if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
17332 tmp = fieldFromInstruction(insn, 12, 4);
17333 if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
17334 tmp = fieldFromInstruction(insn, 16, 4);
17335 if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
17336 tmp = fieldFromInstruction(insn, 0, 4);
17337 if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
17338 tmp = fieldFromInstruction(insn, 7, 5);
17339 MI.addOperand(MCOperand::createImm(tmp));
17340 tmp = fieldFromInstruction(insn, 28, 4);
17341 if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
17344 tmp = fieldFromInstruction(insn, 16, 4);
17345 if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
17346 tmp = fieldFromInstruction(insn, 0, 4);
17347 if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
17348 tmp = fieldFromInstruction(insn, 8, 4);
17349 if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
17350 tmp = fieldFromInstruction(insn, 28, 4);
17351 if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
17354 tmp = fieldFromInstruction(insn, 16, 4);
17355 if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
17356 tmp = fieldFromInstruction(insn, 0, 4);
17357 if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
17358 tmp = fieldFromInstruction(insn, 8, 4);
17359 if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
17360 tmp = fieldFromInstruction(insn, 12, 4);
17361 if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
17362 tmp = fieldFromInstruction(insn, 28, 4);
17363 if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
17366 tmp = fieldFromInstruction(insn, 12, 4);
17367 if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
17368 tmp = fieldFromInstruction(insn, 16, 4);
17369 if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
17370 tmp = fieldFromInstruction(insn, 0, 4);
17371 if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
17372 tmp = fieldFromInstruction(insn, 28, 4);
17373 if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
17376 tmp = fieldFromInstruction(insn, 12, 4);
17377 if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
17378 tmp = fieldFromInstruction(insn, 0, 4);
17379 if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
17380 tmp = fieldFromInstruction(insn, 10, 2);
17381 MI.addOperand(MCOperand::createImm(tmp));
17382 tmp = fieldFromInstruction(insn, 28, 4);
17383 if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
17386 tmp = fieldFromInstruction(insn, 12, 4);
17387 if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
17388 tmp = fieldFromInstruction(insn, 16, 4);
17389 if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
17390 tmp = fieldFromInstruction(insn, 0, 4);
17391 if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
17392 tmp = fieldFromInstruction(insn, 10, 2);
17393 MI.addOperand(MCOperand::createImm(tmp));
17394 tmp = fieldFromInstruction(insn, 28, 4);
17395 if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
17404 tmp = fieldFromInstruction(insn, 12, 4);
17405 if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
17406 tmp = fieldFromInstruction(insn, 16, 5);
17407 MI.addOperand(MCOperand::createImm(tmp));
17408 tmp = fieldFromInstruction(insn, 0, 4);
17409 if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
17410 tmp = 0x0;
17411 tmp |= fieldFromInstruction(insn, 6, 1) << 5;
17412 tmp |= fieldFromInstruction(insn, 7, 5) << 0;
17413 MI.addOperand(MCOperand::createImm(tmp));
17414 tmp = fieldFromInstruction(insn, 28, 4);
17415 if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
17418 tmp = fieldFromInstruction(insn, 12, 4);
17419 if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
17420 tmp = fieldFromInstruction(insn, 16, 4);
17421 MI.addOperand(MCOperand::createImm(tmp));
17422 tmp = fieldFromInstruction(insn, 0, 4);
17423 if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
17424 tmp = fieldFromInstruction(insn, 28, 4);
17425 if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
17428 tmp = fieldFromInstruction(insn, 12, 4);
17429 if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
17430 tmp = fieldFromInstruction(insn, 0, 4);
17431 if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
17432 tmp = fieldFromInstruction(insn, 7, 5);
17433 MI.addOperand(MCOperand::createImm(tmp));
17434 tmp = fieldFromInstruction(insn, 16, 5);
17435 MI.addOperand(MCOperand::createImm(tmp));
17436 tmp = fieldFromInstruction(insn, 28, 4);
17437 if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
17440 tmp = fieldFromInstruction(insn, 12, 4);
17441 if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
17442 tmp = 0x0;
17443 tmp |= fieldFromInstruction(insn, 0, 4) << 0;
17444 tmp |= fieldFromInstruction(insn, 5, 7) << 5;
17445 tmp |= fieldFromInstruction(insn, 16, 4) << 13;
17446 tmp |= fieldFromInstruction(insn, 23, 1) << 12;
17447 if (!Check(S, DecodeSORegMemOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
17448 tmp = fieldFromInstruction(insn, 28, 4);
17449 if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
17452 tmp = fieldFromInstruction(insn, 12, 4);
17453 if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
17454 tmp = fieldFromInstruction(insn, 12, 4);
17455 if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
17456 tmp = 0x0;
17457 tmp |= fieldFromInstruction(insn, 7, 5) << 0;
17458 tmp |= fieldFromInstruction(insn, 16, 5) << 5;
17459 if (!Check(S, DecodeBitfieldMaskOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
17460 tmp = fieldFromInstruction(insn, 28, 4);
17461 if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
17464 tmp = fieldFromInstruction(insn, 12, 4);
17465 if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
17466 tmp = fieldFromInstruction(insn, 12, 4);
17467 if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
17468 tmp = fieldFromInstruction(insn, 0, 4);
17469 if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
17470 tmp = 0x0;
17471 tmp |= fieldFromInstruction(insn, 7, 5) << 0;
17472 tmp |= fieldFromInstruction(insn, 16, 5) << 5;
17473 if (!Check(S, DecodeBitfieldMaskOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
17474 tmp = fieldFromInstruction(insn, 28, 4);
17475 if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
17478 tmp = fieldFromInstruction(insn, 16, 4);
17479 if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
17480 tmp = fieldFromInstruction(insn, 28, 4);
17481 if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
17482 tmp = fieldFromInstruction(insn, 0, 16);
17483 if (!Check(S, DecodeRegListOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
17486 tmp = fieldFromInstruction(insn, 16, 4);
17487 if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
17493 tmp = fieldFromInstruction(insn, 0, 5);
17494 MI.addOperand(MCOperand::createImm(tmp));
17500 tmp = 0x0;
17501 tmp |= fieldFromInstruction(insn, 0, 24) << 1;
17502 tmp |= fieldFromInstruction(insn, 24, 1) << 0;
17503 MI.addOperand(MCOperand::createImm(tmp));
17509 tmp = fieldFromInstruction(insn, 8, 4);
17510 if (!Check(S, DecodeCoprocessor(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
17511 tmp = fieldFromInstruction(insn, 4, 4);
17512 MI.addOperand(MCOperand::createImm(tmp));
17513 tmp = fieldFromInstruction(insn, 12, 4);
17514 if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
17515 tmp = fieldFromInstruction(insn, 16, 4);
17516 if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
17517 tmp = fieldFromInstruction(insn, 0, 4);
17518 MI.addOperand(MCOperand::createImm(tmp));
17519 tmp = fieldFromInstruction(insn, 28, 4);
17520 if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
17523 tmp = fieldFromInstruction(insn, 12, 4);
17524 if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
17525 tmp = fieldFromInstruction(insn, 16, 4);
17526 if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
17527 tmp = fieldFromInstruction(insn, 8, 4);
17528 if (!Check(S, DecodeCoprocessor(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
17529 tmp = fieldFromInstruction(insn, 4, 4);
17530 MI.addOperand(MCOperand::createImm(tmp));
17531 tmp = fieldFromInstruction(insn, 0, 4);
17532 MI.addOperand(MCOperand::createImm(tmp));
17533 tmp = fieldFromInstruction(insn, 28, 4);
17534 if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
17537 tmp = fieldFromInstruction(insn, 0, 24);
17538 MI.addOperand(MCOperand::createImm(tmp));
17539 tmp = fieldFromInstruction(insn, 28, 4);
17540 if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
17546 tmp = fieldFromInstruction(insn, 8, 4);
17547 if (!Check(S, DecodeCoprocessor(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
17548 tmp = fieldFromInstruction(insn, 20, 4);
17549 MI.addOperand(MCOperand::createImm(tmp));
17550 tmp = fieldFromInstruction(insn, 12, 4);
17551 MI.addOperand(MCOperand::createImm(tmp));
17552 tmp = fieldFromInstruction(insn, 16, 4);
17553 MI.addOperand(MCOperand::createImm(tmp));
17554 tmp = fieldFromInstruction(insn, 0, 4);
17555 MI.addOperand(MCOperand::createImm(tmp));
17556 tmp = fieldFromInstruction(insn, 5, 3);
17557 MI.addOperand(MCOperand::createImm(tmp));
17560 tmp = fieldFromInstruction(insn, 8, 4);
17561 if (!Check(S, DecodeCoprocessor(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
17562 tmp = fieldFromInstruction(insn, 20, 4);
17563 MI.addOperand(MCOperand::createImm(tmp));
17564 tmp = fieldFromInstruction(insn, 12, 4);
17565 MI.addOperand(MCOperand::createImm(tmp));
17566 tmp = fieldFromInstruction(insn, 16, 4);
17567 MI.addOperand(MCOperand::createImm(tmp));
17568 tmp = fieldFromInstruction(insn, 0, 4);
17569 MI.addOperand(MCOperand::createImm(tmp));
17570 tmp = fieldFromInstruction(insn, 5, 3);
17571 MI.addOperand(MCOperand::createImm(tmp));
17572 tmp = fieldFromInstruction(insn, 28, 4);
17573 if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
17576 tmp = fieldFromInstruction(insn, 8, 4);
17577 if (!Check(S, DecodeCoprocessor(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
17578 tmp = fieldFromInstruction(insn, 21, 3);
17579 MI.addOperand(MCOperand::createImm(tmp));
17580 tmp = fieldFromInstruction(insn, 12, 4);
17581 if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
17582 tmp = fieldFromInstruction(insn, 16, 4);
17583 MI.addOperand(MCOperand::createImm(tmp));
17584 tmp = fieldFromInstruction(insn, 0, 4);
17585 MI.addOperand(MCOperand::createImm(tmp));
17586 tmp = fieldFromInstruction(insn, 5, 3);
17587 MI.addOperand(MCOperand::createImm(tmp));
17590 tmp = fieldFromInstruction(insn, 8, 4);
17591 if (!Check(S, DecodeCoprocessor(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
17592 tmp = fieldFromInstruction(insn, 21, 3);
17593 MI.addOperand(MCOperand::createImm(tmp));
17594 tmp = fieldFromInstruction(insn, 12, 4);
17595 if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
17596 tmp = fieldFromInstruction(insn, 16, 4);
17597 MI.addOperand(MCOperand::createImm(tmp));
17598 tmp = fieldFromInstruction(insn, 0, 4);
17599 MI.addOperand(MCOperand::createImm(tmp));
17600 tmp = fieldFromInstruction(insn, 5, 3);
17601 MI.addOperand(MCOperand::createImm(tmp));
17602 tmp = fieldFromInstruction(insn, 28, 4);
17603 if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
17606 tmp = fieldFromInstruction(insn, 12, 4);
17607 if (!Check(S, DecodeGPRwithAPSRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
17608 tmp = fieldFromInstruction(insn, 8, 4);
17609 if (!Check(S, DecodeCoprocessor(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
17610 tmp = fieldFromInstruction(insn, 21, 3);
17611 MI.addOperand(MCOperand::createImm(tmp));
17612 tmp = fieldFromInstruction(insn, 16, 4);
17613 MI.addOperand(MCOperand::createImm(tmp));
17614 tmp = fieldFromInstruction(insn, 0, 4);
17615 MI.addOperand(MCOperand::createImm(tmp));
17616 tmp = fieldFromInstruction(insn, 5, 3);
17617 MI.addOperand(MCOperand::createImm(tmp));
17620 tmp = fieldFromInstruction(insn, 12, 4);
17621 if (!Check(S, DecodeGPRwithAPSRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
17622 tmp = fieldFromInstruction(insn, 8, 4);
17623 if (!Check(S, DecodeCoprocessor(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
17624 tmp = fieldFromInstruction(insn, 21, 3);
17625 MI.addOperand(MCOperand::createImm(tmp));
17626 tmp = fieldFromInstruction(insn, 16, 4);
17627 MI.addOperand(MCOperand::createImm(tmp));
17628 tmp = fieldFromInstruction(insn, 0, 4);
17629 MI.addOperand(MCOperand::createImm(tmp));
17630 tmp = fieldFromInstruction(insn, 5, 3);
17631 MI.addOperand(MCOperand::createImm(tmp));
17632 tmp = fieldFromInstruction(insn, 28, 4);
17633 if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
17642 tmp = fieldFromInstruction(insn, 16, 4);
17643 if (!Check(S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
17644 tmp = fieldFromInstruction(insn, 16, 4);
17645 if (!Check(S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
17646 tmp = fieldFromInstruction(insn, 12, 4);
17647 if (!Check(S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
17650 tmp = fieldFromInstruction(insn, 16, 4);
17651 if (!Check(S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
17652 tmp = fieldFromInstruction(insn, 16, 4);
17653 if (!Check(S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
17654 tmp = 0x0;
17655 tmp |= fieldFromInstruction(insn, 6, 2) << 0;
17656 tmp |= fieldFromInstruction(insn, 12, 3) << 2;
17657 if (!Check(S, DecodeLongShiftOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
17660 tmp = fieldFromInstruction(insn, 17, 3) << 1;
17661 if (!Check(S, DecodetGPREvenRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
17662 tmp = fieldFromInstruction(insn, 9, 3) << 1;
17663 if (!Check(S, DecodetGPROddRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
17664 tmp = fieldFromInstruction(insn, 17, 3) << 1;
17665 if (!Check(S, DecodetGPREvenRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
17666 tmp = fieldFromInstruction(insn, 9, 3) << 1;
17667 if (!Check(S, DecodetGPROddRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
17668 tmp = 0x0;
17669 tmp |= fieldFromInstruction(insn, 6, 2) << 0;
17670 tmp |= fieldFromInstruction(insn, 12, 3) << 2;
17671 if (!Check(S, DecodeLongShiftOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
17674 tmp = 0x0;
17675 tmp |= fieldFromInstruction(insn, 13, 3) << 0;
17676 tmp |= fieldFromInstruction(insn, 22, 1) << 3;
17677 if (!Check(S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
17678 tmp = 0x0;
17679 tmp |= fieldFromInstruction(insn, 7, 1) << 3;
17680 tmp |= fieldFromInstruction(insn, 17, 3) << 0;
17681 if (!Check(S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
17682 tmp = 0x0;
17683 tmp |= fieldFromInstruction(insn, 1, 3) << 0;
17684 tmp |= fieldFromInstruction(insn, 5, 1) << 3;
17685 if (!Check(S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
17686 tmp = fieldFromInstruction(insn, 24, 1);
17687 MI.addOperand(MCOperand::createImm(tmp));
17688 tmp = 0x0;
17689 tmp |= fieldFromInstruction(insn, 13, 3) << 0;
17690 tmp |= fieldFromInstruction(insn, 22, 1) << 3;
17691 if (!Check(S, DecodeVpredROperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
17694 tmp = 0x0;
17695 tmp |= fieldFromInstruction(insn, 13, 3) << 0;
17696 tmp |= fieldFromInstruction(insn, 22, 1) << 3;
17697 if (!Check(S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
17698 tmp = 0x0;
17699 tmp |= fieldFromInstruction(insn, 13, 3) << 0;
17700 tmp |= fieldFromInstruction(insn, 22, 1) << 3;
17701 if (!Check(S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
17702 tmp = 0x0;
17703 tmp |= fieldFromInstruction(insn, 7, 1) << 3;
17704 tmp |= fieldFromInstruction(insn, 17, 3) << 0;
17705 if (!Check(S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
17706 tmp = 0x0;
17707 tmp |= fieldFromInstruction(insn, 1, 3) << 0;
17708 tmp |= fieldFromInstruction(insn, 5, 1) << 3;
17709 if (!Check(S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
17710 tmp = fieldFromInstruction(insn, 23, 2);
17711 MI.addOperand(MCOperand::createImm(tmp));
17714 tmp = fieldFromInstruction(insn, 13, 3);
17715 if (!Check(S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
17716 tmp = 0x0;
17717 tmp |= fieldFromInstruction(insn, 1, 3) << 0;
17718 tmp |= fieldFromInstruction(insn, 16, 4) << 3;
17719 if (!Check(S, DecodeMveAddrModeRQ(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
17722 tmp = fieldFromInstruction(insn, 13, 3);
17723 if (!Check(S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
17724 tmp = 0x0;
17725 tmp |= fieldFromInstruction(insn, 0, 7) << 0;
17726 tmp |= fieldFromInstruction(insn, 16, 3) << 8;
17727 tmp |= fieldFromInstruction(insn, 23, 1) << 7;
17728 if (!Check(S, DecodeTAddrModeImm7<0>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
17731 tmp = fieldFromInstruction(insn, 16, 3);
17732 if (!Check(S, DecodetGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
17733 tmp = fieldFromInstruction(insn, 13, 3);
17734 if (!Check(S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
17735 tmp = fieldFromInstruction(insn, 16, 3);
17736 if (!Check(S, DecodetGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
17737 tmp = 0x0;
17738 tmp |= fieldFromInstruction(insn, 0, 7) << 0;
17739 tmp |= fieldFromInstruction(insn, 23, 1) << 7;
17740 if (!Check(S, DecodeT2Imm7<0>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
17749 tmp = fieldFromInstruction(insn, 13, 3);
17750 if (!Check(S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
17751 tmp = 0x0;
17752 tmp |= fieldFromInstruction(insn, 0, 7) << 0;
17753 tmp |= fieldFromInstruction(insn, 16, 3) << 8;
17754 tmp |= fieldFromInstruction(insn, 23, 1) << 7;
17755 if (!Check(S, DecodeTAddrModeImm7<1>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
17761 tmp = fieldFromInstruction(insn, 16, 3);
17762 if (!Check(S, DecodetGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
17763 tmp = fieldFromInstruction(insn, 13, 3);
17764 if (!Check(S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
17765 tmp = fieldFromInstruction(insn, 16, 3);
17766 if (!Check(S, DecodetGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
17767 tmp = 0x0;
17768 tmp |= fieldFromInstruction(insn, 0, 7) << 0;
17769 tmp |= fieldFromInstruction(insn, 23, 1) << 7;
17770 if (!Check(S, DecodeT2Imm7<1>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
17776 tmp = fieldFromInstruction(insn, 13, 3);
17777 if (!Check(S, DecodeQQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
17778 tmp = fieldFromInstruction(insn, 16, 4);
17779 if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
17782 tmp = fieldFromInstruction(insn, 13, 3);
17783 if (!Check(S, DecodeQQQQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
17784 tmp = fieldFromInstruction(insn, 16, 4);
17785 if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
17788 tmp = fieldFromInstruction(insn, 13, 3);
17789 if (!Check(S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
17790 tmp = 0x0;
17791 tmp |= fieldFromInstruction(insn, 0, 7) << 0;
17792 tmp |= fieldFromInstruction(insn, 16, 4) << 8;
17793 tmp |= fieldFromInstruction(insn, 23, 1) << 7;
17794 if (!Check(S, DecodeT2AddrModeImm7<0, 0>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
17797 tmp = fieldFromInstruction(insn, 13, 3);
17798 if (!Check(S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
17799 tmp = 0x0;
17800 tmp |= fieldFromInstruction(insn, 0, 7) << 0;
17801 tmp |= fieldFromInstruction(insn, 17, 3) << 8;
17802 tmp |= fieldFromInstruction(insn, 23, 1) << 7;
17803 if (!Check(S, DecodeMveAddrModeQ<2>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
17806 tmp = fieldFromInstruction(insn, 13, 3);
17807 if (!Check(S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
17808 tmp = 0x0;
17809 tmp |= fieldFromInstruction(insn, 0, 7) << 0;
17810 tmp |= fieldFromInstruction(insn, 16, 4) << 8;
17811 tmp |= fieldFromInstruction(insn, 23, 1) << 7;
17812 if (!Check(S, DecodeT2AddrModeImm7<1, 0>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
17815 tmp = fieldFromInstruction(insn, 13, 3);
17816 if (!Check(S, DecodeQQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
17817 tmp = fieldFromInstruction(insn, 13, 3);
17818 if (!Check(S, DecodeQQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
17819 tmp = fieldFromInstruction(insn, 16, 4);
17820 if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
17823 tmp = fieldFromInstruction(insn, 13, 3);
17824 if (!Check(S, DecodeQQQQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
17825 tmp = fieldFromInstruction(insn, 13, 3);
17826 if (!Check(S, DecodeQQQQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
17827 tmp = fieldFromInstruction(insn, 16, 4);
17828 if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
17831 tmp = fieldFromInstruction(insn, 16, 4);
17832 if (!Check(S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
17833 tmp = fieldFromInstruction(insn, 13, 3);
17834 if (!Check(S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
17835 tmp = fieldFromInstruction(insn, 16, 4);
17836 if (!Check(S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
17837 tmp = 0x0;
17838 tmp |= fieldFromInstruction(insn, 0, 7) << 0;
17839 tmp |= fieldFromInstruction(insn, 23, 1) << 7;
17840 if (!Check(S, DecodeT2Imm7<0>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
17843 tmp = fieldFromInstruction(insn, 16, 4);
17844 if (!Check(S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
17845 tmp = fieldFromInstruction(insn, 13, 3);
17846 if (!Check(S, DecodeQQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
17847 tmp = fieldFromInstruction(insn, 16, 4);
17848 if (!Check(S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
17851 tmp = fieldFromInstruction(insn, 16, 4);
17852 if (!Check(S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
17853 tmp = fieldFromInstruction(insn, 13, 3);
17854 if (!Check(S, DecodeQQQQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
17855 tmp = fieldFromInstruction(insn, 16, 4);
17856 if (!Check(S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
17865 tmp = fieldFromInstruction(insn, 16, 4);
17866 if (!Check(S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
17867 tmp = fieldFromInstruction(insn, 13, 3);
17868 if (!Check(S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
17869 tmp = fieldFromInstruction(insn, 16, 4);
17870 if (!Check(S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
17871 tmp = 0x0;
17872 tmp |= fieldFromInstruction(insn, 0, 7) << 0;
17873 tmp |= fieldFromInstruction(insn, 23, 1) << 7;
17874 if (!Check(S, DecodeT2Imm7<1>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
17880 tmp = fieldFromInstruction(insn, 16, 4);
17881 if (!Check(S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
17882 tmp = fieldFromInstruction(insn, 13, 3);
17883 if (!Check(S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
17884 tmp = fieldFromInstruction(insn, 16, 4);
17885 if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
17886 tmp = 0x0;
17887 tmp |= fieldFromInstruction(insn, 0, 7) << 0;
17888 tmp |= fieldFromInstruction(insn, 23, 1) << 7;
17889 if (!Check(S, DecodeT2Imm7<0>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
17892 tmp = fieldFromInstruction(insn, 13, 3);
17893 if (!Check(S, DecodeQQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
17894 tmp = fieldFromInstruction(insn, 16, 4);
17895 if (!Check(S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
17896 tmp = fieldFromInstruction(insn, 13, 3);
17897 if (!Check(S, DecodeQQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
17898 tmp = fieldFromInstruction(insn, 16, 4);
17899 if (!Check(S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
17902 tmp = fieldFromInstruction(insn, 13, 3);
17903 if (!Check(S, DecodeQQQQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
17904 tmp = fieldFromInstruction(insn, 16, 4);
17905 if (!Check(S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
17906 tmp = fieldFromInstruction(insn, 13, 3);
17907 if (!Check(S, DecodeQQQQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
17908 tmp = fieldFromInstruction(insn, 16, 4);
17909 if (!Check(S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
17912 tmp = fieldFromInstruction(insn, 16, 4);
17913 if (!Check(S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
17914 tmp = fieldFromInstruction(insn, 13, 3);
17915 if (!Check(S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
17916 tmp = fieldFromInstruction(insn, 16, 4);
17917 if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
17918 tmp = 0x0;
17919 tmp |= fieldFromInstruction(insn, 0, 7) << 0;
17920 tmp |= fieldFromInstruction(insn, 23, 1) << 7;
17921 if (!Check(S, DecodeT2Imm7<1>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
17924 tmp = fieldFromInstruction(insn, 13, 3);
17925 if (!Check(S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
17926 tmp = 0x0;
17927 tmp |= fieldFromInstruction(insn, 0, 7) << 0;
17928 tmp |= fieldFromInstruction(insn, 16, 4) << 8;
17929 tmp |= fieldFromInstruction(insn, 23, 1) << 7;
17930 if (!Check(S, DecodeT2AddrModeImm7<2, 0>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
17933 tmp = fieldFromInstruction(insn, 13, 3);
17934 if (!Check(S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
17935 tmp = 0x0;
17936 tmp |= fieldFromInstruction(insn, 0, 7) << 0;
17937 tmp |= fieldFromInstruction(insn, 17, 3) << 8;
17938 tmp |= fieldFromInstruction(insn, 23, 1) << 7;
17939 if (!Check(S, DecodeMveAddrModeQ<3>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
17942 tmp = fieldFromInstruction(insn, 16, 4);
17943 if (!Check(S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
17944 tmp = fieldFromInstruction(insn, 13, 3);
17945 if (!Check(S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
17946 tmp = fieldFromInstruction(insn, 16, 4);
17947 if (!Check(S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
17948 tmp = 0x0;
17949 tmp |= fieldFromInstruction(insn, 0, 7) << 0;
17950 tmp |= fieldFromInstruction(insn, 23, 1) << 7;
17951 if (!Check(S, DecodeT2Imm7<2>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
17960 tmp = fieldFromInstruction(insn, 16, 4);
17961 if (!Check(S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
17962 tmp = fieldFromInstruction(insn, 13, 3);
17963 if (!Check(S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
17964 tmp = fieldFromInstruction(insn, 16, 4);
17965 if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
17966 tmp = 0x0;
17967 tmp |= fieldFromInstruction(insn, 0, 7) << 0;
17968 tmp |= fieldFromInstruction(insn, 23, 1) << 7;
17969 if (!Check(S, DecodeT2Imm7<2>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
17972 tmp = 0x0;
17973 tmp |= fieldFromInstruction(insn, 7, 1) << 3;
17974 tmp |= fieldFromInstruction(insn, 17, 3) << 0;
17975 if (!Check(S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
17976 tmp = 0x0;
17977 tmp |= fieldFromInstruction(insn, 7, 1) << 3;
17978 tmp |= fieldFromInstruction(insn, 17, 3) << 0;
17979 if (!Check(S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
17980 tmp = fieldFromInstruction(insn, 12, 4);
17981 if (!Check(S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
17982 tmp = 0x0;
17983 tmp |= fieldFromInstruction(insn, 16, 1) << 1;
17984 tmp |= fieldFromInstruction(insn, 21, 1) << 0;
17985 MI.addOperand(MCOperand::createImm(tmp));
17988 tmp = 0x0;
17989 tmp |= fieldFromInstruction(insn, 7, 1) << 3;
17990 tmp |= fieldFromInstruction(insn, 17, 3) << 0;
17991 if (!Check(S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
17992 tmp = 0x0;
17993 tmp |= fieldFromInstruction(insn, 7, 1) << 3;
17994 tmp |= fieldFromInstruction(insn, 17, 3) << 0;
17995 if (!Check(S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
17996 tmp = fieldFromInstruction(insn, 12, 4);
17997 if (!Check(S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
17998 tmp = 0x0;
17999 tmp |= fieldFromInstruction(insn, 6, 1) << 0;
18000 tmp |= fieldFromInstruction(insn, 16, 1) << 2;
18001 tmp |= fieldFromInstruction(insn, 21, 1) << 1;
18002 MI.addOperand(MCOperand::createImm(tmp));
18005 tmp = 0x0;
18006 tmp |= fieldFromInstruction(insn, 7, 1) << 3;
18007 tmp |= fieldFromInstruction(insn, 17, 3) << 0;
18008 if (!Check(S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
18009 tmp = 0x0;
18010 tmp |= fieldFromInstruction(insn, 7, 1) << 3;
18011 tmp |= fieldFromInstruction(insn, 17, 3) << 0;
18012 if (!Check(S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
18013 tmp = fieldFromInstruction(insn, 12, 4);
18014 if (!Check(S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
18015 tmp = 0x0;
18016 tmp |= fieldFromInstruction(insn, 5, 2) << 0;
18017 tmp |= fieldFromInstruction(insn, 16, 1) << 3;
18018 tmp |= fieldFromInstruction(insn, 21, 1) << 2;
18019 MI.addOperand(MCOperand::createImm(tmp));
18022 tmp = fieldFromInstruction(insn, 12, 4);
18023 if (!Check(S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
18024 tmp = 0x0;
18025 tmp |= fieldFromInstruction(insn, 7, 1) << 3;
18026 tmp |= fieldFromInstruction(insn, 17, 3) << 0;
18027 if (!Check(S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
18028 tmp = 0x0;
18029 tmp |= fieldFromInstruction(insn, 16, 1) << 1;
18030 tmp |= fieldFromInstruction(insn, 21, 1) << 0;
18031 MI.addOperand(MCOperand::createImm(tmp));
18034 tmp = fieldFromInstruction(insn, 12, 4);
18035 if (!Check(S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
18036 tmp = 0x0;
18037 tmp |= fieldFromInstruction(insn, 7, 1) << 3;
18038 tmp |= fieldFromInstruction(insn, 17, 3) << 0;
18039 if (!Check(S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
18040 tmp = 0x0;
18041 tmp |= fieldFromInstruction(insn, 6, 1) << 0;
18042 tmp |= fieldFromInstruction(insn, 16, 1) << 2;
18043 tmp |= fieldFromInstruction(insn, 21, 1) << 1;
18044 MI.addOperand(MCOperand::createImm(tmp));
18047 tmp = fieldFromInstruction(insn, 12, 4);
18048 if (!Check(S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
18049 tmp = 0x0;
18050 tmp |= fieldFromInstruction(insn, 7, 1) << 3;
18051 tmp |= fieldFromInstruction(insn, 17, 3) << 0;
18052 if (!Check(S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
18053 tmp = 0x0;
18054 tmp |= fieldFromInstruction(insn, 5, 2) << 0;
18055 tmp |= fieldFromInstruction(insn, 16, 1) << 3;
18056 tmp |= fieldFromInstruction(insn, 21, 1) << 2;
18057 MI.addOperand(MCOperand::createImm(tmp));
18060 tmp = 0x0;
18061 tmp |= fieldFromInstruction(insn, 13, 3) << 0;
18062 tmp |= fieldFromInstruction(insn, 22, 1) << 3;
18063 if (!Check(S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
18064 tmp = 0x0;
18065 tmp |= fieldFromInstruction(insn, 13, 3) << 0;
18066 tmp |= fieldFromInstruction(insn, 22, 1) << 3;
18067 if (!Check(S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
18068 tmp = 0x0;
18069 tmp |= fieldFromInstruction(insn, 7, 1) << 3;
18070 tmp |= fieldFromInstruction(insn, 17, 3) << 0;
18071 if (!Check(S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
18072 tmp = 0x0;
18073 tmp |= fieldFromInstruction(insn, 1, 3) << 0;
18074 tmp |= fieldFromInstruction(insn, 5, 1) << 3;
18075 if (!Check(S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
18078 tmp = 0x0;
18079 tmp |= fieldFromInstruction(insn, 13, 3) << 0;
18080 tmp |= fieldFromInstruction(insn, 22, 1) << 3;
18081 if (!Check(S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
18082 tmp = 0x0;
18083 tmp |= fieldFromInstruction(insn, 7, 1) << 3;
18084 tmp |= fieldFromInstruction(insn, 17, 3) << 0;
18085 if (!Check(S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
18086 tmp = 0x0;
18087 tmp |= fieldFromInstruction(insn, 1, 3) << 0;
18088 tmp |= fieldFromInstruction(insn, 5, 1) << 3;
18089 if (!Check(S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
18090 tmp = 0x0;
18091 tmp |= fieldFromInstruction(insn, 13, 3) << 0;
18092 tmp |= fieldFromInstruction(insn, 22, 1) << 3;
18093 if (!Check(S, DecodeVpredROperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
18096 tmp = 0x0;
18097 tmp |= fieldFromInstruction(insn, 13, 3) << 0;
18098 tmp |= fieldFromInstruction(insn, 22, 1) << 3;
18099 if (!Check(S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
18100 tmp = 0x0;
18101 tmp |= fieldFromInstruction(insn, 13, 3) << 0;
18102 tmp |= fieldFromInstruction(insn, 22, 1) << 3;
18103 if (!Check(S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
18104 tmp = 0x0;
18105 tmp |= fieldFromInstruction(insn, 7, 1) << 3;
18106 tmp |= fieldFromInstruction(insn, 17, 3) << 0;
18107 if (!Check(S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
18108 tmp = fieldFromInstruction(insn, 0, 4);
18109 if (!Check(S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
18112 tmp = 0x0;
18113 tmp |= fieldFromInstruction(insn, 13, 3) << 0;
18114 tmp |= fieldFromInstruction(insn, 22, 1) << 3;
18115 if (!Check(S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
18116 tmp = 0x0;
18117 tmp |= fieldFromInstruction(insn, 7, 1) << 3;
18118 tmp |= fieldFromInstruction(insn, 17, 3) << 0;
18119 if (!Check(S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
18120 tmp = fieldFromInstruction(insn, 0, 4);
18121 if (!Check(S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
18122 tmp = 0x0;
18123 tmp |= fieldFromInstruction(insn, 13, 3) << 0;
18124 tmp |= fieldFromInstruction(insn, 22, 1) << 3;
18125 if (!Check(S, DecodeVpredROperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
18128 tmp = 0x0;
18129 tmp |= fieldFromInstruction(insn, 13, 3) << 0;
18130 tmp |= fieldFromInstruction(insn, 22, 1) << 3;
18131 if (!Check(S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
18132 tmp = 0x0;
18133 tmp |= fieldFromInstruction(insn, 7, 1) << 3;
18134 tmp |= fieldFromInstruction(insn, 17, 3) << 0;
18135 if (!Check(S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
18136 tmp = 0x0;
18137 tmp |= fieldFromInstruction(insn, 1, 3) << 0;
18138 tmp |= fieldFromInstruction(insn, 5, 1) << 3;
18139 if (!Check(S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
18140 tmp = 0x0;
18141 tmp |= fieldFromInstruction(insn, 0, 1) << 0;
18142 tmp |= fieldFromInstruction(insn, 12, 1) << 1;
18143 MI.addOperand(MCOperand::createImm(tmp));
18144 tmp = 0x0;
18145 tmp |= fieldFromInstruction(insn, 13, 3) << 0;
18146 tmp |= fieldFromInstruction(insn, 22, 1) << 3;
18147 if (!Check(S, DecodeVpredROperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
18150 tmp = 0x0;
18151 tmp |= fieldFromInstruction(insn, 13, 3) << 0;
18152 tmp |= fieldFromInstruction(insn, 22, 1) << 3;
18153 if (!Check(S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
18154 tmp = 0x0;
18155 tmp |= fieldFromInstruction(insn, 1, 3) << 0;
18156 tmp |= fieldFromInstruction(insn, 5, 1) << 3;
18157 if (!Check(S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
18158 tmp = 0x0;
18159 tmp |= fieldFromInstruction(insn, 13, 3) << 0;
18160 tmp |= fieldFromInstruction(insn, 22, 1) << 3;
18161 if (!Check(S, DecodeVpredROperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
18164 tmp = 0x0;
18165 tmp |= fieldFromInstruction(insn, 13, 3) << 0;
18166 tmp |= fieldFromInstruction(insn, 22, 1) << 3;
18167 if (!Check(S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
18168 tmp = 0x0;
18169 tmp |= fieldFromInstruction(insn, 13, 3) << 0;
18170 tmp |= fieldFromInstruction(insn, 22, 1) << 3;
18171 if (!Check(S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
18172 tmp = 0x0;
18173 tmp |= fieldFromInstruction(insn, 1, 3) << 0;
18174 tmp |= fieldFromInstruction(insn, 5, 1) << 3;
18175 if (!Check(S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
18178 tmp = 0x0;
18179 tmp |= fieldFromInstruction(insn, 13, 3) << 0;
18180 tmp |= fieldFromInstruction(insn, 22, 1) << 3;
18181 if (!Check(S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
18182 tmp = 0x0;
18183 tmp |= fieldFromInstruction(insn, 13, 3) << 0;
18184 tmp |= fieldFromInstruction(insn, 22, 1) << 3;
18185 if (!Check(S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
18186 tmp = fieldFromInstruction(insn, 0, 4);
18187 if (!Check(S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
18190 tmp = 0x0;
18191 tmp |= fieldFromInstruction(insn, 13, 3) << 0;
18192 tmp |= fieldFromInstruction(insn, 22, 1) << 3;
18193 if (!Check(S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
18194 tmp = 0x0;
18195 tmp |= fieldFromInstruction(insn, 7, 1) << 3;
18196 tmp |= fieldFromInstruction(insn, 17, 3) << 0;
18197 if (!Check(S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
18198 tmp = 0x0;
18199 tmp |= fieldFromInstruction(insn, 1, 3) << 0;
18200 tmp |= fieldFromInstruction(insn, 5, 1) << 3;
18201 if (!Check(S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
18202 tmp = fieldFromInstruction(insn, 12, 1);
18203 MI.addOperand(MCOperand::createImm(tmp));
18204 tmp = 0x0;
18205 tmp |= fieldFromInstruction(insn, 13, 3) << 0;
18206 tmp |= fieldFromInstruction(insn, 22, 1) << 3;
18207 if (!Check(S, DecodeVpredROperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
18213 tmp = 0x0;
18214 tmp |= fieldFromInstruction(insn, 13, 3) << 0;
18215 tmp |= fieldFromInstruction(insn, 22, 1) << 3;
18216 if (!Check(S, DecodeVPTMaskOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
18217 tmp = fieldFromInstruction(insn, 17, 3);
18218 if (!Check(S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
18219 tmp = 0x0;
18220 tmp |= fieldFromInstruction(insn, 1, 3) << 0;
18221 tmp |= fieldFromInstruction(insn, 5, 1) << 3;
18222 if (!Check(S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
18223 tmp = fieldFromInstruction(insn, 7, 1);
18224 if (!Check(S, DecodeRestrictedIPredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
18230 tmp = 0x0;
18231 tmp |= fieldFromInstruction(insn, 13, 3) << 0;
18232 tmp |= fieldFromInstruction(insn, 22, 1) << 3;
18233 if (!Check(S, DecodeVPTMaskOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
18234 tmp = fieldFromInstruction(insn, 17, 3);
18235 if (!Check(S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
18236 tmp = 0x0;
18237 tmp |= fieldFromInstruction(insn, 1, 3) << 0;
18238 tmp |= fieldFromInstruction(insn, 5, 1) << 3;
18239 if (!Check(S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
18240 tmp = fieldFromInstruction(insn, 7, 1);
18241 if (!Check(S, DecodeRestrictedUPredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
18247 tmp = 0x0;
18248 tmp |= fieldFromInstruction(insn, 13, 3) << 0;
18249 tmp |= fieldFromInstruction(insn, 22, 1) << 3;
18250 if (!Check(S, DecodeVPTMaskOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
18251 tmp = fieldFromInstruction(insn, 17, 3);
18252 if (!Check(S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
18253 tmp = 0x0;
18254 tmp |= fieldFromInstruction(insn, 1, 3) << 0;
18255 tmp |= fieldFromInstruction(insn, 5, 1) << 3;
18256 if (!Check(S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
18257 tmp = 0x0;
18258 tmp |= fieldFromInstruction(insn, 0, 1) << 1;
18259 tmp |= fieldFromInstruction(insn, 7, 1) << 0;
18260 if (!Check(S, DecodeRestrictedSPredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
18266 tmp = 0x0;
18267 tmp |= fieldFromInstruction(insn, 13, 3) << 0;
18268 tmp |= fieldFromInstruction(insn, 22, 1) << 3;
18269 if (!Check(S, DecodeVPTMaskOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
18270 tmp = fieldFromInstruction(insn, 17, 3);
18271 if (!Check(S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
18272 tmp = fieldFromInstruction(insn, 0, 4);
18273 if (!Check(S, DecodeGPRwithZRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
18274 tmp = fieldFromInstruction(insn, 7, 1);
18275 if (!Check(S, DecodeRestrictedIPredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
18278 tmp = 0x0;
18279 tmp |= fieldFromInstruction(insn, 13, 3) << 0;
18280 tmp |= fieldFromInstruction(insn, 22, 1) << 3;
18281 if (!Check(S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
18282 tmp = fieldFromInstruction(insn, 17, 3) << 1;
18283 if (!Check(S, DecodetGPREvenRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
18284 tmp = fieldFromInstruction(insn, 17, 3) << 1;
18285 if (!Check(S, DecodetGPREvenRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
18286 tmp = 0x0;
18287 tmp |= fieldFromInstruction(insn, 0, 1) << 0;
18288 tmp |= fieldFromInstruction(insn, 7, 1) << 1;
18289 if (!Check(S, DecodePowerTwoOperand<0,3>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
18290 tmp = 0x0;
18291 tmp |= fieldFromInstruction(insn, 13, 3) << 0;
18292 tmp |= fieldFromInstruction(insn, 22, 1) << 3;
18293 if (!Check(S, DecodeVpredROperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
18296 tmp = 0x0;
18297 tmp |= fieldFromInstruction(insn, 13, 3) << 0;
18298 tmp |= fieldFromInstruction(insn, 22, 1) << 3;
18299 if (!Check(S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
18300 tmp = fieldFromInstruction(insn, 17, 3) << 1;
18301 if (!Check(S, DecodetGPREvenRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
18302 tmp = fieldFromInstruction(insn, 17, 3) << 1;
18303 if (!Check(S, DecodetGPREvenRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
18304 tmp = fieldFromInstruction(insn, 1, 3) << 1;
18305 if (!Check(S, DecodetGPROddRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
18306 tmp = 0x0;
18307 tmp |= fieldFromInstruction(insn, 0, 1) << 0;
18308 tmp |= fieldFromInstruction(insn, 7, 1) << 1;
18309 if (!Check(S, DecodePowerTwoOperand<0,3>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
18310 tmp = 0x0;
18311 tmp |= fieldFromInstruction(insn, 13, 3) << 0;
18312 tmp |= fieldFromInstruction(insn, 22, 1) << 3;
18313 if (!Check(S, DecodeVpredROperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
18319 tmp = 0x0;
18320 tmp |= fieldFromInstruction(insn, 13, 3) << 0;
18321 tmp |= fieldFromInstruction(insn, 22, 1) << 3;
18322 if (!Check(S, DecodeVPTMaskOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
18323 tmp = fieldFromInstruction(insn, 17, 3);
18324 if (!Check(S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
18325 tmp = fieldFromInstruction(insn, 0, 4);
18326 if (!Check(S, DecodeGPRwithZRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
18327 tmp = fieldFromInstruction(insn, 7, 1);
18328 if (!Check(S, DecodeRestrictedUPredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
18334 tmp = 0x0;
18335 tmp |= fieldFromInstruction(insn, 13, 3) << 0;
18336 tmp |= fieldFromInstruction(insn, 22, 1) << 3;
18337 if (!Check(S, DecodeVPTMaskOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
18338 tmp = fieldFromInstruction(insn, 17, 3);
18339 if (!Check(S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
18340 tmp = fieldFromInstruction(insn, 0, 4);
18341 if (!Check(S, DecodeGPRwithZRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
18342 tmp = 0x0;
18343 tmp |= fieldFromInstruction(insn, 5, 1) << 1;
18344 tmp |= fieldFromInstruction(insn, 7, 1) << 0;
18345 if (!Check(S, DecodeRestrictedSPredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
18354 tmp = 0x0;
18355 tmp |= fieldFromInstruction(insn, 13, 3) << 0;
18356 tmp |= fieldFromInstruction(insn, 22, 1) << 3;
18357 if (!Check(S, DecodeVPTMaskOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
18358 tmp = fieldFromInstruction(insn, 17, 3);
18359 if (!Check(S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
18360 tmp = 0x0;
18361 tmp |= fieldFromInstruction(insn, 1, 3) << 0;
18362 tmp |= fieldFromInstruction(insn, 5, 1) << 3;
18363 if (!Check(S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
18364 tmp = 0x0;
18365 tmp |= fieldFromInstruction(insn, 0, 1) << 1;
18366 tmp |= fieldFromInstruction(insn, 7, 1) << 0;
18367 tmp |= fieldFromInstruction(insn, 12, 1) << 2;
18368 if (!Check(S, DecodeRestrictedFPPredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
18371 tmp = 0x0;
18372 tmp |= fieldFromInstruction(insn, 13, 3) << 0;
18373 tmp |= fieldFromInstruction(insn, 22, 1) << 3;
18374 if (!Check(S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
18375 tmp = 0x0;
18376 tmp |= fieldFromInstruction(insn, 7, 1) << 3;
18377 tmp |= fieldFromInstruction(insn, 17, 3) << 0;
18378 if (!Check(S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
18379 tmp = 0x0;
18380 tmp |= fieldFromInstruction(insn, 1, 3) << 0;
18381 tmp |= fieldFromInstruction(insn, 5, 1) << 3;
18382 if (!Check(S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
18388 tmp = 0x0;
18389 tmp |= fieldFromInstruction(insn, 13, 3) << 0;
18390 tmp |= fieldFromInstruction(insn, 22, 1) << 3;
18391 if (!Check(S, DecodeVPTMaskOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
18392 tmp = fieldFromInstruction(insn, 17, 3);
18393 if (!Check(S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
18394 tmp = fieldFromInstruction(insn, 0, 4);
18395 if (!Check(S, DecodeGPRwithZRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
18396 tmp = 0x0;
18397 tmp |= fieldFromInstruction(insn, 5, 1) << 1;
18398 tmp |= fieldFromInstruction(insn, 7, 1) << 0;
18399 tmp |= fieldFromInstruction(insn, 12, 1) << 2;
18400 if (!Check(S, DecodeRestrictedFPPredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
18406 tmp = 0x0;
18407 tmp |= fieldFromInstruction(insn, 13, 3) << 0;
18408 tmp |= fieldFromInstruction(insn, 22, 1) << 3;
18409 if (!Check(S, DecodeVPTMaskOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
18412 tmp = 0x0;
18413 tmp |= fieldFromInstruction(insn, 7, 1) << 3;
18414 tmp |= fieldFromInstruction(insn, 17, 3) << 0;
18415 if (!Check(S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
18416 tmp = fieldFromInstruction(insn, 12, 4);
18417 if (!Check(S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
18418 tmp = 0x0;
18419 tmp |= fieldFromInstruction(insn, 7, 1) << 3;
18420 tmp |= fieldFromInstruction(insn, 17, 3) << 0;
18421 if (!Check(S, DecodeVpredROperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
18424 tmp = fieldFromInstruction(insn, 13, 3) << 1;
18425 if (!Check(S, DecodetGPREvenRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
18426 tmp = fieldFromInstruction(insn, 17, 3);
18427 if (!Check(S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
18428 tmp = fieldFromInstruction(insn, 1, 3);
18429 if (!Check(S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
18432 tmp = fieldFromInstruction(insn, 13, 3) << 1;
18433 if (!Check(S, DecodetGPREvenRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
18434 tmp = fieldFromInstruction(insn, 20, 3) << 1;
18435 if (!Check(S, DecodetGPROddRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
18436 tmp = fieldFromInstruction(insn, 17, 3);
18437 if (!Check(S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
18438 tmp = fieldFromInstruction(insn, 1, 3);
18439 if (!Check(S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
18442 tmp = fieldFromInstruction(insn, 13, 3) << 1;
18443 if (!Check(S, DecodetGPREvenRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
18444 tmp = fieldFromInstruction(insn, 13, 3) << 1;
18445 if (!Check(S, DecodetGPREvenRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
18446 tmp = fieldFromInstruction(insn, 17, 3);
18447 if (!Check(S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
18448 tmp = fieldFromInstruction(insn, 1, 3);
18449 if (!Check(S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
18452 tmp = fieldFromInstruction(insn, 13, 3) << 1;
18453 if (!Check(S, DecodetGPREvenRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
18454 tmp = fieldFromInstruction(insn, 20, 3) << 1;
18455 if (!Check(S, DecodetGPROddRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
18456 tmp = fieldFromInstruction(insn, 13, 3) << 1;
18457 if (!Check(S, DecodetGPREvenRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
18458 tmp = fieldFromInstruction(insn, 20, 3) << 1;
18459 if (!Check(S, DecodetGPROddRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
18460 tmp = fieldFromInstruction(insn, 17, 3);
18461 if (!Check(S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
18462 tmp = fieldFromInstruction(insn, 1, 3);
18463 if (!Check(S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
18466 tmp = fieldFromInstruction(insn, 12, 4);
18467 if (!Check(S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
18468 tmp = fieldFromInstruction(insn, 12, 4);
18469 if (!Check(S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
18470 tmp = fieldFromInstruction(insn, 1, 3);
18471 if (!Check(S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
18474 tmp = fieldFromInstruction(insn, 13, 3) << 1;
18475 if (!Check(S, DecodetGPREvenRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
18476 tmp = fieldFromInstruction(insn, 1, 3);
18477 if (!Check(S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
18480 tmp = fieldFromInstruction(insn, 13, 3) << 1;
18481 if (!Check(S, DecodetGPREvenRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
18482 tmp = fieldFromInstruction(insn, 20, 3) << 1;
18483 if (!Check(S, DecodetGPROddRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
18484 tmp = fieldFromInstruction(insn, 1, 3);
18485 if (!Check(S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
18488 tmp = fieldFromInstruction(insn, 13, 3) << 1;
18489 if (!Check(S, DecodetGPREvenRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
18490 tmp = fieldFromInstruction(insn, 13, 3) << 1;
18491 if (!Check(S, DecodetGPREvenRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
18492 tmp = fieldFromInstruction(insn, 1, 3);
18493 if (!Check(S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
18496 tmp = fieldFromInstruction(insn, 13, 3) << 1;
18497 if (!Check(S, DecodetGPREvenRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
18498 tmp = fieldFromInstruction(insn, 20, 3) << 1;
18499 if (!Check(S, DecodetGPROddRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
18500 tmp = fieldFromInstruction(insn, 13, 3) << 1;
18501 if (!Check(S, DecodetGPREvenRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
18502 tmp = fieldFromInstruction(insn, 20, 3) << 1;
18503 if (!Check(S, DecodetGPROddRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
18504 tmp = fieldFromInstruction(insn, 1, 3);
18505 if (!Check(S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
18508 tmp = fieldFromInstruction(insn, 12, 4);
18509 if (!Check(S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
18510 tmp = fieldFromInstruction(insn, 12, 4);
18511 if (!Check(S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
18512 tmp = 0x0;
18513 tmp |= fieldFromInstruction(insn, 7, 1) << 3;
18514 tmp |= fieldFromInstruction(insn, 17, 3) << 0;
18515 if (!Check(S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
18516 tmp = 0x0;
18517 tmp |= fieldFromInstruction(insn, 1, 3) << 0;
18518 tmp |= fieldFromInstruction(insn, 5, 1) << 3;
18519 if (!Check(S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
18522 tmp = 0x0;
18523 tmp |= fieldFromInstruction(insn, 13, 3) << 0;
18524 tmp |= fieldFromInstruction(insn, 22, 1) << 3;
18525 if (!Check(S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
18526 tmp = 0x0;
18527 tmp |= fieldFromInstruction(insn, 13, 3) << 0;
18528 tmp |= fieldFromInstruction(insn, 22, 1) << 3;
18529 if (!Check(S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
18530 tmp = 0x0;
18531 tmp |= fieldFromInstruction(insn, 1, 3) << 0;
18532 tmp |= fieldFromInstruction(insn, 5, 1) << 3;
18533 if (!Check(S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
18534 tmp = fieldFromInstruction(insn, 16, 3);
18535 if (!Check(S, DecodeShiftRight8Imm(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
18538 tmp = 0x0;
18539 tmp |= fieldFromInstruction(insn, 13, 3) << 0;
18540 tmp |= fieldFromInstruction(insn, 22, 1) << 3;
18541 if (!Check(S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
18542 tmp = 0x0;
18543 tmp |= fieldFromInstruction(insn, 13, 3) << 0;
18544 tmp |= fieldFromInstruction(insn, 22, 1) << 3;
18545 if (!Check(S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
18546 tmp = 0x0;
18547 tmp |= fieldFromInstruction(insn, 1, 3) << 0;
18548 tmp |= fieldFromInstruction(insn, 5, 1) << 3;
18549 if (!Check(S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
18550 tmp = fieldFromInstruction(insn, 16, 4);
18551 if (!Check(S, DecodeShiftRight16Imm(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
18554 tmp = 0x0;
18555 tmp |= fieldFromInstruction(insn, 13, 3) << 0;
18556 tmp |= fieldFromInstruction(insn, 22, 1) << 3;
18557 if (!Check(S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
18558 tmp = 0x0;
18559 tmp |= fieldFromInstruction(insn, 1, 3) << 0;
18560 tmp |= fieldFromInstruction(insn, 5, 1) << 3;
18561 if (!Check(S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
18562 tmp = fieldFromInstruction(insn, 16, 3);
18563 MI.addOperand(MCOperand::createImm(tmp));
18564 tmp = 0x0;
18565 tmp |= fieldFromInstruction(insn, 13, 3) << 0;
18566 tmp |= fieldFromInstruction(insn, 22, 1) << 3;
18567 if (!Check(S, DecodeVpredROperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
18570 tmp = 0x0;
18571 tmp |= fieldFromInstruction(insn, 13, 3) << 0;
18572 tmp |= fieldFromInstruction(insn, 22, 1) << 3;
18573 if (!Check(S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
18574 tmp = 0x0;
18575 tmp |= fieldFromInstruction(insn, 1, 3) << 0;
18576 tmp |= fieldFromInstruction(insn, 5, 1) << 3;
18577 if (!Check(S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
18578 tmp = fieldFromInstruction(insn, 16, 4);
18579 MI.addOperand(MCOperand::createImm(tmp));
18580 tmp = 0x0;
18581 tmp |= fieldFromInstruction(insn, 13, 3) << 0;
18582 tmp |= fieldFromInstruction(insn, 22, 1) << 3;
18583 if (!Check(S, DecodeVpredROperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
18586 tmp = fieldFromInstruction(insn, 0, 4);
18587 if (!Check(S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
18588 tmp = 0x0;
18589 tmp |= fieldFromInstruction(insn, 13, 3) << 0;
18590 tmp |= fieldFromInstruction(insn, 22, 1) << 3;
18591 if (!Check(S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
18592 tmp = 0x0;
18593 tmp |= fieldFromInstruction(insn, 13, 3) << 0;
18594 tmp |= fieldFromInstruction(insn, 22, 1) << 3;
18595 if (!Check(S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
18596 tmp = fieldFromInstruction(insn, 0, 4);
18597 if (!Check(S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
18598 tmp = fieldFromInstruction(insn, 16, 5);
18599 if (!Check(S, DecodeLongShiftOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
18602 tmp = 0x0;
18603 tmp |= fieldFromInstruction(insn, 13, 3) << 0;
18604 tmp |= fieldFromInstruction(insn, 22, 1) << 3;
18605 if (!Check(S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
18606 tmp = 0x0;
18607 tmp |= fieldFromInstruction(insn, 1, 3) << 0;
18608 tmp |= fieldFromInstruction(insn, 5, 1) << 3;
18609 if (!Check(S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
18610 tmp = 0x0;
18611 tmp |= fieldFromInstruction(insn, 7, 1) << 3;
18612 tmp |= fieldFromInstruction(insn, 17, 3) << 0;
18613 if (!Check(S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
18614 tmp = 0x0;
18615 tmp |= fieldFromInstruction(insn, 13, 3) << 0;
18616 tmp |= fieldFromInstruction(insn, 22, 1) << 3;
18617 if (!Check(S, DecodeVpredROperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
18620 tmp = 0x0;
18621 tmp |= fieldFromInstruction(insn, 13, 3) << 0;
18622 tmp |= fieldFromInstruction(insn, 22, 1) << 3;
18623 if (!Check(S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
18624 tmp = 0x0;
18625 tmp |= fieldFromInstruction(insn, 13, 3) << 0;
18626 tmp |= fieldFromInstruction(insn, 22, 1) << 3;
18627 if (!Check(S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
18628 tmp = 0x0;
18629 tmp |= fieldFromInstruction(insn, 0, 4) << 0;
18630 tmp |= fieldFromInstruction(insn, 16, 3) << 4;
18631 tmp |= fieldFromInstruction(insn, 28, 1) << 7;
18632 if (!Check(S, DecodeExpandedImmOperand<0>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
18635 tmp = 0x0;
18636 tmp |= fieldFromInstruction(insn, 13, 3) << 0;
18637 tmp |= fieldFromInstruction(insn, 22, 1) << 3;
18638 if (!Check(S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
18639 tmp = 0x0;
18640 tmp |= fieldFromInstruction(insn, 13, 3) << 0;
18641 tmp |= fieldFromInstruction(insn, 22, 1) << 3;
18642 if (!Check(S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
18643 tmp = 0x0;
18644 tmp |= fieldFromInstruction(insn, 0, 4) << 0;
18645 tmp |= fieldFromInstruction(insn, 16, 3) << 4;
18646 tmp |= fieldFromInstruction(insn, 28, 1) << 7;
18647 if (!Check(S, DecodeExpandedImmOperand<8>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
18650 tmp = 0x0;
18651 tmp |= fieldFromInstruction(insn, 13, 3) << 0;
18652 tmp |= fieldFromInstruction(insn, 22, 1) << 3;
18653 if (!Check(S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
18654 tmp = 0x0;
18655 tmp |= fieldFromInstruction(insn, 13, 3) << 0;
18656 tmp |= fieldFromInstruction(insn, 22, 1) << 3;
18657 if (!Check(S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
18658 tmp = 0x0;
18659 tmp |= fieldFromInstruction(insn, 0, 4) << 0;
18660 tmp |= fieldFromInstruction(insn, 16, 3) << 4;
18661 tmp |= fieldFromInstruction(insn, 28, 1) << 7;
18662 if (!Check(S, DecodeExpandedImmOperand<16>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
18665 tmp = 0x0;
18666 tmp |= fieldFromInstruction(insn, 13, 3) << 0;
18667 tmp |= fieldFromInstruction(insn, 22, 1) << 3;
18668 if (!Check(S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
18669 tmp = 0x0;
18670 tmp |= fieldFromInstruction(insn, 13, 3) << 0;
18671 tmp |= fieldFromInstruction(insn, 22, 1) << 3;
18672 if (!Check(S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
18673 tmp = 0x0;
18674 tmp |= fieldFromInstruction(insn, 0, 4) << 0;
18675 tmp |= fieldFromInstruction(insn, 16, 3) << 4;
18676 tmp |= fieldFromInstruction(insn, 28, 1) << 7;
18677 if (!Check(S, DecodeExpandedImmOperand<24>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
18683 tmp = 0x0;
18684 tmp |= fieldFromInstruction(insn, 13, 3) << 0;
18685 tmp |= fieldFromInstruction(insn, 22, 1) << 3;
18686 if (!Check(S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
18687 tmp = 0x0;
18688 tmp |= fieldFromInstruction(insn, 1, 3) << 0;
18689 tmp |= fieldFromInstruction(insn, 5, 1) << 3;
18690 if (!Check(S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
18691 tmp = fieldFromInstruction(insn, 16, 3);
18692 if (!Check(S, DecodeShiftRight8Imm(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
18693 tmp = 0x0;
18694 tmp |= fieldFromInstruction(insn, 13, 3) << 0;
18695 tmp |= fieldFromInstruction(insn, 22, 1) << 3;
18696 if (!Check(S, DecodeVpredROperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
18699 tmp = 0x0;
18700 tmp |= fieldFromInstruction(insn, 13, 3) << 0;
18701 tmp |= fieldFromInstruction(insn, 22, 1) << 3;
18702 if (!Check(S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
18703 tmp = 0x0;
18704 tmp |= fieldFromInstruction(insn, 13, 3) << 0;
18705 tmp |= fieldFromInstruction(insn, 22, 1) << 3;
18706 if (!Check(S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
18707 tmp = 0x0;
18708 tmp |= fieldFromInstruction(insn, 1, 3) << 0;
18709 tmp |= fieldFromInstruction(insn, 5, 1) << 3;
18710 if (!Check(S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
18711 tmp = fieldFromInstruction(insn, 16, 3);
18712 MI.addOperand(MCOperand::createImm(tmp));
18715 tmp = 0x0;
18716 tmp |= fieldFromInstruction(insn, 13, 3) << 0;
18717 tmp |= fieldFromInstruction(insn, 22, 1) << 3;
18718 if (!Check(S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
18719 tmp = 0x0;
18720 tmp |= fieldFromInstruction(insn, 1, 3) << 0;
18721 tmp |= fieldFromInstruction(insn, 5, 1) << 3;
18722 if (!Check(S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
18723 tmp = fieldFromInstruction(insn, 16, 4);
18724 if (!Check(S, DecodeShiftRight16Imm(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
18725 tmp = 0x0;
18726 tmp |= fieldFromInstruction(insn, 13, 3) << 0;
18727 tmp |= fieldFromInstruction(insn, 22, 1) << 3;
18728 if (!Check(S, DecodeVpredROperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
18731 tmp = 0x0;
18732 tmp |= fieldFromInstruction(insn, 13, 3) << 0;
18733 tmp |= fieldFromInstruction(insn, 22, 1) << 3;
18734 if (!Check(S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
18735 tmp = 0x0;
18736 tmp |= fieldFromInstruction(insn, 13, 3) << 0;
18737 tmp |= fieldFromInstruction(insn, 22, 1) << 3;
18738 if (!Check(S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
18739 tmp = 0x0;
18740 tmp |= fieldFromInstruction(insn, 1, 3) << 0;
18741 tmp |= fieldFromInstruction(insn, 5, 1) << 3;
18742 if (!Check(S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
18743 tmp = fieldFromInstruction(insn, 16, 4);
18744 MI.addOperand(MCOperand::createImm(tmp));
18747 tmp = 0x0;
18748 tmp |= fieldFromInstruction(insn, 13, 3) << 0;
18749 tmp |= fieldFromInstruction(insn, 22, 1) << 3;
18750 if (!Check(S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
18751 tmp = 0x0;
18752 tmp |= fieldFromInstruction(insn, 1, 3) << 0;
18753 tmp |= fieldFromInstruction(insn, 5, 1) << 3;
18754 if (!Check(S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
18755 tmp = fieldFromInstruction(insn, 16, 5);
18756 if (!Check(S, DecodeShiftRight32Imm(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
18757 tmp = 0x0;
18758 tmp |= fieldFromInstruction(insn, 13, 3) << 0;
18759 tmp |= fieldFromInstruction(insn, 22, 1) << 3;
18760 if (!Check(S, DecodeVpredROperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
18763 tmp = 0x0;
18764 tmp |= fieldFromInstruction(insn, 13, 3) << 0;
18765 tmp |= fieldFromInstruction(insn, 22, 1) << 3;
18766 if (!Check(S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
18767 tmp = 0x0;
18768 tmp |= fieldFromInstruction(insn, 13, 3) << 0;
18769 tmp |= fieldFromInstruction(insn, 22, 1) << 3;
18770 if (!Check(S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
18771 tmp = 0x0;
18772 tmp |= fieldFromInstruction(insn, 1, 3) << 0;
18773 tmp |= fieldFromInstruction(insn, 5, 1) << 3;
18774 if (!Check(S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
18775 tmp = fieldFromInstruction(insn, 16, 5);
18776 if (!Check(S, DecodeShiftRight32Imm(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
18779 tmp = 0x0;
18780 tmp |= fieldFromInstruction(insn, 13, 3) << 0;
18781 tmp |= fieldFromInstruction(insn, 22, 1) << 3;
18782 if (!Check(S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
18783 tmp = 0x0;
18784 tmp |= fieldFromInstruction(insn, 1, 3) << 0;
18785 tmp |= fieldFromInstruction(insn, 5, 1) << 3;
18786 if (!Check(S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
18787 tmp = fieldFromInstruction(insn, 16, 5);
18788 MI.addOperand(MCOperand::createImm(tmp));
18789 tmp = 0x0;
18790 tmp |= fieldFromInstruction(insn, 13, 3) << 0;
18791 tmp |= fieldFromInstruction(insn, 22, 1) << 3;
18792 if (!Check(S, DecodeVpredROperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
18795 tmp = 0x0;
18796 tmp |= fieldFromInstruction(insn, 13, 3) << 0;
18797 tmp |= fieldFromInstruction(insn, 22, 1) << 3;
18798 if (!Check(S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
18799 tmp = 0x0;
18800 tmp |= fieldFromInstruction(insn, 13, 3) << 0;
18801 tmp |= fieldFromInstruction(insn, 22, 1) << 3;
18802 if (!Check(S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
18803 tmp = 0x0;
18804 tmp |= fieldFromInstruction(insn, 1, 3) << 0;
18805 tmp |= fieldFromInstruction(insn, 5, 1) << 3;
18806 if (!Check(S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
18807 tmp = fieldFromInstruction(insn, 16, 5);
18808 MI.addOperand(MCOperand::createImm(tmp));
18814 tmp = 0x0;
18815 tmp |= fieldFromInstruction(insn, 12, 4) << 0;
18816 tmp |= fieldFromInstruction(insn, 22, 1) << 4;
18817 if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
18818 tmp = 0x0;
18819 tmp |= fieldFromInstruction(insn, 7, 1) << 4;
18820 tmp |= fieldFromInstruction(insn, 16, 4) << 0;
18821 if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
18822 tmp = 0x0;
18823 tmp |= fieldFromInstruction(insn, 0, 4) << 0;
18824 tmp |= fieldFromInstruction(insn, 5, 1) << 4;
18825 if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
18828 tmp = 0x0;
18829 tmp |= fieldFromInstruction(insn, 12, 4) << 0;
18830 tmp |= fieldFromInstruction(insn, 22, 1) << 4;
18831 if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
18832 tmp = 0x0;
18833 tmp |= fieldFromInstruction(insn, 7, 1) << 4;
18834 tmp |= fieldFromInstruction(insn, 16, 4) << 0;
18835 if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
18836 tmp = 0x0;
18837 tmp |= fieldFromInstruction(insn, 0, 4) << 0;
18838 tmp |= fieldFromInstruction(insn, 5, 1) << 4;
18839 if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
18842 tmp = 0x0;
18843 tmp |= fieldFromInstruction(insn, 12, 4) << 0;
18844 tmp |= fieldFromInstruction(insn, 22, 1) << 4;
18845 if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
18846 tmp = 0x0;
18847 tmp |= fieldFromInstruction(insn, 7, 1) << 4;
18848 tmp |= fieldFromInstruction(insn, 16, 4) << 0;
18849 if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
18850 tmp = 0x0;
18851 tmp |= fieldFromInstruction(insn, 0, 4) << 0;
18852 tmp |= fieldFromInstruction(insn, 5, 1) << 4;
18853 if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
18856 tmp = 0x0;
18857 tmp |= fieldFromInstruction(insn, 12, 4) << 0;
18858 tmp |= fieldFromInstruction(insn, 22, 1) << 4;
18859 if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
18860 tmp = 0x0;
18861 tmp |= fieldFromInstruction(insn, 7, 1) << 4;
18862 tmp |= fieldFromInstruction(insn, 16, 4) << 0;
18863 if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
18864 tmp = 0x0;
18865 tmp |= fieldFromInstruction(insn, 0, 4) << 0;
18866 tmp |= fieldFromInstruction(insn, 5, 1) << 4;
18867 if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
18870 tmp = 0x0;
18871 tmp |= fieldFromInstruction(insn, 12, 4) << 0;
18872 tmp |= fieldFromInstruction(insn, 22, 1) << 4;
18873 if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
18874 tmp = 0x0;
18875 tmp |= fieldFromInstruction(insn, 0, 4) << 0;
18876 tmp |= fieldFromInstruction(insn, 5, 1) << 4;
18877 if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
18878 tmp = 0x0;
18879 tmp |= fieldFromInstruction(insn, 7, 1) << 4;
18880 tmp |= fieldFromInstruction(insn, 16, 4) << 0;
18881 if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
18884 tmp = 0x0;
18885 tmp |= fieldFromInstruction(insn, 12, 4) << 0;
18886 tmp |= fieldFromInstruction(insn, 22, 1) << 4;
18887 if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
18888 tmp = 0x0;
18889 tmp |= fieldFromInstruction(insn, 0, 4) << 0;
18890 tmp |= fieldFromInstruction(insn, 5, 1) << 4;
18891 if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
18892 tmp = 0x0;
18893 tmp |= fieldFromInstruction(insn, 7, 1) << 4;
18894 tmp |= fieldFromInstruction(insn, 16, 4) << 0;
18895 if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
18898 tmp = 0x0;
18899 tmp |= fieldFromInstruction(insn, 12, 4) << 0;
18900 tmp |= fieldFromInstruction(insn, 22, 1) << 4;
18901 if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
18902 tmp = 0x0;
18903 tmp |= fieldFromInstruction(insn, 7, 1) << 4;
18904 tmp |= fieldFromInstruction(insn, 16, 4) << 0;
18905 if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
18906 tmp = 0x0;
18907 tmp |= fieldFromInstruction(insn, 0, 4) << 0;
18908 tmp |= fieldFromInstruction(insn, 5, 1) << 4;
18909 if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
18912 tmp = 0x0;
18913 tmp |= fieldFromInstruction(insn, 12, 4) << 0;
18914 tmp |= fieldFromInstruction(insn, 22, 1) << 4;
18915 if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
18916 tmp = 0x0;
18917 tmp |= fieldFromInstruction(insn, 12, 4) << 0;
18918 tmp |= fieldFromInstruction(insn, 22, 1) << 4;
18919 if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
18920 tmp = 0x0;
18921 tmp |= fieldFromInstruction(insn, 7, 1) << 4;
18922 tmp |= fieldFromInstruction(insn, 16, 4) << 0;
18923 if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
18924 tmp = 0x0;
18925 tmp |= fieldFromInstruction(insn, 0, 4) << 0;
18926 tmp |= fieldFromInstruction(insn, 5, 1) << 4;
18927 if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
18930 tmp = 0x0;
18931 tmp |= fieldFromInstruction(insn, 12, 4) << 0;
18932 tmp |= fieldFromInstruction(insn, 22, 1) << 4;
18933 if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
18934 tmp = 0x0;
18935 tmp |= fieldFromInstruction(insn, 12, 4) << 0;
18936 tmp |= fieldFromInstruction(insn, 22, 1) << 4;
18937 if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
18938 tmp = 0x0;
18939 tmp |= fieldFromInstruction(insn, 7, 1) << 4;
18940 tmp |= fieldFromInstruction(insn, 16, 4) << 0;
18941 if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
18942 tmp = 0x0;
18943 tmp |= fieldFromInstruction(insn, 0, 4) << 0;
18944 tmp |= fieldFromInstruction(insn, 5, 1) << 4;
18945 if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
18948 tmp = 0x0;
18949 tmp |= fieldFromInstruction(insn, 12, 4) << 0;
18950 tmp |= fieldFromInstruction(insn, 22, 1) << 4;
18951 if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
18952 tmp = 0x0;
18953 tmp |= fieldFromInstruction(insn, 12, 4) << 0;
18954 tmp |= fieldFromInstruction(insn, 22, 1) << 4;
18955 if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
18956 tmp = 0x0;
18957 tmp |= fieldFromInstruction(insn, 7, 1) << 4;
18958 tmp |= fieldFromInstruction(insn, 16, 4) << 0;
18959 if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
18960 tmp = 0x0;
18961 tmp |= fieldFromInstruction(insn, 0, 4) << 0;
18962 tmp |= fieldFromInstruction(insn, 5, 1) << 4;
18963 if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
18966 tmp = 0x0;
18967 tmp |= fieldFromInstruction(insn, 12, 4) << 0;
18968 tmp |= fieldFromInstruction(insn, 22, 1) << 4;
18969 if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
18970 tmp = 0x0;
18971 tmp |= fieldFromInstruction(insn, 12, 4) << 0;
18972 tmp |= fieldFromInstruction(insn, 22, 1) << 4;
18973 if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
18974 tmp = 0x0;
18975 tmp |= fieldFromInstruction(insn, 7, 1) << 4;
18976 tmp |= fieldFromInstruction(insn, 16, 4) << 0;
18977 if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
18978 tmp = fieldFromInstruction(insn, 0, 3);
18979 if (!Check(S, DecodeDPR_8RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
18980 tmp = 0x0;
18981 tmp |= fieldFromInstruction(insn, 3, 1) << 0;
18982 tmp |= fieldFromInstruction(insn, 5, 1) << 1;
18983 MI.addOperand(MCOperand::createImm(tmp));
18986 tmp = 0x0;
18987 tmp |= fieldFromInstruction(insn, 12, 4) << 0;
18988 tmp |= fieldFromInstruction(insn, 22, 1) << 4;
18989 if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
18990 tmp = 0x0;
18991 tmp |= fieldFromInstruction(insn, 12, 4) << 0;
18992 tmp |= fieldFromInstruction(insn, 22, 1) << 4;
18993 if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
18994 tmp = 0x0;
18995 tmp |= fieldFromInstruction(insn, 7, 1) << 4;
18996 tmp |= fieldFromInstruction(insn, 16, 4) << 0;
18997 if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
18998 tmp = fieldFromInstruction(insn, 0, 3);
18999 if (!Check(S, DecodeDPR_8RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
19000 tmp = 0x0;
19001 tmp |= fieldFromInstruction(insn, 3, 1) << 0;
19002 tmp |= fieldFromInstruction(insn, 5, 1) << 1;
19003 MI.addOperand(MCOperand::createImm(tmp));
19006 tmp = 0x0;
19007 tmp |= fieldFromInstruction(insn, 12, 4) << 0;
19008 tmp |= fieldFromInstruction(insn, 22, 1) << 4;
19009 if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
19010 tmp = 0x0;
19011 tmp |= fieldFromInstruction(insn, 12, 4) << 0;
19012 tmp |= fieldFromInstruction(insn, 22, 1) << 4;
19013 if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
19014 tmp = 0x0;
19015 tmp |= fieldFromInstruction(insn, 7, 1) << 4;
19016 tmp |= fieldFromInstruction(insn, 16, 4) << 0;
19017 if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
19018 tmp = fieldFromInstruction(insn, 0, 3);
19019 if (!Check(S, DecodeDPR_8RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
19020 tmp = 0x0;
19021 tmp |= fieldFromInstruction(insn, 3, 1) << 0;
19022 tmp |= fieldFromInstruction(insn, 5, 1) << 1;
19023 MI.addOperand(MCOperand::createImm(tmp));
19026 tmp = 0x0;
19027 tmp |= fieldFromInstruction(insn, 12, 4) << 0;
19028 tmp |= fieldFromInstruction(insn, 22, 1) << 4;
19029 if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
19030 tmp = 0x0;
19031 tmp |= fieldFromInstruction(insn, 7, 1) << 4;
19032 tmp |= fieldFromInstruction(insn, 16, 4) << 0;
19033 if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
19034 tmp = fieldFromInstruction(insn, 0, 3);
19035 if (!Check(S, DecodeDPR_8RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
19036 tmp = 0x0;
19037 tmp |= fieldFromInstruction(insn, 3, 1) << 0;
19038 tmp |= fieldFromInstruction(insn, 5, 1) << 1;
19039 MI.addOperand(MCOperand::createImm(tmp));
19042 tmp = 0x0;
19043 tmp |= fieldFromInstruction(insn, 12, 4) << 0;
19044 tmp |= fieldFromInstruction(insn, 22, 1) << 4;
19045 if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
19046 tmp = 0x0;
19047 tmp |= fieldFromInstruction(insn, 7, 1) << 4;
19048 tmp |= fieldFromInstruction(insn, 16, 4) << 0;
19049 if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
19050 tmp = fieldFromInstruction(insn, 0, 3);
19051 if (!Check(S, DecodeDPR_8RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
19052 tmp = 0x0;
19053 tmp |= fieldFromInstruction(insn, 3, 1) << 0;
19054 tmp |= fieldFromInstruction(insn, 5, 1) << 1;
19055 MI.addOperand(MCOperand::createImm(tmp));
19058 tmp = 0x0;
19059 tmp |= fieldFromInstruction(insn, 12, 4) << 0;
19060 tmp |= fieldFromInstruction(insn, 22, 1) << 4;
19061 if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
19062 tmp = 0x0;
19063 tmp |= fieldFromInstruction(insn, 7, 1) << 4;
19064 tmp |= fieldFromInstruction(insn, 16, 4) << 0;
19065 if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
19066 tmp = fieldFromInstruction(insn, 0, 3);
19067 if (!Check(S, DecodeDPR_8RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
19068 tmp = 0x0;
19069 tmp |= fieldFromInstruction(insn, 3, 1) << 0;
19070 tmp |= fieldFromInstruction(insn, 5, 1) << 1;
19071 MI.addOperand(MCOperand::createImm(tmp));
19074 tmp = 0x0;
19075 tmp |= fieldFromInstruction(insn, 12, 4) << 0;
19076 tmp |= fieldFromInstruction(insn, 22, 1) << 4;
19077 if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
19078 tmp = 0x0;
19079 tmp |= fieldFromInstruction(insn, 12, 4) << 0;
19080 tmp |= fieldFromInstruction(insn, 22, 1) << 4;
19081 if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
19082 tmp = 0x0;
19083 tmp |= fieldFromInstruction(insn, 7, 1) << 4;
19084 tmp |= fieldFromInstruction(insn, 16, 4) << 0;
19085 if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
19086 tmp = fieldFromInstruction(insn, 0, 4);
19087 if (!Check(S, DecodeDPR_VFP2RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
19088 tmp = fieldFromInstruction(insn, 5, 1);
19089 MI.addOperand(MCOperand::createImm(tmp));
19092 tmp = 0x0;
19093 tmp |= fieldFromInstruction(insn, 12, 4) << 0;
19094 tmp |= fieldFromInstruction(insn, 22, 1) << 4;
19095 if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
19096 tmp = 0x0;
19097 tmp |= fieldFromInstruction(insn, 12, 4) << 0;
19098 tmp |= fieldFromInstruction(insn, 22, 1) << 4;
19099 if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
19100 tmp = 0x0;
19101 tmp |= fieldFromInstruction(insn, 7, 1) << 4;
19102 tmp |= fieldFromInstruction(insn, 16, 4) << 0;
19103 if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
19104 tmp = fieldFromInstruction(insn, 0, 4);
19105 if (!Check(S, DecodeDPR_VFP2RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
19106 tmp = fieldFromInstruction(insn, 5, 1);
19107 MI.addOperand(MCOperand::createImm(tmp));
19110 tmp = 0x0;
19111 tmp |= fieldFromInstruction(insn, 12, 4) << 0;
19112 tmp |= fieldFromInstruction(insn, 22, 1) << 4;
19113 if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
19114 tmp = 0x0;
19115 tmp |= fieldFromInstruction(insn, 12, 4) << 0;
19116 tmp |= fieldFromInstruction(insn, 22, 1) << 4;
19117 if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
19118 tmp = 0x0;
19119 tmp |= fieldFromInstruction(insn, 7, 1) << 4;
19120 tmp |= fieldFromInstruction(insn, 16, 4) << 0;
19121 if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
19122 tmp = fieldFromInstruction(insn, 0, 4);
19123 if (!Check(S, DecodeDPR_VFP2RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
19124 tmp = fieldFromInstruction(insn, 5, 1);
19125 MI.addOperand(MCOperand::createImm(tmp));
19128 tmp = 0x0;
19129 tmp |= fieldFromInstruction(insn, 12, 4) << 0;
19130 tmp |= fieldFromInstruction(insn, 22, 1) << 4;
19131 if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
19132 tmp = 0x0;
19133 tmp |= fieldFromInstruction(insn, 7, 1) << 4;
19134 tmp |= fieldFromInstruction(insn, 16, 4) << 0;
19135 if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
19136 tmp = fieldFromInstruction(insn, 0, 4);
19137 if (!Check(S, DecodeDPR_VFP2RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
19138 tmp = fieldFromInstruction(insn, 5, 1);
19139 MI.addOperand(MCOperand::createImm(tmp));
19142 tmp = 0x0;
19143 tmp |= fieldFromInstruction(insn, 12, 4) << 0;
19144 tmp |= fieldFromInstruction(insn, 22, 1) << 4;
19145 if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
19146 tmp = 0x0;
19147 tmp |= fieldFromInstruction(insn, 7, 1) << 4;
19148 tmp |= fieldFromInstruction(insn, 16, 4) << 0;
19149 if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
19150 tmp = fieldFromInstruction(insn, 0, 4);
19151 if (!Check(S, DecodeDPR_VFP2RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
19152 tmp = fieldFromInstruction(insn, 5, 1);
19153 MI.addOperand(MCOperand::createImm(tmp));
19156 tmp = 0x0;
19157 tmp |= fieldFromInstruction(insn, 12, 4) << 0;
19158 tmp |= fieldFromInstruction(insn, 22, 1) << 4;
19159 if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
19160 tmp = 0x0;
19161 tmp |= fieldFromInstruction(insn, 7, 1) << 4;
19162 tmp |= fieldFromInstruction(insn, 16, 4) << 0;
19163 if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
19164 tmp = fieldFromInstruction(insn, 0, 4);
19165 if (!Check(S, DecodeDPR_VFP2RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
19166 tmp = fieldFromInstruction(insn, 5, 1);
19167 MI.addOperand(MCOperand::createImm(tmp));
19170 tmp = 0x0;
19171 tmp |= fieldFromInstruction(insn, 12, 4) << 0;
19172 tmp |= fieldFromInstruction(insn, 22, 1) << 4;
19173 if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
19174 tmp = 0x0;
19175 tmp |= fieldFromInstruction(insn, 7, 1) << 4;
19176 tmp |= fieldFromInstruction(insn, 16, 4) << 0;
19177 if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
19178 tmp = 0x0;
19179 tmp |= fieldFromInstruction(insn, 0, 4) << 0;
19180 tmp |= fieldFromInstruction(insn, 5, 1) << 4;
19181 if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
19182 tmp = fieldFromInstruction(insn, 10, 1);
19183 MI.addOperand(MCOperand::createImm(tmp));
19186 tmp = 0x0;
19187 tmp |= fieldFromInstruction(insn, 12, 4) << 0;
19188 tmp |= fieldFromInstruction(insn, 22, 1) << 4;
19189 if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
19190 tmp = 0x0;
19191 tmp |= fieldFromInstruction(insn, 7, 1) << 4;
19192 tmp |= fieldFromInstruction(insn, 16, 4) << 0;
19193 if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
19194 tmp = 0x0;
19195 tmp |= fieldFromInstruction(insn, 0, 4) << 0;
19196 tmp |= fieldFromInstruction(insn, 5, 1) << 4;
19197 if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
19198 tmp = fieldFromInstruction(insn, 9, 2);
19199 MI.addOperand(MCOperand::createImm(tmp));
19202 tmp = 0x0;
19203 tmp |= fieldFromInstruction(insn, 12, 4) << 0;
19204 tmp |= fieldFromInstruction(insn, 22, 1) << 4;
19205 if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
19206 tmp = 0x0;
19207 tmp |= fieldFromInstruction(insn, 7, 1) << 4;
19208 tmp |= fieldFromInstruction(insn, 16, 4) << 0;
19209 if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
19210 tmp = 0x0;
19211 tmp |= fieldFromInstruction(insn, 0, 4) << 0;
19212 tmp |= fieldFromInstruction(insn, 5, 1) << 4;
19213 if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
19214 tmp = fieldFromInstruction(insn, 8, 3);
19215 MI.addOperand(MCOperand::createImm(tmp));
19218 tmp = 0x0;
19219 tmp |= fieldFromInstruction(insn, 12, 4) << 0;
19220 tmp |= fieldFromInstruction(insn, 22, 1) << 4;
19221 if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
19222 tmp = 0x0;
19223 tmp |= fieldFromInstruction(insn, 7, 1) << 4;
19224 tmp |= fieldFromInstruction(insn, 16, 4) << 0;
19225 if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
19226 tmp = 0x0;
19227 tmp |= fieldFromInstruction(insn, 0, 4) << 0;
19228 tmp |= fieldFromInstruction(insn, 5, 1) << 4;
19229 if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
19230 tmp = fieldFromInstruction(insn, 11, 1);
19231 MI.addOperand(MCOperand::createImm(tmp));
19234 tmp = 0x0;
19235 tmp |= fieldFromInstruction(insn, 12, 4) << 0;
19236 tmp |= fieldFromInstruction(insn, 22, 1) << 4;
19237 if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
19238 tmp = 0x0;
19239 tmp |= fieldFromInstruction(insn, 7, 1) << 4;
19240 tmp |= fieldFromInstruction(insn, 16, 4) << 0;
19241 if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
19242 tmp = 0x0;
19243 tmp |= fieldFromInstruction(insn, 0, 4) << 0;
19244 tmp |= fieldFromInstruction(insn, 5, 1) << 4;
19245 if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
19246 tmp = fieldFromInstruction(insn, 10, 2);
19247 MI.addOperand(MCOperand::createImm(tmp));
19250 tmp = 0x0;
19251 tmp |= fieldFromInstruction(insn, 12, 4) << 0;
19252 tmp |= fieldFromInstruction(insn, 22, 1) << 4;
19253 if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
19254 tmp = 0x0;
19255 tmp |= fieldFromInstruction(insn, 7, 1) << 4;
19256 tmp |= fieldFromInstruction(insn, 16, 4) << 0;
19257 if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
19258 tmp = 0x0;
19259 tmp |= fieldFromInstruction(insn, 0, 4) << 0;
19260 tmp |= fieldFromInstruction(insn, 5, 1) << 4;
19261 if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
19262 tmp = fieldFromInstruction(insn, 9, 3);
19263 MI.addOperand(MCOperand::createImm(tmp));
19266 tmp = 0x0;
19267 tmp |= fieldFromInstruction(insn, 12, 4) << 0;
19268 tmp |= fieldFromInstruction(insn, 22, 1) << 4;
19269 if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
19270 tmp = 0x0;
19271 tmp |= fieldFromInstruction(insn, 7, 1) << 4;
19272 tmp |= fieldFromInstruction(insn, 16, 4) << 0;
19273 if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
19274 tmp = 0x0;
19275 tmp |= fieldFromInstruction(insn, 0, 4) << 0;
19276 tmp |= fieldFromInstruction(insn, 5, 1) << 4;
19277 if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
19278 tmp = fieldFromInstruction(insn, 8, 4);
19279 MI.addOperand(MCOperand::createImm(tmp));
19282 tmp = 0x0;
19283 tmp |= fieldFromInstruction(insn, 12, 4) << 0;
19284 tmp |= fieldFromInstruction(insn, 22, 1) << 4;
19285 if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
19286 tmp = 0x0;
19287 tmp |= fieldFromInstruction(insn, 0, 4) << 0;
19288 tmp |= fieldFromInstruction(insn, 5, 1) << 4;
19289 if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
19292 tmp = 0x0;
19293 tmp |= fieldFromInstruction(insn, 12, 4) << 0;
19294 tmp |= fieldFromInstruction(insn, 22, 1) << 4;
19295 if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
19296 tmp = 0x0;
19297 tmp |= fieldFromInstruction(insn, 0, 4) << 0;
19298 tmp |= fieldFromInstruction(insn, 5, 1) << 4;
19299 if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
19302 tmp = 0x0;
19303 tmp |= fieldFromInstruction(insn, 12, 4) << 0;
19304 tmp |= fieldFromInstruction(insn, 22, 1) << 4;
19305 if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
19306 tmp = 0x0;
19307 tmp |= fieldFromInstruction(insn, 0, 4) << 0;
19308 tmp |= fieldFromInstruction(insn, 5, 1) << 4;
19309 if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
19310 tmp = 0x0;
19311 tmp |= fieldFromInstruction(insn, 12, 4) << 0;
19312 tmp |= fieldFromInstruction(insn, 22, 1) << 4;
19313 if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
19314 tmp = 0x0;
19315 tmp |= fieldFromInstruction(insn, 0, 4) << 0;
19316 tmp |= fieldFromInstruction(insn, 5, 1) << 4;
19317 if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
19320 tmp = 0x0;
19321 tmp |= fieldFromInstruction(insn, 12, 4) << 0;
19322 tmp |= fieldFromInstruction(insn, 22, 1) << 4;
19323 if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
19324 tmp = 0x0;
19325 tmp |= fieldFromInstruction(insn, 0, 4) << 0;
19326 tmp |= fieldFromInstruction(insn, 5, 1) << 4;
19327 if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
19328 tmp = 0x0;
19329 tmp |= fieldFromInstruction(insn, 12, 4) << 0;
19330 tmp |= fieldFromInstruction(insn, 22, 1) << 4;
19331 if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
19332 tmp = 0x0;
19333 tmp |= fieldFromInstruction(insn, 0, 4) << 0;
19334 tmp |= fieldFromInstruction(insn, 5, 1) << 4;
19335 if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
19338 tmp = 0x0;
19339 tmp |= fieldFromInstruction(insn, 12, 4) << 0;
19340 tmp |= fieldFromInstruction(insn, 22, 1) << 4;
19341 if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
19342 tmp = 0x0;
19343 tmp |= fieldFromInstruction(insn, 0, 4) << 0;
19344 tmp |= fieldFromInstruction(insn, 5, 1) << 4;
19345 if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
19351 tmp = 0x0;
19352 tmp |= fieldFromInstruction(insn, 12, 4) << 0;
19353 tmp |= fieldFromInstruction(insn, 22, 1) << 4;
19354 if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
19355 tmp = 0x0;
19356 tmp |= fieldFromInstruction(insn, 12, 4) << 0;
19357 tmp |= fieldFromInstruction(insn, 22, 1) << 4;
19358 if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
19359 tmp = 0x0;
19360 tmp |= fieldFromInstruction(insn, 0, 4) << 0;
19361 tmp |= fieldFromInstruction(insn, 5, 1) << 4;
19362 if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
19365 tmp = 0x0;
19366 tmp |= fieldFromInstruction(insn, 12, 4) << 0;
19367 tmp |= fieldFromInstruction(insn, 22, 1) << 4;
19368 if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
19369 tmp = 0x0;
19370 tmp |= fieldFromInstruction(insn, 12, 4) << 0;
19371 tmp |= fieldFromInstruction(insn, 22, 1) << 4;
19372 if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
19373 tmp = 0x0;
19374 tmp |= fieldFromInstruction(insn, 0, 4) << 0;
19375 tmp |= fieldFromInstruction(insn, 5, 1) << 4;
19376 if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
19379 tmp = 0x0;
19380 tmp |= fieldFromInstruction(insn, 12, 4) << 0;
19381 tmp |= fieldFromInstruction(insn, 22, 1) << 4;
19382 if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
19383 tmp = 0x0;
19384 tmp |= fieldFromInstruction(insn, 0, 4) << 0;
19385 tmp |= fieldFromInstruction(insn, 5, 1) << 4;
19386 if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
19392 tmp = 0x0;
19393 tmp |= fieldFromInstruction(insn, 12, 4) << 0;
19394 tmp |= fieldFromInstruction(insn, 22, 1) << 4;
19395 if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
19396 tmp = 0x0;
19397 tmp |= fieldFromInstruction(insn, 0, 4) << 0;
19398 tmp |= fieldFromInstruction(insn, 5, 1) << 4;
19399 if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
19400 tmp = fieldFromInstruction(insn, 19, 1);
19401 MI.addOperand(MCOperand::createImm(tmp));
19404 tmp = 0x0;
19405 tmp |= fieldFromInstruction(insn, 12, 4) << 0;
19406 tmp |= fieldFromInstruction(insn, 22, 1) << 4;
19407 if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
19408 tmp = 0x0;
19409 tmp |= fieldFromInstruction(insn, 0, 4) << 0;
19410 tmp |= fieldFromInstruction(insn, 5, 1) << 4;
19411 if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
19412 tmp = fieldFromInstruction(insn, 18, 2);
19413 MI.addOperand(MCOperand::createImm(tmp));
19416 tmp = 0x0;
19417 tmp |= fieldFromInstruction(insn, 12, 4) << 0;
19418 tmp |= fieldFromInstruction(insn, 22, 1) << 4;
19419 if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
19420 tmp = 0x0;
19421 tmp |= fieldFromInstruction(insn, 0, 4) << 0;
19422 tmp |= fieldFromInstruction(insn, 5, 1) << 4;
19423 if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
19424 tmp = fieldFromInstruction(insn, 17, 3);
19425 MI.addOperand(MCOperand::createImm(tmp));
19428 tmp = 0x0;
19429 tmp |= fieldFromInstruction(insn, 12, 4) << 0;
19430 tmp |= fieldFromInstruction(insn, 22, 1) << 4;
19431 if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
19432 tmp = 0x0;
19433 tmp |= fieldFromInstruction(insn, 0, 4) << 0;
19434 tmp |= fieldFromInstruction(insn, 5, 1) << 4;
19435 if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
19436 tmp = fieldFromInstruction(insn, 19, 1);
19437 MI.addOperand(MCOperand::createImm(tmp));
19440 tmp = 0x0;
19441 tmp |= fieldFromInstruction(insn, 12, 4) << 0;
19442 tmp |= fieldFromInstruction(insn, 22, 1) << 4;
19443 if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
19444 tmp = 0x0;
19445 tmp |= fieldFromInstruction(insn, 0, 4) << 0;
19446 tmp |= fieldFromInstruction(insn, 5, 1) << 4;
19447 if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
19448 tmp = fieldFromInstruction(insn, 18, 2);
19449 MI.addOperand(MCOperand::createImm(tmp));
19452 tmp = 0x0;
19453 tmp |= fieldFromInstruction(insn, 12, 4) << 0;
19454 tmp |= fieldFromInstruction(insn, 22, 1) << 4;
19455 if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
19456 tmp = 0x0;
19457 tmp |= fieldFromInstruction(insn, 0, 4) << 0;
19458 tmp |= fieldFromInstruction(insn, 5, 1) << 4;
19459 if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
19460 tmp = fieldFromInstruction(insn, 17, 3);
19461 MI.addOperand(MCOperand::createImm(tmp));
19464 tmp = 0x0;
19465 tmp |= fieldFromInstruction(insn, 12, 4) << 0;
19466 tmp |= fieldFromInstruction(insn, 22, 1) << 4;
19467 if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
19468 tmp = 0x0;
19469 tmp |= fieldFromInstruction(insn, 0, 4) << 0;
19470 tmp |= fieldFromInstruction(insn, 5, 1) << 4;
19471 if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
19472 tmp = fieldFromInstruction(insn, 16, 3);
19473 if (!Check(S, DecodeShiftRight8Imm(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
19476 tmp = 0x0;
19477 tmp |= fieldFromInstruction(insn, 12, 4) << 0;
19478 tmp |= fieldFromInstruction(insn, 22, 1) << 4;
19479 if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
19480 tmp = 0x0;
19481 tmp |= fieldFromInstruction(insn, 0, 4) << 0;
19482 tmp |= fieldFromInstruction(insn, 5, 1) << 4;
19483 if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
19484 tmp = fieldFromInstruction(insn, 16, 4);
19485 if (!Check(S, DecodeShiftRight16Imm(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
19488 tmp = 0x0;
19489 tmp |= fieldFromInstruction(insn, 12, 4) << 0;
19490 tmp |= fieldFromInstruction(insn, 22, 1) << 4;
19491 if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
19492 tmp = 0x0;
19493 tmp |= fieldFromInstruction(insn, 0, 4) << 0;
19494 tmp |= fieldFromInstruction(insn, 5, 1) << 4;
19495 if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
19496 tmp = fieldFromInstruction(insn, 16, 5);
19497 if (!Check(S, DecodeShiftRight32Imm(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
19500 tmp = 0x0;
19501 tmp |= fieldFromInstruction(insn, 12, 4) << 0;
19502 tmp |= fieldFromInstruction(insn, 22, 1) << 4;
19503 if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
19504 tmp = 0x0;
19505 tmp |= fieldFromInstruction(insn, 12, 4) << 0;
19506 tmp |= fieldFromInstruction(insn, 22, 1) << 4;
19507 if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
19508 tmp = 0x0;
19509 tmp |= fieldFromInstruction(insn, 0, 4) << 0;
19510 tmp |= fieldFromInstruction(insn, 5, 1) << 4;
19511 if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
19512 tmp = fieldFromInstruction(insn, 16, 3);
19513 if (!Check(S, DecodeShiftRight8Imm(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
19516 tmp = 0x0;
19517 tmp |= fieldFromInstruction(insn, 12, 4) << 0;
19518 tmp |= fieldFromInstruction(insn, 22, 1) << 4;
19519 if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
19520 tmp = 0x0;
19521 tmp |= fieldFromInstruction(insn, 12, 4) << 0;
19522 tmp |= fieldFromInstruction(insn, 22, 1) << 4;
19523 if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
19524 tmp = 0x0;
19525 tmp |= fieldFromInstruction(insn, 0, 4) << 0;
19526 tmp |= fieldFromInstruction(insn, 5, 1) << 4;
19527 if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
19528 tmp = fieldFromInstruction(insn, 16, 4);
19529 if (!Check(S, DecodeShiftRight16Imm(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
19532 tmp = 0x0;
19533 tmp |= fieldFromInstruction(insn, 12, 4) << 0;
19534 tmp |= fieldFromInstruction(insn, 22, 1) << 4;
19535 if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
19536 tmp = 0x0;
19537 tmp |= fieldFromInstruction(insn, 12, 4) << 0;
19538 tmp |= fieldFromInstruction(insn, 22, 1) << 4;
19539 if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
19540 tmp = 0x0;
19541 tmp |= fieldFromInstruction(insn, 0, 4) << 0;
19542 tmp |= fieldFromInstruction(insn, 5, 1) << 4;
19543 if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
19544 tmp = fieldFromInstruction(insn, 16, 5);
19545 if (!Check(S, DecodeShiftRight32Imm(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
19548 tmp = 0x0;
19549 tmp |= fieldFromInstruction(insn, 12, 4) << 0;
19550 tmp |= fieldFromInstruction(insn, 22, 1) << 4;
19551 if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
19552 tmp = 0x0;
19553 tmp |= fieldFromInstruction(insn, 0, 4) << 0;
19554 tmp |= fieldFromInstruction(insn, 5, 1) << 4;
19555 if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
19556 tmp = fieldFromInstruction(insn, 16, 3);
19557 MI.addOperand(MCOperand::createImm(tmp));
19560 tmp = 0x0;
19561 tmp |= fieldFromInstruction(insn, 12, 4) << 0;
19562 tmp |= fieldFromInstruction(insn, 22, 1) << 4;
19563 if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
19564 tmp = 0x0;
19565 tmp |= fieldFromInstruction(insn, 12, 4) << 0;
19566 tmp |= fieldFromInstruction(insn, 22, 1) << 4;
19567 if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
19568 tmp = 0x0;
19569 tmp |= fieldFromInstruction(insn, 0, 4) << 0;
19570 tmp |= fieldFromInstruction(insn, 5, 1) << 4;
19571 if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
19572 tmp = fieldFromInstruction(insn, 16, 3);
19573 MI.addOperand(MCOperand::createImm(tmp));
19576 tmp = 0x0;
19577 tmp |= fieldFromInstruction(insn, 12, 4) << 0;
19578 tmp |= fieldFromInstruction(insn, 22, 1) << 4;
19579 if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
19580 tmp = 0x0;
19581 tmp |= fieldFromInstruction(insn, 0, 4) << 0;
19582 tmp |= fieldFromInstruction(insn, 5, 1) << 4;
19583 if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
19584 tmp = fieldFromInstruction(insn, 16, 4);
19585 MI.addOperand(MCOperand::createImm(tmp));
19588 tmp = 0x0;
19589 tmp |= fieldFromInstruction(insn, 12, 4) << 0;
19590 tmp |= fieldFromInstruction(insn, 22, 1) << 4;
19591 if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
19592 tmp = 0x0;
19593 tmp |= fieldFromInstruction(insn, 12, 4) << 0;
19594 tmp |= fieldFromInstruction(insn, 22, 1) << 4;
19595 if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
19596 tmp = 0x0;
19597 tmp |= fieldFromInstruction(insn, 0, 4) << 0;
19598 tmp |= fieldFromInstruction(insn, 5, 1) << 4;
19599 if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
19600 tmp = fieldFromInstruction(insn, 16, 4);
19601 MI.addOperand(MCOperand::createImm(tmp));
19604 tmp = 0x0;
19605 tmp |= fieldFromInstruction(insn, 12, 4) << 0;
19606 tmp |= fieldFromInstruction(insn, 22, 1) << 4;
19607 if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
19608 tmp = 0x0;
19609 tmp |= fieldFromInstruction(insn, 0, 4) << 0;
19610 tmp |= fieldFromInstruction(insn, 5, 1) << 4;
19611 if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
19612 tmp = fieldFromInstruction(insn, 16, 5);
19613 MI.addOperand(MCOperand::createImm(tmp));
19616 tmp = 0x0;
19617 tmp |= fieldFromInstruction(insn, 12, 4) << 0;
19618 tmp |= fieldFromInstruction(insn, 22, 1) << 4;
19619 if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
19620 tmp = 0x0;
19621 tmp |= fieldFromInstruction(insn, 12, 4) << 0;
19622 tmp |= fieldFromInstruction(insn, 22, 1) << 4;
19623 if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
19624 tmp = 0x0;
19625 tmp |= fieldFromInstruction(insn, 0, 4) << 0;
19626 tmp |= fieldFromInstruction(insn, 5, 1) << 4;
19627 if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
19628 tmp = fieldFromInstruction(insn, 16, 5);
19629 MI.addOperand(MCOperand::createImm(tmp));
19632 tmp = 0x0;
19633 tmp |= fieldFromInstruction(insn, 12, 4) << 0;
19634 tmp |= fieldFromInstruction(insn, 22, 1) << 4;
19635 if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
19636 tmp = 0x0;
19637 tmp |= fieldFromInstruction(insn, 0, 4) << 0;
19638 tmp |= fieldFromInstruction(insn, 5, 1) << 4;
19639 if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
19640 tmp = fieldFromInstruction(insn, 16, 3);
19641 if (!Check(S, DecodeShiftRight8Imm(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
19644 tmp = 0x0;
19645 tmp |= fieldFromInstruction(insn, 12, 4) << 0;
19646 tmp |= fieldFromInstruction(insn, 22, 1) << 4;
19647 if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
19648 tmp = 0x0;
19649 tmp |= fieldFromInstruction(insn, 0, 4) << 0;
19650 tmp |= fieldFromInstruction(insn, 5, 1) << 4;
19651 if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
19652 tmp = fieldFromInstruction(insn, 16, 4);
19653 if (!Check(S, DecodeShiftRight16Imm(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
19656 tmp = 0x0;
19657 tmp |= fieldFromInstruction(insn, 12, 4) << 0;
19658 tmp |= fieldFromInstruction(insn, 22, 1) << 4;
19659 if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
19660 tmp = 0x0;
19661 tmp |= fieldFromInstruction(insn, 0, 4) << 0;
19662 tmp |= fieldFromInstruction(insn, 5, 1) << 4;
19663 if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
19664 tmp = fieldFromInstruction(insn, 16, 5);
19665 if (!Check(S, DecodeShiftRight32Imm(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
19668 tmp = 0x0;
19669 tmp |= fieldFromInstruction(insn, 12, 4) << 0;
19670 tmp |= fieldFromInstruction(insn, 22, 1) << 4;
19671 if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
19672 tmp = 0x0;
19673 tmp |= fieldFromInstruction(insn, 0, 4) << 0;
19674 tmp |= fieldFromInstruction(insn, 5, 1) << 4;
19675 if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
19676 tmp = fieldFromInstruction(insn, 16, 3);
19677 MI.addOperand(MCOperand::createImm(tmp));
19680 tmp = 0x0;
19681 tmp |= fieldFromInstruction(insn, 12, 4) << 0;
19682 tmp |= fieldFromInstruction(insn, 22, 1) << 4;
19683 if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
19684 tmp = 0x0;
19685 tmp |= fieldFromInstruction(insn, 0, 4) << 0;
19686 tmp |= fieldFromInstruction(insn, 5, 1) << 4;
19687 if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
19688 tmp = fieldFromInstruction(insn, 16, 4);
19689 MI.addOperand(MCOperand::createImm(tmp));
19692 tmp = 0x0;
19693 tmp |= fieldFromInstruction(insn, 12, 4) << 0;
19694 tmp |= fieldFromInstruction(insn, 22, 1) << 4;
19695 if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
19696 tmp = 0x0;
19697 tmp |= fieldFromInstruction(insn, 0, 4) << 0;
19698 tmp |= fieldFromInstruction(insn, 5, 1) << 4;
19699 if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
19700 tmp = fieldFromInstruction(insn, 16, 5);
19701 MI.addOperand(MCOperand::createImm(tmp));
19710 tmp = 0x0;
19711 tmp |= fieldFromInstruction(insn, 12, 4) << 0;
19712 tmp |= fieldFromInstruction(insn, 22, 1) << 4;
19713 if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
19714 tmp = 0x0;
19715 tmp |= fieldFromInstruction(insn, 0, 4) << 0;
19716 tmp |= fieldFromInstruction(insn, 5, 1) << 4;
19717 if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
19718 tmp = fieldFromInstruction(insn, 16, 6);
19719 if (!Check(S, DecodeShiftRight64Imm(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
19722 tmp = 0x0;
19723 tmp |= fieldFromInstruction(insn, 12, 4) << 0;
19724 tmp |= fieldFromInstruction(insn, 22, 1) << 4;
19725 if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
19726 tmp = 0x0;
19727 tmp |= fieldFromInstruction(insn, 12, 4) << 0;
19728 tmp |= fieldFromInstruction(insn, 22, 1) << 4;
19729 if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
19730 tmp = 0x0;
19731 tmp |= fieldFromInstruction(insn, 0, 4) << 0;
19732 tmp |= fieldFromInstruction(insn, 5, 1) << 4;
19733 if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
19734 tmp = fieldFromInstruction(insn, 16, 6);
19735 if (!Check(S, DecodeShiftRight64Imm(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
19738 tmp = 0x0;
19739 tmp |= fieldFromInstruction(insn, 12, 4) << 0;
19740 tmp |= fieldFromInstruction(insn, 22, 1) << 4;
19741 if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
19742 tmp = 0x0;
19743 tmp |= fieldFromInstruction(insn, 0, 4) << 0;
19744 tmp |= fieldFromInstruction(insn, 5, 1) << 4;
19745 if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
19746 tmp = fieldFromInstruction(insn, 16, 6);
19747 MI.addOperand(MCOperand::createImm(tmp));
19750 tmp = 0x0;
19751 tmp |= fieldFromInstruction(insn, 12, 4) << 0;
19752 tmp |= fieldFromInstruction(insn, 22, 1) << 4;
19753 if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
19754 tmp = 0x0;
19755 tmp |= fieldFromInstruction(insn, 12, 4) << 0;
19756 tmp |= fieldFromInstruction(insn, 22, 1) << 4;
19757 if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
19758 tmp = 0x0;
19759 tmp |= fieldFromInstruction(insn, 0, 4) << 0;
19760 tmp |= fieldFromInstruction(insn, 5, 1) << 4;
19761 if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
19762 tmp = fieldFromInstruction(insn, 16, 6);
19763 MI.addOperand(MCOperand::createImm(tmp));
19766 tmp = 0x0;
19767 tmp |= fieldFromInstruction(insn, 12, 4) << 0;
19768 tmp |= fieldFromInstruction(insn, 22, 1) << 4;
19769 if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
19770 tmp = 0x0;
19771 tmp |= fieldFromInstruction(insn, 0, 4) << 0;
19772 tmp |= fieldFromInstruction(insn, 5, 1) << 4;
19773 if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
19774 tmp = fieldFromInstruction(insn, 16, 3);
19775 if (!Check(S, DecodeShiftRight8Imm(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
19778 tmp = 0x0;
19779 tmp |= fieldFromInstruction(insn, 12, 4) << 0;
19780 tmp |= fieldFromInstruction(insn, 22, 1) << 4;
19781 if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
19782 tmp = 0x0;
19783 tmp |= fieldFromInstruction(insn, 0, 4) << 0;
19784 tmp |= fieldFromInstruction(insn, 5, 1) << 4;
19785 if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
19786 tmp = fieldFromInstruction(insn, 16, 4);
19787 if (!Check(S, DecodeShiftRight16Imm(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
19790 tmp = 0x0;
19791 tmp |= fieldFromInstruction(insn, 12, 4) << 0;
19792 tmp |= fieldFromInstruction(insn, 22, 1) << 4;
19793 if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
19794 tmp = 0x0;
19795 tmp |= fieldFromInstruction(insn, 0, 4) << 0;
19796 tmp |= fieldFromInstruction(insn, 5, 1) << 4;
19797 if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
19798 tmp = fieldFromInstruction(insn, 16, 5);
19799 if (!Check(S, DecodeShiftRight32Imm(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
19802 tmp = 0x0;
19803 tmp |= fieldFromInstruction(insn, 12, 4) << 0;
19804 tmp |= fieldFromInstruction(insn, 22, 1) << 4;
19805 if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
19806 tmp = 0x0;
19807 tmp |= fieldFromInstruction(insn, 12, 4) << 0;
19808 tmp |= fieldFromInstruction(insn, 22, 1) << 4;
19809 if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
19810 tmp = 0x0;
19811 tmp |= fieldFromInstruction(insn, 0, 4) << 0;
19812 tmp |= fieldFromInstruction(insn, 5, 1) << 4;
19813 if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
19814 tmp = fieldFromInstruction(insn, 16, 3);
19815 if (!Check(S, DecodeShiftRight8Imm(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
19818 tmp = 0x0;
19819 tmp |= fieldFromInstruction(insn, 12, 4) << 0;
19820 tmp |= fieldFromInstruction(insn, 22, 1) << 4;
19821 if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
19822 tmp = 0x0;
19823 tmp |= fieldFromInstruction(insn, 12, 4) << 0;
19824 tmp |= fieldFromInstruction(insn, 22, 1) << 4;
19825 if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
19826 tmp = 0x0;
19827 tmp |= fieldFromInstruction(insn, 0, 4) << 0;
19828 tmp |= fieldFromInstruction(insn, 5, 1) << 4;
19829 if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
19830 tmp = fieldFromInstruction(insn, 16, 4);
19831 if (!Check(S, DecodeShiftRight16Imm(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
19834 tmp = 0x0;
19835 tmp |= fieldFromInstruction(insn, 12, 4) << 0;
19836 tmp |= fieldFromInstruction(insn, 22, 1) << 4;
19837 if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
19838 tmp = 0x0;
19839 tmp |= fieldFromInstruction(insn, 12, 4) << 0;
19840 tmp |= fieldFromInstruction(insn, 22, 1) << 4;
19841 if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
19842 tmp = 0x0;
19843 tmp |= fieldFromInstruction(insn, 0, 4) << 0;
19844 tmp |= fieldFromInstruction(insn, 5, 1) << 4;
19845 if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
19846 tmp = fieldFromInstruction(insn, 16, 5);
19847 if (!Check(S, DecodeShiftRight32Imm(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
19850 tmp = 0x0;
19851 tmp |= fieldFromInstruction(insn, 12, 4) << 0;
19852 tmp |= fieldFromInstruction(insn, 22, 1) << 4;
19853 if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
19854 tmp = 0x0;
19855 tmp |= fieldFromInstruction(insn, 0, 4) << 0;
19856 tmp |= fieldFromInstruction(insn, 5, 1) << 4;
19857 if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
19858 tmp = fieldFromInstruction(insn, 16, 3);
19859 MI.addOperand(MCOperand::createImm(tmp));
19862 tmp = 0x0;
19863 tmp |= fieldFromInstruction(insn, 12, 4) << 0;
19864 tmp |= fieldFromInstruction(insn, 22, 1) << 4;
19865 if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
19866 tmp = 0x0;
19867 tmp |= fieldFromInstruction(insn, 12, 4) << 0;
19868 tmp |= fieldFromInstruction(insn, 22, 1) << 4;
19869 if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
19870 tmp = 0x0;
19871 tmp |= fieldFromInstruction(insn, 0, 4) << 0;
19872 tmp |= fieldFromInstruction(insn, 5, 1) << 4;
19873 if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
19874 tmp = fieldFromInstruction(insn, 16, 3);
19875 MI.addOperand(MCOperand::createImm(tmp));
19878 tmp = 0x0;
19879 tmp |= fieldFromInstruction(insn, 12, 4) << 0;
19880 tmp |= fieldFromInstruction(insn, 22, 1) << 4;
19881 if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
19882 tmp = 0x0;
19883 tmp |= fieldFromInstruction(insn, 0, 4) << 0;
19884 tmp |= fieldFromInstruction(insn, 5, 1) << 4;
19885 if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
19886 tmp = fieldFromInstruction(insn, 16, 4);
19887 MI.addOperand(MCOperand::createImm(tmp));
19890 tmp = 0x0;
19891 tmp |= fieldFromInstruction(insn, 12, 4) << 0;
19892 tmp |= fieldFromInstruction(insn, 22, 1) << 4;
19893 if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
19894 tmp = 0x0;
19895 tmp |= fieldFromInstruction(insn, 12, 4) << 0;
19896 tmp |= fieldFromInstruction(insn, 22, 1) << 4;
19897 if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
19898 tmp = 0x0;
19899 tmp |= fieldFromInstruction(insn, 0, 4) << 0;
19900 tmp |= fieldFromInstruction(insn, 5, 1) << 4;
19901 if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
19902 tmp = fieldFromInstruction(insn, 16, 4);
19903 MI.addOperand(MCOperand::createImm(tmp));
19906 tmp = 0x0;
19907 tmp |= fieldFromInstruction(insn, 12, 4) << 0;
19908 tmp |= fieldFromInstruction(insn, 22, 1) << 4;
19909 if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
19910 tmp = 0x0;
19911 tmp |= fieldFromInstruction(insn, 0, 4) << 0;
19912 tmp |= fieldFromInstruction(insn, 5, 1) << 4;
19913 if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
19914 tmp = fieldFromInstruction(insn, 16, 5);
19915 MI.addOperand(MCOperand::createImm(tmp));
19918 tmp = 0x0;
19919 tmp |= fieldFromInstruction(insn, 12, 4) << 0;
19920 tmp |= fieldFromInstruction(insn, 22, 1) << 4;
19921 if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
19922 tmp = 0x0;
19923 tmp |= fieldFromInstruction(insn, 12, 4) << 0;
19924 tmp |= fieldFromInstruction(insn, 22, 1) << 4;
19925 if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
19926 tmp = 0x0;
19927 tmp |= fieldFromInstruction(insn, 0, 4) << 0;
19928 tmp |= fieldFromInstruction(insn, 5, 1) << 4;
19929 if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
19930 tmp = fieldFromInstruction(insn, 16, 5);
19931 MI.addOperand(MCOperand::createImm(tmp));
19937 tmp = 0x0;
19938 tmp |= fieldFromInstruction(insn, 12, 4) << 0;
19939 tmp |= fieldFromInstruction(insn, 22, 1) << 4;
19940 if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
19941 tmp = 0x0;
19942 tmp |= fieldFromInstruction(insn, 0, 4) << 0;
19943 tmp |= fieldFromInstruction(insn, 5, 1) << 4;
19944 if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
19945 tmp = fieldFromInstruction(insn, 16, 6);
19946 if (!Check(S, DecodeShiftRight64Imm(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
19949 tmp = 0x0;
19950 tmp |= fieldFromInstruction(insn, 12, 4) << 0;
19951 tmp |= fieldFromInstruction(insn, 22, 1) << 4;
19952 if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
19953 tmp = 0x0;
19954 tmp |= fieldFromInstruction(insn, 12, 4) << 0;
19955 tmp |= fieldFromInstruction(insn, 22, 1) << 4;
19956 if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
19957 tmp = 0x0;
19958 tmp |= fieldFromInstruction(insn, 0, 4) << 0;
19959 tmp |= fieldFromInstruction(insn, 5, 1) << 4;
19960 if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
19961 tmp = fieldFromInstruction(insn, 16, 6);
19962 if (!Check(S, DecodeShiftRight64Imm(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
19965 tmp = 0x0;
19966 tmp |= fieldFromInstruction(insn, 12, 4) << 0;
19967 tmp |= fieldFromInstruction(insn, 22, 1) << 4;
19968 if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
19969 tmp = 0x0;
19970 tmp |= fieldFromInstruction(insn, 0, 4) << 0;
19971 tmp |= fieldFromInstruction(insn, 5, 1) << 4;
19972 if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
19973 tmp = fieldFromInstruction(insn, 16, 6);
19974 MI.addOperand(MCOperand::createImm(tmp));
19977 tmp = 0x0;
19978 tmp |= fieldFromInstruction(insn, 12, 4) << 0;
19979 tmp |= fieldFromInstruction(insn, 22, 1) << 4;
19980 if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
19981 tmp = 0x0;
19982 tmp |= fieldFromInstruction(insn, 12, 4) << 0;
19983 tmp |= fieldFromInstruction(insn, 22, 1) << 4;
19984 if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
19985 tmp = 0x0;
19986 tmp |= fieldFromInstruction(insn, 0, 4) << 0;
19987 tmp |= fieldFromInstruction(insn, 5, 1) << 4;
19988 if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
19989 tmp = fieldFromInstruction(insn, 16, 6);
19990 MI.addOperand(MCOperand::createImm(tmp));
19993 tmp = 0x0;
19994 tmp |= fieldFromInstruction(insn, 7, 1) << 4;
19995 tmp |= fieldFromInstruction(insn, 16, 4) << 0;
19996 if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
19997 tmp = 0x0;
19998 tmp |= fieldFromInstruction(insn, 7, 1) << 4;
19999 tmp |= fieldFromInstruction(insn, 16, 4) << 0;
20000 if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
20001 tmp = fieldFromInstruction(insn, 12, 4);
20002 if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
20003 tmp = fieldFromInstruction(insn, 21, 1);
20004 MI.addOperand(MCOperand::createImm(tmp));
20005 tmp = fieldFromInstruction(insn, 28, 4);
20006 if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
20009 tmp = fieldFromInstruction(insn, 12, 4);
20010 if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
20011 tmp = 0x0;
20012 tmp |= fieldFromInstruction(insn, 7, 1) << 4;
20013 tmp |= fieldFromInstruction(insn, 16, 4) << 0;
20014 if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
20015 tmp = fieldFromInstruction(insn, 21, 1);
20016 MI.addOperand(MCOperand::createImm(tmp));
20017 tmp = fieldFromInstruction(insn, 28, 4);
20018 if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
20021 tmp = 0x0;
20022 tmp |= fieldFromInstruction(insn, 7, 1) << 4;
20023 tmp |= fieldFromInstruction(insn, 16, 4) << 0;
20024 if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
20025 tmp = 0x0;
20026 tmp |= fieldFromInstruction(insn, 7, 1) << 4;
20027 tmp |= fieldFromInstruction(insn, 16, 4) << 0;
20028 if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
20029 tmp = fieldFromInstruction(insn, 12, 4);
20030 if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
20031 tmp = 0x0;
20032 tmp |= fieldFromInstruction(insn, 6, 1) << 0;
20033 tmp |= fieldFromInstruction(insn, 21, 1) << 1;
20034 MI.addOperand(MCOperand::createImm(tmp));
20035 tmp = fieldFromInstruction(insn, 28, 4);
20036 if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
20039 tmp = fieldFromInstruction(insn, 12, 4);
20040 if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
20041 tmp = 0x0;
20042 tmp |= fieldFromInstruction(insn, 7, 1) << 4;
20043 tmp |= fieldFromInstruction(insn, 16, 4) << 0;
20044 if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
20045 tmp = 0x0;
20046 tmp |= fieldFromInstruction(insn, 6, 1) << 0;
20047 tmp |= fieldFromInstruction(insn, 21, 1) << 1;
20048 MI.addOperand(MCOperand::createImm(tmp));
20049 tmp = fieldFromInstruction(insn, 28, 4);
20050 if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
20053 tmp = 0x0;
20054 tmp |= fieldFromInstruction(insn, 7, 1) << 4;
20055 tmp |= fieldFromInstruction(insn, 16, 4) << 0;
20056 if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
20057 tmp = 0x0;
20058 tmp |= fieldFromInstruction(insn, 7, 1) << 4;
20059 tmp |= fieldFromInstruction(insn, 16, 4) << 0;
20060 if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
20061 tmp = fieldFromInstruction(insn, 12, 4);
20062 if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
20063 tmp = 0x0;
20064 tmp |= fieldFromInstruction(insn, 5, 2) << 0;
20065 tmp |= fieldFromInstruction(insn, 21, 1) << 2;
20066 MI.addOperand(MCOperand::createImm(tmp));
20067 tmp = fieldFromInstruction(insn, 28, 4);
20068 if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
20071 tmp = fieldFromInstruction(insn, 12, 4);
20072 if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
20073 tmp = 0x0;
20074 tmp |= fieldFromInstruction(insn, 7, 1) << 4;
20075 tmp |= fieldFromInstruction(insn, 16, 4) << 0;
20076 if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
20077 tmp = 0x0;
20078 tmp |= fieldFromInstruction(insn, 5, 2) << 0;
20079 tmp |= fieldFromInstruction(insn, 21, 1) << 2;
20080 MI.addOperand(MCOperand::createImm(tmp));
20081 tmp = fieldFromInstruction(insn, 28, 4);
20082 if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
20085 tmp = 0x0;
20086 tmp |= fieldFromInstruction(insn, 7, 1) << 4;
20087 tmp |= fieldFromInstruction(insn, 16, 4) << 0;
20088 if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
20089 tmp = fieldFromInstruction(insn, 12, 4);
20090 if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
20091 tmp = fieldFromInstruction(insn, 28, 4);
20092 if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
20095 tmp = 0x0;
20096 tmp |= fieldFromInstruction(insn, 7, 1) << 4;
20097 tmp |= fieldFromInstruction(insn, 16, 4) << 0;
20098 if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
20099 tmp = fieldFromInstruction(insn, 12, 4);
20100 if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
20101 tmp = fieldFromInstruction(insn, 28, 4);
20102 if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
20153 tmp = fieldFromInstruction(insn, 0, 3);
20154 if (!Check(S, DecodetGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
20155 tmp = fieldFromInstruction(insn, 3, 3);
20156 if (!Check(S, DecodetGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
20159 tmp = fieldFromInstruction(insn, 8, 3);
20160 if (!Check(S, DecodetGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
20161 tmp = fieldFromInstruction(insn, 0, 8);
20162 MI.addOperand(MCOperand::createImm(tmp));
20168 tmp = 0x0;
20169 tmp |= fieldFromInstruction(insn, 0, 3) << 0;
20170 tmp |= fieldFromInstruction(insn, 7, 1) << 3;
20171 if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
20172 tmp = 0x0;
20173 tmp |= fieldFromInstruction(insn, 0, 3) << 0;
20174 tmp |= fieldFromInstruction(insn, 7, 1) << 3;
20175 if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
20176 tmp = fieldFromInstruction(insn, 3, 4);
20177 if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
20180 tmp = 0x0;
20181 tmp |= fieldFromInstruction(insn, 0, 3) << 0;
20182 tmp |= fieldFromInstruction(insn, 7, 1) << 3;
20183 if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
20184 tmp = fieldFromInstruction(insn, 3, 4);
20185 if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
20188 tmp = fieldFromInstruction(insn, 3, 4);
20189 if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
20192 tmp = fieldFromInstruction(insn, 3, 4);
20193 if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
20196 tmp = fieldFromInstruction(insn, 8, 3);
20197 if (!Check(S, DecodetGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
20198 tmp = fieldFromInstruction(insn, 0, 8);
20199 if (!Check(S, DecodeThumbAddrModePC(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
20202 tmp = fieldFromInstruction(insn, 0, 3);
20203 if (!Check(S, DecodetGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
20204 tmp = fieldFromInstruction(insn, 3, 6);
20205 if (!Check(S, DecodeThumbAddrModeRR(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
20208 tmp = fieldFromInstruction(insn, 0, 3);
20209 if (!Check(S, DecodetGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
20210 tmp = fieldFromInstruction(insn, 3, 8);
20211 if (!Check(S, DecodeThumbAddrModeIS(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
20214 tmp = fieldFromInstruction(insn, 8, 3);
20215 if (!Check(S, DecodetGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
20216 tmp = fieldFromInstruction(insn, 0, 8);
20217 if (!Check(S, DecodeThumbAddrModeSP(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
20226 tmp = fieldFromInstruction(insn, 0, 3);
20227 if (!Check(S, DecodetGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
20228 tmp = 0x0;
20229 tmp |= fieldFromInstruction(insn, 3, 5) << 0;
20230 tmp |= fieldFromInstruction(insn, 9, 1) << 5;
20231 if (!Check(S, DecodeThumbCmpBROperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
20234 tmp = 0x0;
20235 tmp |= fieldFromInstruction(insn, 0, 8) << 0;
20236 tmp |= fieldFromInstruction(insn, 8, 1) << 14;
20237 if (!Check(S, DecodeRegListOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
20240 tmp = fieldFromInstruction(insn, 3, 1);
20241 MI.addOperand(MCOperand::createImm(tmp));
20247 tmp = fieldFromInstruction(insn, 0, 6);
20248 MI.addOperand(MCOperand::createImm(tmp));
20251 tmp = 0x0;
20252 tmp |= fieldFromInstruction(insn, 0, 8) << 0;
20253 tmp |= fieldFromInstruction(insn, 8, 1) << 15;
20254 if (!Check(S, DecodeRegListOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
20257 tmp = fieldFromInstruction(insn, 0, 8);
20258 MI.addOperand(MCOperand::createImm(tmp));
20261 tmp = fieldFromInstruction(insn, 4, 4);
20262 MI.addOperand(MCOperand::createImm(tmp));
20265 tmp = fieldFromInstruction(insn, 8, 3);
20266 if (!Check(S, DecodetGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
20267 tmp = fieldFromInstruction(insn, 8, 3);
20268 if (!Check(S, DecodetGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
20269 tmp = fieldFromInstruction(insn, 0, 8);
20270 if (!Check(S, DecodeRegListOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
20273 tmp = fieldFromInstruction(insn, 8, 3);
20274 if (!Check(S, DecodetGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
20275 tmp = fieldFromInstruction(insn, 0, 8);
20276 if (!Check(S, DecodeRegListOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
20279 tmp = fieldFromInstruction(insn, 0, 8);
20280 if (!Check(S, DecodeThumbBCCTargetOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
20281 tmp = fieldFromInstruction(insn, 8, 4);
20282 if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
20285 tmp = fieldFromInstruction(insn, 0, 11);
20286 if (!Check(S, DecodeThumbBROperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
20289 tmp = 0x0;
20290 tmp |= fieldFromInstruction(insn, 1, 10) << 1;
20291 tmp |= fieldFromInstruction(insn, 11, 1) << 21;
20292 tmp |= fieldFromInstruction(insn, 13, 1) << 22;
20293 tmp |= fieldFromInstruction(insn, 16, 10) << 11;
20294 tmp |= fieldFromInstruction(insn, 26, 1) << 23;
20295 if (!Check(S, DecodeThumbBLXOffset(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
20298 tmp = 0x0;
20299 tmp |= fieldFromInstruction(insn, 0, 11) << 0;
20300 tmp |= fieldFromInstruction(insn, 11, 1) << 21;
20301 tmp |= fieldFromInstruction(insn, 13, 1) << 22;
20302 tmp |= fieldFromInstruction(insn, 16, 10) << 11;
20303 tmp |= fieldFromInstruction(insn, 26, 1) << 23;
20304 if (!Check(S, DecodeThumbBLTargetOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
20310 tmp = fieldFromInstruction(insn, 16, 4);
20311 if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
20312 tmp = 0x0;
20313 tmp |= fieldFromInstruction(insn, 0, 13) << 0;
20314 tmp |= fieldFromInstruction(insn, 14, 1) << 14;
20315 if (!Check(S, DecodeRegListOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
20318 tmp = 0x0;
20319 tmp |= fieldFromInstruction(insn, 0, 13) << 0;
20320 tmp |= fieldFromInstruction(insn, 14, 2) << 14;
20321 if (!Check(S, DecodeRegListOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
20324 tmp = fieldFromInstruction(insn, 16, 4);
20325 if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
20326 tmp = fieldFromInstruction(insn, 0, 16);
20327 if (!Check(S, DecodeRegListOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
20330 tmp = fieldFromInstruction(insn, 16, 4);
20331 if (!Check(S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
20332 tmp = fieldFromInstruction(insn, 0, 4);
20333 if (!Check(S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
20336 tmp = fieldFromInstruction(insn, 16, 4);
20337 if (!Check(S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
20338 tmp = 0x0;
20339 tmp |= fieldFromInstruction(insn, 0, 4) << 0;
20340 tmp |= fieldFromInstruction(insn, 4, 4) << 5;
20341 tmp |= fieldFromInstruction(insn, 12, 3) << 9;
20342 if (!Check(S, DecodeSORegImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
20345 tmp = fieldFromInstruction(insn, 8, 4);
20346 if (!Check(S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
20347 tmp = fieldFromInstruction(insn, 16, 4);
20348 if (!Check(S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
20349 tmp = fieldFromInstruction(insn, 0, 4);
20350 if (!Check(S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
20351 tmp = fieldFromInstruction(insn, 20, 1);
20352 if (!Check(S, DecodeCCOutOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
20355 tmp = fieldFromInstruction(insn, 8, 4);
20356 if (!Check(S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
20357 tmp = fieldFromInstruction(insn, 16, 4);
20358 if (!Check(S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
20359 tmp = 0x0;
20360 tmp |= fieldFromInstruction(insn, 0, 4) << 0;
20361 tmp |= fieldFromInstruction(insn, 4, 4) << 5;
20362 tmp |= fieldFromInstruction(insn, 12, 3) << 9;
20363 if (!Check(S, DecodeSORegImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
20364 tmp = fieldFromInstruction(insn, 20, 1);
20365 if (!Check(S, DecodeCCOutOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
20368 tmp = fieldFromInstruction(insn, 16, 4);
20369 if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
20370 tmp = fieldFromInstruction(insn, 0, 4);
20371 if (!Check(S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
20374 tmp = fieldFromInstruction(insn, 16, 4);
20375 if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
20376 tmp = 0x0;
20377 tmp |= fieldFromInstruction(insn, 0, 4) << 0;
20378 tmp |= fieldFromInstruction(insn, 4, 4) << 5;
20379 tmp |= fieldFromInstruction(insn, 12, 3) << 9;
20380 if (!Check(S, DecodeSORegImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
20383 tmp = fieldFromInstruction(insn, 8, 4);
20384 if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
20385 tmp = fieldFromInstruction(insn, 16, 4);
20386 if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
20387 tmp = fieldFromInstruction(insn, 0, 4);
20388 if (!Check(S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
20389 tmp = fieldFromInstruction(insn, 20, 1);
20390 if (!Check(S, DecodeCCOutOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
20393 tmp = fieldFromInstruction(insn, 8, 4);
20394 if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
20395 tmp = fieldFromInstruction(insn, 16, 4);
20396 if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
20397 tmp = 0x0;
20398 tmp |= fieldFromInstruction(insn, 0, 4) << 0;
20399 tmp |= fieldFromInstruction(insn, 4, 4) << 5;
20400 tmp |= fieldFromInstruction(insn, 12, 3) << 9;
20401 if (!Check(S, DecodeSORegImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
20402 tmp = fieldFromInstruction(insn, 20, 1);
20403 if (!Check(S, DecodeCCOutOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
20406 tmp = fieldFromInstruction(insn, 16, 4);
20407 if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
20408 tmp = fieldFromInstruction(insn, 16, 4);
20409 if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
20410 tmp = 0x0;
20411 tmp |= fieldFromInstruction(insn, 0, 13) << 0;
20412 tmp |= fieldFromInstruction(insn, 14, 1) << 14;
20413 if (!Check(S, DecodeRegListOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
20416 tmp = fieldFromInstruction(insn, 16, 4);
20417 if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
20418 tmp = fieldFromInstruction(insn, 16, 4);
20419 if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
20420 tmp = fieldFromInstruction(insn, 0, 16);
20421 if (!Check(S, DecodeRegListOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
20424 tmp = fieldFromInstruction(insn, 8, 4);
20425 if (!Check(S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
20426 tmp = fieldFromInstruction(insn, 16, 4);
20427 if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
20430 tmp = fieldFromInstruction(insn, 8, 4);
20431 if (!Check(S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
20432 tmp = fieldFromInstruction(insn, 12, 4);
20433 if (!Check(S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
20434 tmp = 0x0;
20435 tmp |= fieldFromInstruction(insn, 0, 8) << 0;
20436 tmp |= fieldFromInstruction(insn, 16, 4) << 8;
20437 if (!Check(S, DecodeT2AddrModeImm0_1020s4(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
20440 tmp = fieldFromInstruction(insn, 0, 4);
20441 if (!Check(S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
20442 tmp = fieldFromInstruction(insn, 12, 4);
20443 if (!Check(S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
20444 tmp = fieldFromInstruction(insn, 16, 4);
20445 if (!Check(S, DecodeAddrMode7Operand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
20448 tmp = fieldFromInstruction(insn, 0, 4);
20449 if (!Check(S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
20450 tmp = fieldFromInstruction(insn, 12, 4);
20451 if (!Check(S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
20452 tmp = fieldFromInstruction(insn, 8, 4);
20453 if (!Check(S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
20454 tmp = fieldFromInstruction(insn, 16, 4);
20455 if (!Check(S, DecodeAddrMode7Operand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
20458 tmp = fieldFromInstruction(insn, 12, 4);
20459 if (!Check(S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
20460 tmp = fieldFromInstruction(insn, 16, 4);
20461 if (!Check(S, DecodeAddrMode7Operand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
20464 tmp = fieldFromInstruction(insn, 12, 4);
20465 if (!Check(S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
20466 tmp = 0x0;
20467 tmp |= fieldFromInstruction(insn, 0, 8) << 0;
20468 tmp |= fieldFromInstruction(insn, 16, 4) << 8;
20469 if (!Check(S, DecodeT2AddrModeImm0_1020s4(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
20475 tmp = fieldFromInstruction(insn, 12, 4);
20476 if (!Check(S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
20477 tmp = fieldFromInstruction(insn, 8, 4);
20478 if (!Check(S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
20479 tmp = fieldFromInstruction(insn, 16, 4);
20480 if (!Check(S, DecodeAddrMode7Operand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
20483 tmp = fieldFromInstruction(insn, 12, 4);
20484 if (!Check(S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
20485 tmp = fieldFromInstruction(insn, 8, 4);
20486 if (!Check(S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
20487 tmp = 0x0;
20488 tmp |= fieldFromInstruction(insn, 0, 8) << 0;
20489 tmp |= fieldFromInstruction(insn, 16, 4) << 9;
20490 tmp |= fieldFromInstruction(insn, 23, 1) << 8;
20491 if (!Check(S, DecodeT2AddrModeImm8s4(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
20494 tmp = fieldFromInstruction(insn, 8, 4);
20495 if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
20496 tmp = fieldFromInstruction(insn, 0, 4);
20497 if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
20498 tmp = fieldFromInstruction(insn, 20, 1);
20499 if (!Check(S, DecodeCCOutOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
20502 tmp = fieldFromInstruction(insn, 8, 4);
20503 if (!Check(S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
20504 tmp = fieldFromInstruction(insn, 0, 4);
20505 if (!Check(S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
20506 tmp = fieldFromInstruction(insn, 20, 1);
20507 if (!Check(S, DecodeCCOutOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
20510 tmp = fieldFromInstruction(insn, 8, 4);
20511 if (!Check(S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
20512 tmp = fieldFromInstruction(insn, 0, 4);
20513 if (!Check(S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
20514 tmp = 0x0;
20515 tmp |= fieldFromInstruction(insn, 6, 2) << 0;
20516 tmp |= fieldFromInstruction(insn, 12, 3) << 2;
20517 MI.addOperand(MCOperand::createImm(tmp));
20518 tmp = fieldFromInstruction(insn, 20, 1);
20519 if (!Check(S, DecodeCCOutOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
20522 tmp = fieldFromInstruction(insn, 8, 4);
20523 if (!Check(S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
20524 tmp = fieldFromInstruction(insn, 16, 4);
20525 if (!Check(S, DecodeGPRwithZRnospRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
20526 tmp = fieldFromInstruction(insn, 0, 4);
20527 if (!Check(S, DecodeGPRwithZRnospRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
20528 tmp = fieldFromInstruction(insn, 4, 4);
20529 if (!Check(S, DecodePredNoALOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
20532 tmp = fieldFromInstruction(insn, 8, 4);
20533 if (!Check(S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
20534 tmp = fieldFromInstruction(insn, 16, 4);
20535 if (!Check(S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
20536 tmp = fieldFromInstruction(insn, 0, 4);
20537 if (!Check(S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
20538 tmp = 0x0;
20539 tmp |= fieldFromInstruction(insn, 6, 2) << 0;
20540 tmp |= fieldFromInstruction(insn, 12, 3) << 2;
20541 MI.addOperand(MCOperand::createImm(tmp));
20544 tmp = fieldFromInstruction(insn, 16, 4);
20545 if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
20546 tmp = fieldFromInstruction(insn, 12, 4);
20547 if (!Check(S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
20548 tmp = fieldFromInstruction(insn, 8, 4);
20549 if (!Check(S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
20550 tmp = fieldFromInstruction(insn, 16, 4);
20551 if (!Check(S, DecodeAddrMode7Operand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
20552 tmp = 0x0;
20553 tmp |= fieldFromInstruction(insn, 0, 8) << 0;
20554 tmp |= fieldFromInstruction(insn, 23, 1) << 8;
20555 if (!Check(S, DecodeT2Imm8S4(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
20558 tmp = fieldFromInstruction(insn, 12, 4);
20559 if (!Check(S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
20560 tmp = fieldFromInstruction(insn, 8, 4);
20561 if (!Check(S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
20562 tmp = fieldFromInstruction(insn, 16, 4);
20563 if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
20564 tmp = fieldFromInstruction(insn, 16, 4);
20565 if (!Check(S, DecodeAddrMode7Operand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
20566 tmp = 0x0;
20567 tmp |= fieldFromInstruction(insn, 0, 8) << 0;
20568 tmp |= fieldFromInstruction(insn, 23, 1) << 8;
20569 if (!Check(S, DecodeT2Imm8S4(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
20578 tmp = fieldFromInstruction(insn, 8, 4);
20579 if (!Check(S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
20580 tmp = 0x0;
20581 tmp |= fieldFromInstruction(insn, 0, 4) << 0;
20582 tmp |= fieldFromInstruction(insn, 4, 4) << 5;
20583 tmp |= fieldFromInstruction(insn, 12, 3) << 9;
20584 if (!Check(S, DecodeSORegImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
20585 tmp = fieldFromInstruction(insn, 20, 1);
20586 if (!Check(S, DecodeCCOutOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
20589 tmp = fieldFromInstruction(insn, 16, 4);
20590 if (!Check(S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
20591 tmp = 0x0;
20592 tmp |= fieldFromInstruction(insn, 0, 8) << 0;
20593 tmp |= fieldFromInstruction(insn, 12, 3) << 8;
20594 tmp |= fieldFromInstruction(insn, 26, 1) << 11;
20595 if (!Check(S, DecodeT2SOImm(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
20598 tmp = fieldFromInstruction(insn, 8, 4);
20599 if (!Check(S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
20600 tmp = fieldFromInstruction(insn, 16, 4);
20601 if (!Check(S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
20602 tmp = 0x0;
20603 tmp |= fieldFromInstruction(insn, 0, 8) << 0;
20604 tmp |= fieldFromInstruction(insn, 12, 3) << 8;
20605 tmp |= fieldFromInstruction(insn, 26, 1) << 11;
20606 if (!Check(S, DecodeT2SOImm(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
20607 tmp = fieldFromInstruction(insn, 20, 1);
20608 if (!Check(S, DecodeCCOutOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
20611 tmp = fieldFromInstruction(insn, 8, 4);
20612 if (!Check(S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
20613 tmp = 0x0;
20614 tmp |= fieldFromInstruction(insn, 0, 8) << 0;
20615 tmp |= fieldFromInstruction(insn, 12, 3) << 8;
20616 tmp |= fieldFromInstruction(insn, 26, 1) << 11;
20617 if (!Check(S, DecodeT2SOImm(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
20618 tmp = fieldFromInstruction(insn, 20, 1);
20619 if (!Check(S, DecodeCCOutOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
20622 tmp = fieldFromInstruction(insn, 16, 4);
20623 if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
20624 tmp = 0x0;
20625 tmp |= fieldFromInstruction(insn, 0, 8) << 0;
20626 tmp |= fieldFromInstruction(insn, 12, 3) << 8;
20627 tmp |= fieldFromInstruction(insn, 26, 1) << 11;
20628 if (!Check(S, DecodeT2SOImm(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
20631 tmp = fieldFromInstruction(insn, 8, 4);
20632 if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
20633 tmp = fieldFromInstruction(insn, 16, 4);
20634 if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
20635 tmp = 0x0;
20636 tmp |= fieldFromInstruction(insn, 0, 8) << 0;
20637 tmp |= fieldFromInstruction(insn, 12, 3) << 8;
20638 tmp |= fieldFromInstruction(insn, 26, 1) << 11;
20639 if (!Check(S, DecodeT2SOImm(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
20640 tmp = fieldFromInstruction(insn, 20, 1);
20641 if (!Check(S, DecodeCCOutOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
20644 tmp = fieldFromInstruction(insn, 8, 4);
20645 if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
20646 tmp = fieldFromInstruction(insn, 16, 4);
20647 if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
20648 tmp = 0x0;
20649 tmp |= fieldFromInstruction(insn, 0, 8) << 0;
20650 tmp |= fieldFromInstruction(insn, 12, 3) << 8;
20651 tmp |= fieldFromInstruction(insn, 26, 1) << 11;
20652 MI.addOperand(MCOperand::createImm(tmp));
20661 tmp = fieldFromInstruction(insn, 8, 4);
20662 if (!Check(S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
20663 tmp = fieldFromInstruction(insn, 0, 4);
20664 MI.addOperand(MCOperand::createImm(tmp));
20665 tmp = fieldFromInstruction(insn, 16, 4);
20666 if (!Check(S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
20669 tmp = fieldFromInstruction(insn, 8, 4);
20670 if (!Check(S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
20671 tmp = fieldFromInstruction(insn, 0, 5);
20672 MI.addOperand(MCOperand::createImm(tmp));
20673 tmp = fieldFromInstruction(insn, 16, 4);
20674 if (!Check(S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
20675 tmp = 0x0;
20676 tmp |= fieldFromInstruction(insn, 6, 2) << 0;
20677 tmp |= fieldFromInstruction(insn, 12, 3) << 2;
20678 tmp |= fieldFromInstruction(insn, 21, 1) << 5;
20679 if (!Check(S, DecodeT2ShifterImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
20682 tmp = fieldFromInstruction(insn, 8, 4);
20683 if (!Check(S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
20684 tmp = fieldFromInstruction(insn, 16, 4);
20685 if (!Check(S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
20686 tmp = 0x0;
20687 tmp |= fieldFromInstruction(insn, 6, 2) << 0;
20688 tmp |= fieldFromInstruction(insn, 12, 3) << 2;
20689 MI.addOperand(MCOperand::createImm(tmp));
20690 tmp = fieldFromInstruction(insn, 0, 5);
20691 MI.addOperand(MCOperand::createImm(tmp));
20694 tmp = fieldFromInstruction(insn, 8, 4);
20695 if (!Check(S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
20696 tmp = fieldFromInstruction(insn, 8, 4);
20697 if (!Check(S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
20698 tmp = 0x0;
20699 tmp |= fieldFromInstruction(insn, 0, 5) << 5;
20700 tmp |= fieldFromInstruction(insn, 6, 2) << 0;
20701 tmp |= fieldFromInstruction(insn, 12, 3) << 2;
20702 if (!Check(S, DecodeBitfieldMaskOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
20705 tmp = fieldFromInstruction(insn, 8, 4);
20706 if (!Check(S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
20707 tmp = fieldFromInstruction(insn, 8, 4);
20708 if (!Check(S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
20709 tmp = fieldFromInstruction(insn, 16, 4);
20710 if (!Check(S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
20711 tmp = 0x0;
20712 tmp |= fieldFromInstruction(insn, 0, 5) << 5;
20713 tmp |= fieldFromInstruction(insn, 6, 2) << 0;
20714 tmp |= fieldFromInstruction(insn, 12, 3) << 2;
20715 if (!Check(S, DecodeBitfieldMaskOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
20718 tmp = fieldFromInstruction(insn, 16, 4);
20719 if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
20722 tmp = fieldFromInstruction(insn, 0, 4);
20723 MI.addOperand(MCOperand::createImm(tmp));
20729 tmp = fieldFromInstruction(insn, 8, 4);
20730 if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
20733 tmp = 0x0;
20734 tmp |= fieldFromInstruction(insn, 0, 12) << 0;
20735 tmp |= fieldFromInstruction(insn, 16, 4) << 12;
20736 MI.addOperand(MCOperand::createImm(tmp));
20739 tmp = fieldFromInstruction(insn, 16, 4);
20740 MI.addOperand(MCOperand::createImm(tmp));
20743 tmp = 0x0;
20744 tmp |= fieldFromInstruction(insn, 8, 4) << 0;
20745 tmp |= fieldFromInstruction(insn, 20, 1) << 4;
20746 if (!Check(S, DecodeMSRMask(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
20747 tmp = fieldFromInstruction(insn, 16, 4);
20748 if (!Check(S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
20751 tmp = 0x0;
20752 tmp |= fieldFromInstruction(insn, 4, 1) << 4;
20753 tmp |= fieldFromInstruction(insn, 8, 4) << 0;
20754 tmp |= fieldFromInstruction(insn, 20, 1) << 5;
20755 if (!Check(S, DecodeBankedReg(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
20756 tmp = fieldFromInstruction(insn, 16, 4);
20757 if (!Check(S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
20760 tmp = 0x0;
20761 tmp |= fieldFromInstruction(insn, 0, 8) << 0;
20762 tmp |= fieldFromInstruction(insn, 10, 2) << 10;
20763 if (!Check(S, DecodeMSRMask(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
20764 tmp = fieldFromInstruction(insn, 16, 4);
20765 if (!Check(S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
20768 tmp = fieldFromInstruction(insn, 8, 4);
20769 if (!Check(S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
20770 tmp = 0x0;
20771 tmp |= fieldFromInstruction(insn, 4, 1) << 4;
20772 tmp |= fieldFromInstruction(insn, 16, 4) << 0;
20773 tmp |= fieldFromInstruction(insn, 20, 1) << 5;
20774 if (!Check(S, DecodeBankedReg(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
20777 tmp = fieldFromInstruction(insn, 8, 4);
20778 if (!Check(S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
20779 tmp = fieldFromInstruction(insn, 0, 8);
20780 if (!Check(S, DecodeMSRMask(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
20789 tmp = fieldFromInstruction(insn, 23, 4);
20790 if (!Check(S, DecodeBFLabelOperand<false, false, false, 4>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
20791 tmp = 0x0;
20792 tmp |= fieldFromInstruction(insn, 1, 10) << 1;
20793 tmp |= fieldFromInstruction(insn, 11, 1) << 0;
20794 tmp |= fieldFromInstruction(insn, 16, 7) << 11;
20795 if (!Check(S, DecodeBFLabelOperand<true, false, true, 18>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
20798 tmp = fieldFromInstruction(insn, 23, 4);
20799 if (!Check(S, DecodeBFLabelOperand<false, false, false, 4>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
20800 tmp = 0x0;
20801 tmp |= fieldFromInstruction(insn, 1, 10) << 1;
20802 tmp |= fieldFromInstruction(insn, 11, 1) << 0;
20803 tmp |= fieldFromInstruction(insn, 16, 1) << 11;
20804 if (!Check(S, DecodeBFLabelOperand<true, false, true, 12>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
20805 tmp = fieldFromInstruction(insn, 17, 1);
20806 if (!Check(S, DecodeBFAfterTargetOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
20807 tmp = fieldFromInstruction(insn, 18, 4);
20808 if (!Check(S, DecodePredNoALOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
20811 tmp = fieldFromInstruction(insn, 23, 4);
20812 if (!Check(S, DecodeBFLabelOperand<false, false, false, 4>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
20813 tmp = 0x0;
20814 tmp |= fieldFromInstruction(insn, 1, 10) << 1;
20815 tmp |= fieldFromInstruction(insn, 11, 1) << 0;
20816 tmp |= fieldFromInstruction(insn, 16, 5) << 11;
20817 if (!Check(S, DecodeBFLabelOperand<true, false, true, 16>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
20820 tmp = fieldFromInstruction(insn, 23, 4);
20821 if (!Check(S, DecodeBFLabelOperand<false, false, false, 4>(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
20822 tmp = fieldFromInstruction(insn, 16, 4);
20823 if (!Check(S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
20829 tmp = fieldFromInstruction(insn, 12, 4);
20830 if (!Check(S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
20831 tmp = 0x0;
20832 tmp |= fieldFromInstruction(insn, 0, 4) << 2;
20833 tmp |= fieldFromInstruction(insn, 4, 2) << 0;
20834 tmp |= fieldFromInstruction(insn, 16, 4) << 6;
20835 if (!Check(S, DecodeT2AddrModeSOReg(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
20841 tmp = fieldFromInstruction(insn, 12, 4);
20842 if (!Check(S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
20843 tmp = 0x0;
20844 tmp |= fieldFromInstruction(insn, 0, 8) << 0;
20845 tmp |= fieldFromInstruction(insn, 16, 4) << 9;
20846 if (!Check(S, DecodeT2AddrModeImm8(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
20849 tmp = fieldFromInstruction(insn, 12, 4);
20850 if (!Check(S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
20851 tmp = 0x0;
20852 tmp |= fieldFromInstruction(insn, 0, 8) << 0;
20853 tmp |= fieldFromInstruction(insn, 9, 1) << 8;
20854 tmp |= fieldFromInstruction(insn, 16, 4) << 9;
20855 if (!Check(S, DecodeT2AddrModeImm8(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
20858 tmp = fieldFromInstruction(insn, 12, 4);
20859 if (!Check(S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
20860 tmp = 0x1000;
20861 tmp |= fieldFromInstruction(insn, 0, 12) << 0;
20862 tmp |= fieldFromInstruction(insn, 16, 4) << 13;
20863 if (!Check(S, DecodeT2AddrModeImm12(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
20881 tmp = fieldFromInstruction(insn, 8, 4);
20882 if (!Check(S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
20883 tmp = fieldFromInstruction(insn, 16, 4);
20884 if (!Check(S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
20885 tmp = fieldFromInstruction(insn, 0, 4);
20886 if (!Check(S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
20889 tmp = fieldFromInstruction(insn, 8, 4);
20890 if (!Check(S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
20891 tmp = fieldFromInstruction(insn, 0, 4);
20892 if (!Check(S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
20893 tmp = fieldFromInstruction(insn, 4, 2);
20894 MI.addOperand(MCOperand::createImm(tmp));
20897 tmp = fieldFromInstruction(insn, 8, 4);
20898 if (!Check(S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
20899 tmp = fieldFromInstruction(insn, 16, 4);
20900 if (!Check(S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
20901 tmp = fieldFromInstruction(insn, 0, 4);
20902 if (!Check(S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
20903 tmp = fieldFromInstruction(insn, 4, 2);
20904 MI.addOperand(MCOperand::createImm(tmp));
20907 tmp = fieldFromInstruction(insn, 8, 4);
20908 if (!Check(S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
20909 tmp = fieldFromInstruction(insn, 0, 4);
20910 if (!Check(S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
20911 tmp = fieldFromInstruction(insn, 16, 4);
20912 if (!Check(S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
20915 tmp = fieldFromInstruction(insn, 8, 4);
20916 if (!Check(S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
20917 tmp = 0x0;
20918 tmp |= fieldFromInstruction(insn, 0, 4) << 0;
20919 tmp |= fieldFromInstruction(insn, 16, 4) << 0;
20920 if (!Check(S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
20923 tmp = fieldFromInstruction(insn, 8, 4);
20924 if (!Check(S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
20925 tmp = fieldFromInstruction(insn, 16, 4);
20926 if (!Check(S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
20927 tmp = fieldFromInstruction(insn, 0, 4);
20928 if (!Check(S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
20929 tmp = fieldFromInstruction(insn, 12, 4);
20930 if (!Check(S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
20933 tmp = fieldFromInstruction(insn, 12, 4);
20934 if (!Check(S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
20935 tmp = fieldFromInstruction(insn, 8, 4);
20936 if (!Check(S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
20937 tmp = fieldFromInstruction(insn, 16, 4);
20938 if (!Check(S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
20939 tmp = fieldFromInstruction(insn, 0, 4);
20940 if (!Check(S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
20943 tmp = fieldFromInstruction(insn, 8, 4);
20944 if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
20945 tmp = fieldFromInstruction(insn, 16, 4);
20946 if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
20947 tmp = fieldFromInstruction(insn, 0, 4);
20948 if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
20951 tmp = fieldFromInstruction(insn, 12, 4);
20952 if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
20953 tmp = 0x0;
20954 tmp |= fieldFromInstruction(insn, 0, 4) << 2;
20955 tmp |= fieldFromInstruction(insn, 4, 2) << 0;
20956 tmp |= fieldFromInstruction(insn, 16, 4) << 6;
20957 if (!Check(S, DecodeT2AddrModeSOReg(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
20960 tmp = fieldFromInstruction(insn, 12, 4);
20961 if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
20962 tmp = 0x0;
20963 tmp |= fieldFromInstruction(insn, 0, 8) << 0;
20964 tmp |= fieldFromInstruction(insn, 9, 1) << 8;
20965 tmp |= fieldFromInstruction(insn, 16, 4) << 9;
20966 if (!Check(S, DecodeT2AddrModeImm8(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
20969 tmp = fieldFromInstruction(insn, 12, 4);
20970 if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
20971 tmp = 0x1000;
20972 tmp |= fieldFromInstruction(insn, 0, 12) << 0;
20973 tmp |= fieldFromInstruction(insn, 16, 4) << 13;
20974 if (!Check(S, DecodeT2AddrModeImm12(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
20977 tmp = fieldFromInstruction(insn, 12, 4);
20978 if (!Check(S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
20979 tmp = fieldFromInstruction(insn, 8, 4);
20980 if (!Check(S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
20981 tmp = fieldFromInstruction(insn, 16, 4);
20982 if (!Check(S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
20983 tmp = fieldFromInstruction(insn, 0, 4);
20984 if (!Check(S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
20985 tmp = fieldFromInstruction(insn, 12, 4);
20986 if (!Check(S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
20987 tmp = fieldFromInstruction(insn, 8, 4);
20988 if (!Check(S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
20991 tmp = fieldFromInstruction(insn, 8, 4);
20992 if (!Check(S, DecodeCoprocessor(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
20993 tmp = fieldFromInstruction(insn, 4, 4);
20994 MI.addOperand(MCOperand::createImm(tmp));
20995 tmp = fieldFromInstruction(insn, 12, 4);
20996 if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
20997 tmp = fieldFromInstruction(insn, 16, 4);
20998 if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
20999 tmp = fieldFromInstruction(insn, 0, 4);
21000 MI.addOperand(MCOperand::createImm(tmp));
21003 tmp = fieldFromInstruction(insn, 12, 4);
21004 if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
21005 tmp = fieldFromInstruction(insn, 16, 4);
21006 if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
21007 tmp = fieldFromInstruction(insn, 8, 4);
21008 if (!Check(S, DecodeCoprocessor(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
21009 tmp = fieldFromInstruction(insn, 4, 4);
21010 MI.addOperand(MCOperand::createImm(tmp));
21011 tmp = fieldFromInstruction(insn, 0, 4);
21012 MI.addOperand(MCOperand::createImm(tmp));
21015 tmp = fieldFromInstruction(insn, 0, 3);
21016 if (!Check(S, DecodetGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
21017 tmp = fieldFromInstruction(insn, 3, 3);
21018 if (!Check(S, DecodetGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
21019 tmp = fieldFromInstruction(insn, 6, 5);
21020 MI.addOperand(MCOperand::createImm(tmp));
21023 tmp = fieldFromInstruction(insn, 0, 3);
21024 if (!Check(S, DecodetGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
21025 tmp = fieldFromInstruction(insn, 3, 3);
21026 if (!Check(S, DecodetGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
21027 tmp = fieldFromInstruction(insn, 6, 3);
21028 if (!Check(S, DecodetGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
21031 tmp = fieldFromInstruction(insn, 0, 3);
21032 if (!Check(S, DecodetGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
21033 tmp = fieldFromInstruction(insn, 3, 3);
21034 if (!Check(S, DecodetGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
21035 tmp = fieldFromInstruction(insn, 6, 3);
21036 MI.addOperand(MCOperand::createImm(tmp));
21039 tmp = fieldFromInstruction(insn, 8, 3);
21040 if (!Check(S, DecodetGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
21041 tmp = fieldFromInstruction(insn, 8, 3);
21042 if (!Check(S, DecodetGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
21043 tmp = fieldFromInstruction(insn, 0, 8);
21044 MI.addOperand(MCOperand::createImm(tmp));
21047 tmp = fieldFromInstruction(insn, 0, 3);
21048 if (!Check(S, DecodetGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
21049 tmp = fieldFromInstruction(insn, 0, 3);
21050 if (!Check(S, DecodetGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
21051 tmp = fieldFromInstruction(insn, 3, 3);
21052 if (!Check(S, DecodetGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
21055 tmp = fieldFromInstruction(insn, 0, 3);
21056 if (!Check(S, DecodetGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
21057 tmp = fieldFromInstruction(insn, 3, 3);
21058 if (!Check(S, DecodetGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
21059 tmp = fieldFromInstruction(insn, 0, 3);
21060 if (!Check(S, DecodetGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
21063 tmp = 0x0;
21064 tmp |= fieldFromInstruction(insn, 12, 4) << 1;
21065 tmp |= fieldFromInstruction(insn, 22, 1) << 0;
21066 if (!Check(S, DecodeHPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
21067 tmp = 0x0;
21068 tmp |= fieldFromInstruction(insn, 0, 8) << 0;
21069 tmp |= fieldFromInstruction(insn, 16, 4) << 9;
21070 tmp |= fieldFromInstruction(insn, 23, 1) << 8;
21071 if (!Check(S, DecodeAddrMode5FP16Operand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
21072 tmp = fieldFromInstruction(insn, 28, 4);
21073 if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
21076 tmp = 0x0;
21077 tmp |= fieldFromInstruction(insn, 12, 4) << 1;
21078 tmp |= fieldFromInstruction(insn, 22, 1) << 0;
21079 if (!Check(S, DecodeHPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
21080 tmp = 0x0;
21081 tmp |= fieldFromInstruction(insn, 12, 4) << 1;
21082 tmp |= fieldFromInstruction(insn, 22, 1) << 0;
21083 if (!Check(S, DecodeHPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
21084 tmp = 0x0;
21085 tmp |= fieldFromInstruction(insn, 7, 1) << 0;
21086 tmp |= fieldFromInstruction(insn, 16, 4) << 1;
21087 if (!Check(S, DecodeHPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
21088 tmp = 0x0;
21089 tmp |= fieldFromInstruction(insn, 0, 4) << 1;
21090 tmp |= fieldFromInstruction(insn, 5, 1) << 0;
21091 if (!Check(S, DecodeHPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
21092 tmp = fieldFromInstruction(insn, 28, 4);
21093 if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
21096 tmp = 0x0;
21097 tmp |= fieldFromInstruction(insn, 12, 4) << 1;
21098 tmp |= fieldFromInstruction(insn, 22, 1) << 0;
21099 if (!Check(S, DecodeHPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
21100 tmp = 0x0;
21101 tmp |= fieldFromInstruction(insn, 7, 1) << 0;
21102 tmp |= fieldFromInstruction(insn, 16, 4) << 1;
21103 if (!Check(S, DecodeHPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
21104 tmp = 0x0;
21105 tmp |= fieldFromInstruction(insn, 0, 4) << 1;
21106 tmp |= fieldFromInstruction(insn, 5, 1) << 0;
21107 if (!Check(S, DecodeHPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
21108 tmp = fieldFromInstruction(insn, 28, 4);
21109 if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
21112 tmp = 0x0;
21113 tmp |= fieldFromInstruction(insn, 7, 1) << 0;
21114 tmp |= fieldFromInstruction(insn, 16, 4) << 1;
21115 if (!Check(S, DecodeHPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
21116 tmp = fieldFromInstruction(insn, 12, 4);
21117 if (!Check(S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
21118 tmp = fieldFromInstruction(insn, 28, 4);
21119 if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
21122 tmp = fieldFromInstruction(insn, 12, 4);
21123 if (!Check(S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
21124 tmp = 0x0;
21125 tmp |= fieldFromInstruction(insn, 7, 1) << 0;
21126 tmp |= fieldFromInstruction(insn, 16, 4) << 1;
21127 if (!Check(S, DecodeHPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
21128 tmp = fieldFromInstruction(insn, 28, 4);
21129 if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
21132 tmp = 0x0;
21133 tmp |= fieldFromInstruction(insn, 12, 4) << 1;
21134 tmp |= fieldFromInstruction(insn, 22, 1) << 0;
21135 if (!Check(S, DecodeHPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
21136 tmp = 0x0;
21137 tmp |= fieldFromInstruction(insn, 0, 4) << 0;
21138 tmp |= fieldFromInstruction(insn, 16, 4) << 4;
21139 MI.addOperand(MCOperand::createImm(tmp));
21140 tmp = fieldFromInstruction(insn, 28, 4);
21141 if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
21144 tmp = 0x0;
21145 tmp |= fieldFromInstruction(insn, 12, 4) << 1;
21146 tmp |= fieldFromInstruction(insn, 22, 1) << 0;
21147 if (!Check(S, DecodeHPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
21148 tmp = 0x0;
21149 tmp |= fieldFromInstruction(insn, 0, 4) << 1;
21150 tmp |= fieldFromInstruction(insn, 5, 1) << 0;
21151 if (!Check(S, DecodeHPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
21152 tmp = fieldFromInstruction(insn, 28, 4);
21153 if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
21156 tmp = 0x0;
21157 tmp |= fieldFromInstruction(insn, 12, 4) << 1;
21158 tmp |= fieldFromInstruction(insn, 22, 1) << 0;
21159 if (!Check(S, DecodeHPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
21160 tmp = fieldFromInstruction(insn, 28, 4);
21161 if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
21164 tmp = 0x0;
21165 tmp |= fieldFromInstruction(insn, 12, 4) << 1;
21166 tmp |= fieldFromInstruction(insn, 22, 1) << 0;
21167 if (!Check(S, DecodeHPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
21168 tmp = 0x0;
21169 tmp |= fieldFromInstruction(insn, 0, 4) << 1;
21170 tmp |= fieldFromInstruction(insn, 5, 1) << 0;
21171 if (!Check(S, DecodeSPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
21172 tmp = fieldFromInstruction(insn, 28, 4);
21173 if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
21176 tmp = 0x0;
21177 tmp |= fieldFromInstruction(insn, 12, 4) << 1;
21178 tmp |= fieldFromInstruction(insn, 22, 1) << 0;
21179 if (!Check(S, DecodeSPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
21180 tmp = 0x0;
21181 tmp |= fieldFromInstruction(insn, 12, 4) << 1;
21182 tmp |= fieldFromInstruction(insn, 22, 1) << 0;
21183 if (!Check(S, DecodeSPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
21184 tmp = 0x0;
21185 tmp |= fieldFromInstruction(insn, 0, 4) << 1;
21186 tmp |= fieldFromInstruction(insn, 5, 1) << 0;
21187 MI.addOperand(MCOperand::createImm(tmp));
21188 tmp = fieldFromInstruction(insn, 28, 4);
21189 if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
21192 tmp = 0x0;
21193 tmp |= fieldFromInstruction(insn, 12, 4) << 1;
21194 tmp |= fieldFromInstruction(insn, 22, 1) << 0;
21195 if (!Check(S, DecodeSPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
21196 tmp = 0x0;
21197 tmp |= fieldFromInstruction(insn, 0, 4) << 1;
21198 tmp |= fieldFromInstruction(insn, 5, 1) << 0;
21199 if (!Check(S, DecodeSPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
21200 tmp = fieldFromInstruction(insn, 28, 4);
21201 if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
21204 tmp = 0x0;
21205 tmp |= fieldFromInstruction(insn, 12, 4) << 1;
21206 tmp |= fieldFromInstruction(insn, 22, 1) << 0;
21207 if (!Check(S, DecodeSPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
21208 tmp = 0x0;
21209 tmp |= fieldFromInstruction(insn, 0, 4) << 1;
21210 tmp |= fieldFromInstruction(insn, 5, 1) << 0;
21211 if (!Check(S, DecodeHPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
21212 tmp = fieldFromInstruction(insn, 28, 4);
21213 if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
21219 tmp = fieldFromInstruction(insn, 16, 4);
21220 if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
21221 tmp = fieldFromInstruction(insn, 28, 4);
21222 if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
21223 tmp = 0x0;
21224 tmp |= fieldFromInstruction(insn, 0, 8) << 0;
21225 tmp |= fieldFromInstruction(insn, 12, 4) << 9;
21226 tmp |= fieldFromInstruction(insn, 22, 1) << 8;
21227 if (!Check(S, DecodeSPRRegListOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
21230 tmp = 0x0;
21231 tmp |= fieldFromInstruction(insn, 12, 4) << 1;
21232 tmp |= fieldFromInstruction(insn, 22, 1) << 0;
21233 if (!Check(S, DecodeSPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
21234 tmp = 0x0;
21235 tmp |= fieldFromInstruction(insn, 0, 8) << 0;
21236 tmp |= fieldFromInstruction(insn, 16, 4) << 9;
21237 tmp |= fieldFromInstruction(insn, 23, 1) << 8;
21238 if (!Check(S, DecodeAddrMode5Operand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
21239 tmp = fieldFromInstruction(insn, 28, 4);
21240 if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
21243 tmp = 0x0;
21244 tmp |= fieldFromInstruction(insn, 12, 4) << 1;
21245 tmp |= fieldFromInstruction(insn, 22, 1) << 0;
21246 if (!Check(S, DecodeSPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
21247 tmp = 0x0;
21248 tmp |= fieldFromInstruction(insn, 12, 4) << 1;
21249 tmp |= fieldFromInstruction(insn, 22, 1) << 0;
21250 if (!Check(S, DecodeSPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
21251 tmp = 0x0;
21252 tmp |= fieldFromInstruction(insn, 7, 1) << 0;
21253 tmp |= fieldFromInstruction(insn, 16, 4) << 1;
21254 if (!Check(S, DecodeSPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
21255 tmp = 0x0;
21256 tmp |= fieldFromInstruction(insn, 0, 4) << 1;
21257 tmp |= fieldFromInstruction(insn, 5, 1) << 0;
21258 if (!Check(S, DecodeSPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
21259 tmp = fieldFromInstruction(insn, 28, 4);
21260 if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
21263 tmp = 0x0;
21264 tmp |= fieldFromInstruction(insn, 12, 4) << 1;
21265 tmp |= fieldFromInstruction(insn, 22, 1) << 0;
21266 if (!Check(S, DecodeSPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
21267 tmp = 0x0;
21268 tmp |= fieldFromInstruction(insn, 7, 1) << 0;
21269 tmp |= fieldFromInstruction(insn, 16, 4) << 1;
21270 if (!Check(S, DecodeSPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
21271 tmp = 0x0;
21272 tmp |= fieldFromInstruction(insn, 0, 4) << 1;
21273 tmp |= fieldFromInstruction(insn, 5, 1) << 0;
21274 if (!Check(S, DecodeSPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
21275 tmp = fieldFromInstruction(insn, 28, 4);
21276 if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
21279 tmp = 0x0;
21280 tmp |= fieldFromInstruction(insn, 7, 1) << 0;
21281 tmp |= fieldFromInstruction(insn, 16, 4) << 1;
21282 if (!Check(S, DecodeSPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
21283 tmp = fieldFromInstruction(insn, 12, 4);
21284 if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
21285 tmp = fieldFromInstruction(insn, 28, 4);
21286 if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
21295 tmp = fieldFromInstruction(insn, 12, 4);
21296 if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
21297 tmp = 0x0;
21298 tmp |= fieldFromInstruction(insn, 7, 1) << 0;
21299 tmp |= fieldFromInstruction(insn, 16, 4) << 1;
21300 if (!Check(S, DecodeSPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
21301 tmp = fieldFromInstruction(insn, 28, 4);
21302 if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
21305 tmp = fieldFromInstruction(insn, 16, 4);
21306 if (!Check(S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
21307 tmp = fieldFromInstruction(insn, 28, 4);
21308 if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
21311 tmp = fieldFromInstruction(insn, 16, 4);
21312 if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
21313 tmp = fieldFromInstruction(insn, 16, 4);
21314 if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
21315 tmp = fieldFromInstruction(insn, 28, 4);
21316 if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
21317 tmp = 0x0;
21318 tmp |= fieldFromInstruction(insn, 0, 8) << 0;
21319 tmp |= fieldFromInstruction(insn, 12, 4) << 9;
21320 tmp |= fieldFromInstruction(insn, 22, 1) << 8;
21321 if (!Check(S, DecodeSPRRegListOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
21327 tmp = 0x0;
21328 tmp |= fieldFromInstruction(insn, 12, 4) << 1;
21329 tmp |= fieldFromInstruction(insn, 22, 1) << 0;
21330 if (!Check(S, DecodeSPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
21331 tmp = 0x0;
21332 tmp |= fieldFromInstruction(insn, 0, 4) << 0;
21333 tmp |= fieldFromInstruction(insn, 16, 4) << 4;
21334 MI.addOperand(MCOperand::createImm(tmp));
21335 tmp = fieldFromInstruction(insn, 28, 4);
21336 if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
21339 tmp = 0x0;
21340 tmp |= fieldFromInstruction(insn, 12, 4) << 1;
21341 tmp |= fieldFromInstruction(insn, 22, 1) << 0;
21342 if (!Check(S, DecodeSPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
21343 tmp = fieldFromInstruction(insn, 28, 4);
21344 if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
21347 tmp = 0x0;
21348 tmp |= fieldFromInstruction(insn, 12, 4) << 0;
21349 tmp |= fieldFromInstruction(insn, 22, 1) << 4;
21350 if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
21351 tmp = 0x0;
21352 tmp |= fieldFromInstruction(insn, 0, 4) << 1;
21353 tmp |= fieldFromInstruction(insn, 5, 1) << 0;
21354 if (!Check(S, DecodeSPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
21355 tmp = fieldFromInstruction(insn, 28, 4);
21356 if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
21359 tmp = 0x0;
21360 tmp |= fieldFromInstruction(insn, 0, 4) << 0;
21361 tmp |= fieldFromInstruction(insn, 5, 1) << 4;
21362 if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
21363 tmp = fieldFromInstruction(insn, 12, 4);
21364 if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
21365 tmp = fieldFromInstruction(insn, 16, 4);
21366 if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
21367 tmp = fieldFromInstruction(insn, 28, 4);
21368 if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
21371 tmp = fieldFromInstruction(insn, 16, 4);
21372 if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
21373 tmp = fieldFromInstruction(insn, 28, 4);
21374 if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
21375 tmp = 0x0;
21376 tmp |= fieldFromInstruction(insn, 1, 7) << 1;
21377 tmp |= fieldFromInstruction(insn, 12, 4) << 8;
21378 tmp |= fieldFromInstruction(insn, 22, 1) << 12;
21379 if (!Check(S, DecodeDPRRegListOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
21382 tmp = fieldFromInstruction(insn, 16, 4);
21383 if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
21384 tmp = fieldFromInstruction(insn, 28, 4);
21385 if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
21386 tmp = 0x0;
21387 tmp |= fieldFromInstruction(insn, 1, 7) << 1;
21388 tmp |= fieldFromInstruction(insn, 12, 4) << 8;
21389 if (!Check(S, DecodeDPRRegListOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
21392 tmp = 0x0;
21393 tmp |= fieldFromInstruction(insn, 12, 4) << 0;
21394 tmp |= fieldFromInstruction(insn, 22, 1) << 4;
21395 if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
21396 tmp = 0x0;
21397 tmp |= fieldFromInstruction(insn, 0, 8) << 0;
21398 tmp |= fieldFromInstruction(insn, 16, 4) << 9;
21399 tmp |= fieldFromInstruction(insn, 23, 1) << 8;
21400 if (!Check(S, DecodeAddrMode5Operand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
21401 tmp = fieldFromInstruction(insn, 28, 4);
21402 if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
21405 tmp = 0x0;
21406 tmp |= fieldFromInstruction(insn, 12, 4) << 0;
21407 tmp |= fieldFromInstruction(insn, 22, 1) << 4;
21408 if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
21409 tmp = 0x0;
21410 tmp |= fieldFromInstruction(insn, 12, 4) << 0;
21411 tmp |= fieldFromInstruction(insn, 22, 1) << 4;
21412 if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
21413 tmp = 0x0;
21414 tmp |= fieldFromInstruction(insn, 7, 1) << 4;
21415 tmp |= fieldFromInstruction(insn, 16, 4) << 0;
21416 if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
21417 tmp = 0x0;
21418 tmp |= fieldFromInstruction(insn, 0, 4) << 0;
21419 tmp |= fieldFromInstruction(insn, 5, 1) << 4;
21420 if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
21421 tmp = fieldFromInstruction(insn, 28, 4);
21422 if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
21425 tmp = 0x0;
21426 tmp |= fieldFromInstruction(insn, 12, 4) << 0;
21427 tmp |= fieldFromInstruction(insn, 22, 1) << 4;
21428 if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
21429 tmp = 0x0;
21430 tmp |= fieldFromInstruction(insn, 7, 1) << 4;
21431 tmp |= fieldFromInstruction(insn, 16, 4) << 0;
21432 if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
21433 tmp = 0x0;
21434 tmp |= fieldFromInstruction(insn, 0, 4) << 0;
21435 tmp |= fieldFromInstruction(insn, 5, 1) << 4;
21436 if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
21437 tmp = fieldFromInstruction(insn, 28, 4);
21438 if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
21441 tmp = fieldFromInstruction(insn, 12, 4);
21442 if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
21443 tmp = fieldFromInstruction(insn, 16, 4);
21444 if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
21445 tmp = 0x0;
21446 tmp |= fieldFromInstruction(insn, 0, 4) << 0;
21447 tmp |= fieldFromInstruction(insn, 5, 1) << 4;
21448 if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
21449 tmp = fieldFromInstruction(insn, 28, 4);
21450 if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
21453 tmp = fieldFromInstruction(insn, 16, 4);
21454 if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
21455 tmp = fieldFromInstruction(insn, 16, 4);
21456 if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
21457 tmp = fieldFromInstruction(insn, 28, 4);
21458 if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
21459 tmp = 0x0;
21460 tmp |= fieldFromInstruction(insn, 1, 7) << 1;
21461 tmp |= fieldFromInstruction(insn, 12, 4) << 8;
21462 tmp |= fieldFromInstruction(insn, 22, 1) << 12;
21463 if (!Check(S, DecodeDPRRegListOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
21466 tmp = fieldFromInstruction(insn, 16, 4);
21467 if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
21468 tmp = fieldFromInstruction(insn, 16, 4);
21469 if (!Check(S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
21470 tmp = fieldFromInstruction(insn, 28, 4);
21471 if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
21472 tmp = 0x0;
21473 tmp |= fieldFromInstruction(insn, 1, 7) << 1;
21474 tmp |= fieldFromInstruction(insn, 12, 4) << 8;
21475 if (!Check(S, DecodeDPRRegListOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
21478 tmp = 0x0;
21479 tmp |= fieldFromInstruction(insn, 12, 4) << 0;
21480 tmp |= fieldFromInstruction(insn, 22, 1) << 4;
21481 if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
21482 tmp = 0x0;
21483 tmp |= fieldFromInstruction(insn, 0, 4) << 0;
21484 tmp |= fieldFromInstruction(insn, 16, 4) << 4;
21485 MI.addOperand(MCOperand::createImm(tmp));
21486 tmp = fieldFromInstruction(insn, 28, 4);
21487 if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
21490 tmp = 0x0;
21491 tmp |= fieldFromInstruction(insn, 12, 4) << 0;
21492 tmp |= fieldFromInstruction(insn, 22, 1) << 4;
21493 if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
21494 tmp = 0x0;
21495 tmp |= fieldFromInstruction(insn, 0, 4) << 0;
21496 tmp |= fieldFromInstruction(insn, 5, 1) << 4;
21497 if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
21498 tmp = fieldFromInstruction(insn, 28, 4);
21499 if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
21502 tmp = 0x0;
21503 tmp |= fieldFromInstruction(insn, 12, 4) << 1;
21504 tmp |= fieldFromInstruction(insn, 22, 1) << 0;
21505 if (!Check(S, DecodeSPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
21506 tmp = 0x0;
21507 tmp |= fieldFromInstruction(insn, 0, 4) << 0;
21508 tmp |= fieldFromInstruction(insn, 5, 1) << 4;
21509 if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
21510 tmp = fieldFromInstruction(insn, 28, 4);
21511 if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
21514 tmp = 0x0;
21515 tmp |= fieldFromInstruction(insn, 12, 4) << 0;
21516 tmp |= fieldFromInstruction(insn, 22, 1) << 4;
21517 if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
21518 tmp = fieldFromInstruction(insn, 28, 4);
21519 if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
21522 tmp = 0x0;
21523 tmp |= fieldFromInstruction(insn, 12, 4) << 0;
21524 tmp |= fieldFromInstruction(insn, 22, 1) << 4;
21525 if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
21526 tmp = 0x0;
21527 tmp |= fieldFromInstruction(insn, 12, 4) << 0;
21528 tmp |= fieldFromInstruction(insn, 22, 1) << 4;
21529 if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
21530 tmp = 0x0;
21531 tmp |= fieldFromInstruction(insn, 0, 4) << 1;
21532 tmp |= fieldFromInstruction(insn, 5, 1) << 0;
21533 MI.addOperand(MCOperand::createImm(tmp));
21534 tmp = fieldFromInstruction(insn, 28, 4);
21535 if (!Check(S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
21544 tmp = 0x0;
21545 tmp |= fieldFromInstruction(insn, 12, 4) << 0;
21546 tmp |= fieldFromInstruction(insn, 22, 1) << 4;
21547 if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
21548 tmp = 0x0;
21549 tmp |= fieldFromInstruction(insn, 7, 1) << 4;
21550 tmp |= fieldFromInstruction(insn, 16, 4) << 0;
21551 if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
21552 tmp = 0x0;
21553 tmp |= fieldFromInstruction(insn, 0, 4) << 0;
21554 tmp |= fieldFromInstruction(insn, 5, 1) << 4;
21555 if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
21556 tmp = fieldFromInstruction(insn, 24, 1);
21557 MI.addOperand(MCOperand::createImm(tmp));
21560 tmp = 0x0;
21561 tmp |= fieldFromInstruction(insn, 12, 4) << 0;
21562 tmp |= fieldFromInstruction(insn, 22, 1) << 4;
21563 if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
21564 tmp = 0x0;
21565 tmp |= fieldFromInstruction(insn, 12, 4) << 0;
21566 tmp |= fieldFromInstruction(insn, 22, 1) << 4;
21567 if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
21568 tmp = 0x0;
21569 tmp |= fieldFromInstruction(insn, 7, 1) << 4;
21570 tmp |= fieldFromInstruction(insn, 16, 4) << 0;
21571 if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
21572 tmp = 0x0;
21573 tmp |= fieldFromInstruction(insn, 0, 4) << 0;
21574 tmp |= fieldFromInstruction(insn, 5, 1) << 4;
21575 if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
21576 tmp = fieldFromInstruction(insn, 23, 2);
21577 MI.addOperand(MCOperand::createImm(tmp));
21580 tmp = 0x0;
21581 tmp |= fieldFromInstruction(insn, 12, 4) << 0;
21582 tmp |= fieldFromInstruction(insn, 22, 1) << 4;
21583 if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
21584 tmp = 0x0;
21585 tmp |= fieldFromInstruction(insn, 12, 4) << 0;
21586 tmp |= fieldFromInstruction(insn, 22, 1) << 4;
21587 if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
21588 tmp = 0x0;
21589 tmp |= fieldFromInstruction(insn, 7, 1) << 4;
21590 tmp |= fieldFromInstruction(insn, 16, 4) << 0;
21591 if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
21592 tmp = fieldFromInstruction(insn, 0, 4);
21593 if (!Check(S, DecodeDPR_VFP2RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
21594 tmp = fieldFromInstruction(insn, 5, 1);
21595 MI.addOperand(MCOperand::createImm(tmp));
21596 tmp = fieldFromInstruction(insn, 20, 2);
21597 MI.addOperand(MCOperand::createImm(tmp));
21603 tmp = 0x0;
21604 tmp |= fieldFromInstruction(insn, 12, 4) << 0;
21605 tmp |= fieldFromInstruction(insn, 22, 1) << 4;
21606 if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
21607 tmp = 0x0;
21608 tmp |= fieldFromInstruction(insn, 7, 1) << 4;
21609 tmp |= fieldFromInstruction(insn, 16, 4) << 0;
21610 if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
21611 tmp = 0x0;
21612 tmp |= fieldFromInstruction(insn, 0, 4) << 0;
21613 tmp |= fieldFromInstruction(insn, 5, 1) << 4;
21614 if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
21615 tmp = fieldFromInstruction(insn, 24, 1);
21616 MI.addOperand(MCOperand::createImm(tmp));
21619 tmp = 0x0;
21620 tmp |= fieldFromInstruction(insn, 12, 4) << 0;
21621 tmp |= fieldFromInstruction(insn, 22, 1) << 4;
21622 if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
21623 tmp = 0x0;
21624 tmp |= fieldFromInstruction(insn, 12, 4) << 0;
21625 tmp |= fieldFromInstruction(insn, 22, 1) << 4;
21626 if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
21627 tmp = 0x0;
21628 tmp |= fieldFromInstruction(insn, 7, 1) << 4;
21629 tmp |= fieldFromInstruction(insn, 16, 4) << 0;
21630 if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
21631 tmp = 0x0;
21632 tmp |= fieldFromInstruction(insn, 0, 4) << 0;
21633 tmp |= fieldFromInstruction(insn, 5, 1) << 4;
21634 if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
21635 tmp = fieldFromInstruction(insn, 23, 2);
21636 MI.addOperand(MCOperand::createImm(tmp));
21639 tmp = 0x0;
21640 tmp |= fieldFromInstruction(insn, 12, 4) << 0;
21641 tmp |= fieldFromInstruction(insn, 22, 1) << 4;
21642 if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
21643 tmp = 0x0;
21644 tmp |= fieldFromInstruction(insn, 12, 4) << 0;
21645 tmp |= fieldFromInstruction(insn, 22, 1) << 4;
21646 if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
21647 tmp = 0x0;
21648 tmp |= fieldFromInstruction(insn, 7, 1) << 4;
21649 tmp |= fieldFromInstruction(insn, 16, 4) << 0;
21650 if (!Check(S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
21651 tmp = fieldFromInstruction(insn, 0, 4);
21652 if (!Check(S, DecodeDPR_VFP2RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
21653 tmp = fieldFromInstruction(insn, 5, 1);
21654 MI.addOperand(MCOperand::createImm(tmp));
21655 tmp = fieldFromInstruction(insn, 20, 2);
21656 MI.addOperand(MCOperand::createImm(tmp));
21659 tmp = 0x0;
21660 tmp |= fieldFromInstruction(insn, 12, 4) << 0;
21661 tmp |= fieldFromInstruction(insn, 22, 1) << 4;
21662 if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
21663 tmp = 0x0;
21664 tmp |= fieldFromInstruction(insn, 7, 1) << 0;
21665 tmp |= fieldFromInstruction(insn, 16, 4) << 1;
21666 if (!Check(S, DecodeSPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
21667 tmp = 0x0;
21668 tmp |= fieldFromInstruction(insn, 0, 3) << 1;
21669 tmp |= fieldFromInstruction(insn, 5, 1) << 0;
21670 if (!Check(S, DecodeSPR_8RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
21671 tmp = fieldFromInstruction(insn, 3, 1);
21672 MI.addOperand(MCOperand::createImm(tmp));
21675 tmp = 0x0;
21676 tmp |= fieldFromInstruction(insn, 12, 4) << 0;
21677 tmp |= fieldFromInstruction(insn, 22, 1) << 4;
21678 if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
21679 tmp = 0x0;
21680 tmp |= fieldFromInstruction(insn, 7, 1) << 0;
21681 tmp |= fieldFromInstruction(insn, 16, 4) << 1;
21682 if (!Check(S, DecodeSPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
21683 tmp = 0x0;
21684 tmp |= fieldFromInstruction(insn, 0, 4) << 1;
21685 tmp |= fieldFromInstruction(insn, 5, 1) << 0;
21686 if (!Check(S, DecodeSPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
21689 tmp = 0x0;
21690 tmp |= fieldFromInstruction(insn, 12, 4) << 1;
21691 tmp |= fieldFromInstruction(insn, 22, 1) << 0;
21692 if (!Check(S, DecodeHPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
21693 tmp = 0x0;
21694 tmp |= fieldFromInstruction(insn, 7, 1) << 0;
21695 tmp |= fieldFromInstruction(insn, 16, 4) << 1;
21696 if (!Check(S, DecodeHPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
21697 tmp = 0x0;
21698 tmp |= fieldFromInstruction(insn, 0, 4) << 1;
21699 tmp |= fieldFromInstruction(insn, 5, 1) << 0;
21700 if (!Check(S, DecodeHPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
21703 tmp = 0x0;
21704 tmp |= fieldFromInstruction(insn, 12, 4) << 1;
21705 tmp |= fieldFromInstruction(insn, 22, 1) << 0;
21706 if (!Check(S, DecodeHPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
21707 tmp = 0x0;
21708 tmp |= fieldFromInstruction(insn, 0, 4) << 1;
21709 tmp |= fieldFromInstruction(insn, 5, 1) << 0;
21710 if (!Check(S, DecodeHPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
21713 tmp = 0x0;
21714 tmp |= fieldFromInstruction(insn, 12, 4) << 1;
21715 tmp |= fieldFromInstruction(insn, 22, 1) << 0;
21716 if (!Check(S, DecodeSPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
21717 tmp = 0x0;
21718 tmp |= fieldFromInstruction(insn, 0, 4) << 1;
21719 tmp |= fieldFromInstruction(insn, 5, 1) << 0;
21720 if (!Check(S, DecodeHPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
21723 tmp = 0x0;
21724 tmp |= fieldFromInstruction(insn, 12, 4) << 1;
21725 tmp |= fieldFromInstruction(insn, 22, 1) << 0;
21726 if (!Check(S, DecodeSPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
21727 tmp = 0x0;
21728 tmp |= fieldFromInstruction(insn, 7, 1) << 0;
21729 tmp |= fieldFromInstruction(insn, 16, 4) << 1;
21730 if (!Check(S, DecodeSPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
21731 tmp = 0x0;
21732 tmp |= fieldFromInstruction(insn, 0, 4) << 1;
21733 tmp |= fieldFromInstruction(insn, 5, 1) << 0;
21734 if (!Check(S, DecodeSPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
21737 tmp = 0x0;
21738 tmp |= fieldFromInstruction(insn, 12, 4) << 1;
21739 tmp |= fieldFromInstruction(insn, 22, 1) << 0;
21740 if (!Check(S, DecodeSPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
21741 tmp = 0x0;
21742 tmp |= fieldFromInstruction(insn, 0, 4) << 1;
21743 tmp |= fieldFromInstruction(insn, 5, 1) << 0;
21744 if (!Check(S, DecodeSPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
21747 tmp = 0x0;
21748 tmp |= fieldFromInstruction(insn, 12, 4) << 1;
21749 tmp |= fieldFromInstruction(insn, 22, 1) << 0;
21750 if (!Check(S, DecodeSPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
21751 tmp = 0x0;
21752 tmp |= fieldFromInstruction(insn, 0, 4) << 0;
21753 tmp |= fieldFromInstruction(insn, 5, 1) << 4;
21754 if (!Check(S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }