reference, declaration → definition definition → references, declarations, derived classes, virtual overrides reference to multiple definitions → definitions unreferenced |
9077 default: OpKind = InvalidMatchClass; break; 9078 case ARM::R0: OpKind = MCK_Reg11; break; 9079 case ARM::R1: OpKind = MCK_Reg15; break; 9080 case ARM::R2: OpKind = MCK_Reg11; break; 9081 case ARM::R3: OpKind = MCK_Reg15; break; 9082 case ARM::R4: OpKind = MCK_Reg12; break; 9083 case ARM::R5: OpKind = MCK_Reg16; break; 9084 case ARM::R6: OpKind = MCK_Reg12; break; 9085 case ARM::R7: OpKind = MCK_Reg16; break; 9086 case ARM::R8: OpKind = MCK_Reg21; break; 9087 case ARM::R9: OpKind = MCK_Reg22; break; 9088 case ARM::R10: OpKind = MCK_Reg21; break; 9089 case ARM::R11: OpKind = MCK_Reg22; break; 9090 case ARM::R12: OpKind = MCK_Reg23; break; 9091 case ARM::SP: OpKind = MCK_GPRsp; break; 9092 case ARM::LR: OpKind = MCK_GPRlr; break; 9093 case ARM::PC: OpKind = MCK_PC; break; 9094 case ARM::S0: OpKind = MCK_SPR_8; break; 9095 case ARM::S1: OpKind = MCK_SPR_8; break; 9096 case ARM::S2: OpKind = MCK_SPR_8; break; 9097 case ARM::S3: OpKind = MCK_SPR_8; break; 9098 case ARM::S4: OpKind = MCK_SPR_8; break; 9099 case ARM::S5: OpKind = MCK_SPR_8; break; 9100 case ARM::S6: OpKind = MCK_SPR_8; break; 9101 case ARM::S7: OpKind = MCK_SPR_8; break; 9102 case ARM::S8: OpKind = MCK_SPR_8; break; 9103 case ARM::S9: OpKind = MCK_SPR_8; break; 9104 case ARM::S10: OpKind = MCK_SPR_8; break; 9105 case ARM::S11: OpKind = MCK_SPR_8; break; 9106 case ARM::S12: OpKind = MCK_SPR_8; break; 9107 case ARM::S13: OpKind = MCK_SPR_8; break; 9108 case ARM::S14: OpKind = MCK_SPR_8; break; 9109 case ARM::S15: OpKind = MCK_SPR_8; break; 9110 case ARM::S16: OpKind = MCK_HPR; break; 9111 case ARM::S17: OpKind = MCK_HPR; break; 9112 case ARM::S18: OpKind = MCK_HPR; break; 9113 case ARM::S19: OpKind = MCK_HPR; break; 9114 case ARM::S20: OpKind = MCK_HPR; break; 9115 case ARM::S21: OpKind = MCK_HPR; break; 9116 case ARM::S22: OpKind = MCK_HPR; break; 9117 case ARM::S23: OpKind = MCK_HPR; break; 9118 case ARM::S24: OpKind = MCK_HPR; break; 9119 case ARM::S25: OpKind = MCK_HPR; break; 9120 case ARM::S26: OpKind = MCK_HPR; break; 9121 case ARM::S27: OpKind = MCK_HPR; break; 9122 case ARM::S28: OpKind = MCK_HPR; break; 9123 case ARM::S29: OpKind = MCK_HPR; break; 9124 case ARM::S30: OpKind = MCK_HPR; break; 9125 case ARM::S31: OpKind = MCK_HPR; break; 9126 case ARM::D0: OpKind = MCK_DPR_8; break; 9127 case ARM::D1: OpKind = MCK_DPR_8; break; 9128 case ARM::D2: OpKind = MCK_DPR_8; break; 9129 case ARM::D3: OpKind = MCK_DPR_8; break; 9130 case ARM::D4: OpKind = MCK_DPR_8; break; 9131 case ARM::D5: OpKind = MCK_DPR_8; break; 9132 case ARM::D6: OpKind = MCK_DPR_8; break; 9133 case ARM::D7: OpKind = MCK_DPR_8; break; 9134 case ARM::D8: OpKind = MCK_DPR_VFP2; break; 9135 case ARM::D9: OpKind = MCK_DPR_VFP2; break; 9136 case ARM::D10: OpKind = MCK_DPR_VFP2; break; 9137 case ARM::D11: OpKind = MCK_DPR_VFP2; break; 9138 case ARM::D12: OpKind = MCK_DPR_VFP2; break; 9139 case ARM::D13: OpKind = MCK_DPR_VFP2; break; 9140 case ARM::D14: OpKind = MCK_DPR_VFP2; break; 9141 case ARM::D15: OpKind = MCK_DPR_VFP2; break; 9142 case ARM::D16: OpKind = MCK_DPR; break; 9143 case ARM::D17: OpKind = MCK_DPR; break; 9144 case ARM::D18: OpKind = MCK_DPR; break; 9145 case ARM::D19: OpKind = MCK_DPR; break; 9146 case ARM::D20: OpKind = MCK_DPR; break; 9147 case ARM::D21: OpKind = MCK_DPR; break; 9148 case ARM::D22: OpKind = MCK_DPR; break; 9149 case ARM::D23: OpKind = MCK_DPR; break; 9150 case ARM::D24: OpKind = MCK_DPR; break; 9151 case ARM::D25: OpKind = MCK_DPR; break; 9152 case ARM::D26: OpKind = MCK_DPR; break; 9153 case ARM::D27: OpKind = MCK_DPR; break; 9154 case ARM::D28: OpKind = MCK_DPR; break; 9155 case ARM::D29: OpKind = MCK_DPR; break; 9156 case ARM::D30: OpKind = MCK_DPR; break; 9157 case ARM::D31: OpKind = MCK_DPR; break; 9158 case ARM::Q0: OpKind = MCK_QPR_8; break; 9159 case ARM::Q1: OpKind = MCK_QPR_8; break; 9160 case ARM::Q2: OpKind = MCK_QPR_8; break; 9161 case ARM::Q3: OpKind = MCK_QPR_8; break; 9162 case ARM::Q4: OpKind = MCK_MQPR; break; 9163 case ARM::Q5: OpKind = MCK_MQPR; break; 9164 case ARM::Q6: OpKind = MCK_MQPR; break; 9165 case ARM::Q7: OpKind = MCK_MQPR; break; 9166 case ARM::Q8: OpKind = MCK_QPR; break; 9167 case ARM::Q9: OpKind = MCK_QPR; break; 9168 case ARM::Q10: OpKind = MCK_QPR; break; 9169 case ARM::Q11: OpKind = MCK_QPR; break; 9170 case ARM::Q12: OpKind = MCK_QPR; break; 9171 case ARM::Q13: OpKind = MCK_QPR; break; 9172 case ARM::Q14: OpKind = MCK_QPR; break; 9173 case ARM::Q15: OpKind = MCK_QPR; break; 9174 case ARM::CPSR: OpKind = MCK_CCR; break; 9175 case ARM::APSR: OpKind = MCK_APSR; break; 9176 case ARM::APSR_NZCV: OpKind = MCK_APSR_NZCV; break; 9177 case ARM::SPSR: OpKind = MCK_SPSR; break; 9178 case ARM::FPSCR: OpKind = MCK_FPSCR; break; 9179 case ARM::FPSCR_NZCV: OpKind = MCK_cl_FPSCR_NZCV; break; 9180 case ARM::FPSID: OpKind = MCK_FPSID; break; 9181 case ARM::MVFR2: OpKind = MCK_MVFR2; break; 9182 case ARM::MVFR1: OpKind = MCK_MVFR1; break; 9183 case ARM::MVFR0: OpKind = MCK_MVFR0; break; 9184 case ARM::FPEXC: OpKind = MCK_FPEXC; break; 9185 case ARM::FPINST: OpKind = MCK_FPINST; break; 9186 case ARM::FPINST2: OpKind = MCK_FPINST2; break; 9187 case ARM::VPR: OpKind = MCK_VCCR; break; 9188 case ARM::FPSCR_NZCVQC: OpKind = MCK_FPSCR_NZCVQC; break; 9189 case ARM::P0: OpKind = MCK_P0; break; 9190 case ARM::FPCXTNS: OpKind = MCK_FPCXTNS; break; 9191 case ARM::FPCXTS: OpKind = MCK_FPCXTS; break; 9192 case ARM::ZR: OpKind = MCK_GPRwithZRnosp; break; 9193 case ARM::D0_D2: OpKind = MCK_Reg59; break; 9194 case ARM::D1_D3: OpKind = MCK_Reg59; break; 9195 case ARM::D2_D4: OpKind = MCK_Reg59; break; 9196 case ARM::D3_D5: OpKind = MCK_Reg59; break; 9197 case ARM::D4_D6: OpKind = MCK_Reg59; break; 9198 case ARM::D5_D7: OpKind = MCK_Reg59; break; 9199 case ARM::D6_D8: OpKind = MCK_Reg60; break; 9200 case ARM::D7_D9: OpKind = MCK_Reg60; break; 9201 case ARM::D8_D10: OpKind = MCK_Reg61; break; 9202 case ARM::D9_D11: OpKind = MCK_Reg61; break; 9203 case ARM::D10_D12: OpKind = MCK_Reg61; break; 9204 case ARM::D11_D13: OpKind = MCK_Reg61; break; 9205 case ARM::D12_D14: OpKind = MCK_Reg61; break; 9206 case ARM::D13_D15: OpKind = MCK_Reg61; break; 9207 case ARM::D14_D16: OpKind = MCK_Reg62; break; 9208 case ARM::D15_D17: OpKind = MCK_Reg62; break; 9209 case ARM::D16_D18: OpKind = MCK_DPairSpc; break; 9210 case ARM::D17_D19: OpKind = MCK_DPairSpc; break; 9211 case ARM::D18_D20: OpKind = MCK_DPairSpc; break; 9212 case ARM::D19_D21: OpKind = MCK_DPairSpc; break; 9213 case ARM::D20_D22: OpKind = MCK_DPairSpc; break; 9214 case ARM::D21_D23: OpKind = MCK_DPairSpc; break; 9215 case ARM::D22_D24: OpKind = MCK_DPairSpc; break; 9216 case ARM::D23_D25: OpKind = MCK_DPairSpc; break; 9217 case ARM::D24_D26: OpKind = MCK_DPairSpc; break; 9218 case ARM::D25_D27: OpKind = MCK_DPairSpc; break; 9219 case ARM::D26_D28: OpKind = MCK_DPairSpc; break; 9220 case ARM::D27_D29: OpKind = MCK_DPairSpc; break; 9221 case ARM::D28_D30: OpKind = MCK_DPairSpc; break; 9222 case ARM::D29_D31: OpKind = MCK_DPairSpc; break; 9223 case ARM::Q0_Q1: OpKind = MCK_Reg64; break; 9224 case ARM::Q1_Q2: OpKind = MCK_Reg64; break; 9225 case ARM::Q2_Q3: OpKind = MCK_Reg64; break; 9226 case ARM::Q3_Q4: OpKind = MCK_Reg65; break; 9227 case ARM::Q4_Q5: OpKind = MCK_Reg66; break; 9228 case ARM::Q5_Q6: OpKind = MCK_Reg66; break; 9229 case ARM::Q6_Q7: OpKind = MCK_Reg66; break; 9230 case ARM::Q7_Q8: OpKind = MCK_Reg67; break; 9231 case ARM::Q8_Q9: OpKind = MCK_QQPR; break; 9232 case ARM::Q9_Q10: OpKind = MCK_QQPR; break; 9233 case ARM::Q10_Q11: OpKind = MCK_QQPR; break; 9234 case ARM::Q11_Q12: OpKind = MCK_QQPR; break; 9235 case ARM::Q12_Q13: OpKind = MCK_QQPR; break; 9236 case ARM::Q13_Q14: OpKind = MCK_QQPR; break; 9237 case ARM::Q14_Q15: OpKind = MCK_QQPR; break; 9238 case ARM::Q0_Q1_Q2_Q3: OpKind = MCK_Reg78; break; 9239 case ARM::Q1_Q2_Q3_Q4: OpKind = MCK_Reg79; break; 9240 case ARM::Q2_Q3_Q4_Q5: OpKind = MCK_Reg80; break; 9241 case ARM::Q3_Q4_Q5_Q6: OpKind = MCK_Reg81; break; 9242 case ARM::Q4_Q5_Q6_Q7: OpKind = MCK_Reg82; break; 9243 case ARM::Q5_Q6_Q7_Q8: OpKind = MCK_Reg83; break; 9244 case ARM::Q6_Q7_Q8_Q9: OpKind = MCK_Reg84; break; 9245 case ARM::Q7_Q8_Q9_Q10: OpKind = MCK_Reg85; break; 9246 case ARM::Q8_Q9_Q10_Q11: OpKind = MCK_QQQQPR; break; 9247 case ARM::Q9_Q10_Q11_Q12: OpKind = MCK_QQQQPR; break; 9248 case ARM::Q10_Q11_Q12_Q13: OpKind = MCK_QQQQPR; break; 9249 case ARM::Q11_Q12_Q13_Q14: OpKind = MCK_QQQQPR; break; 9250 case ARM::Q12_Q13_Q14_Q15: OpKind = MCK_QQQQPR; break; 9251 case ARM::R0_R1: OpKind = MCK_Reg87; break; 9252 case ARM::R2_R3: OpKind = MCK_Reg87; break; 9253 case ARM::R4_R5: OpKind = MCK_Reg88; break; 9254 case ARM::R6_R7: OpKind = MCK_Reg88; break; 9255 case ARM::R8_R9: OpKind = MCK_Reg92; break; 9256 case ARM::R10_R11: OpKind = MCK_Reg92; break; 9257 case ARM::R12_SP: OpKind = MCK_Reg94; break; 9258 case ARM::D0_D1_D2: OpKind = MCK_Reg102; break; 9259 case ARM::D1_D2_D3: OpKind = MCK_Reg107; break; 9260 case ARM::D2_D3_D4: OpKind = MCK_Reg102; break; 9261 case ARM::D3_D4_D5: OpKind = MCK_Reg107; break; 9262 case ARM::D4_D5_D6: OpKind = MCK_Reg102; break; 9263 case ARM::D5_D6_D7: OpKind = MCK_Reg107; break; 9264 case ARM::D6_D7_D8: OpKind = MCK_Reg103; break; 9265 case ARM::D7_D8_D9: OpKind = MCK_Reg108; break; 9266 case ARM::D8_D9_D10: OpKind = MCK_Reg104; break; 9267 case ARM::D9_D10_D11: OpKind = MCK_Reg109; break; 9268 case ARM::D10_D11_D12: OpKind = MCK_Reg104; break; 9269 case ARM::D11_D12_D13: OpKind = MCK_Reg109; break; 9270 case ARM::D12_D13_D14: OpKind = MCK_Reg104; break; 9271 case ARM::D13_D14_D15: OpKind = MCK_Reg109; break; 9272 case ARM::D14_D15_D16: OpKind = MCK_Reg105; break; 9273 case ARM::D15_D16_D17: OpKind = MCK_Reg110; break; 9274 case ARM::D16_D17_D18: OpKind = MCK_Reg106; break; 9275 case ARM::D17_D18_D19: OpKind = MCK_Reg111; break; 9276 case ARM::D18_D19_D20: OpKind = MCK_Reg106; break; 9277 case ARM::D19_D20_D21: OpKind = MCK_Reg111; break; 9278 case ARM::D20_D21_D22: OpKind = MCK_Reg106; break; 9279 case ARM::D21_D22_D23: OpKind = MCK_Reg111; break; 9280 case ARM::D22_D23_D24: OpKind = MCK_Reg106; break; 9281 case ARM::D23_D24_D25: OpKind = MCK_Reg111; break; 9282 case ARM::D24_D25_D26: OpKind = MCK_Reg106; break; 9283 case ARM::D25_D26_D27: OpKind = MCK_Reg111; break; 9284 case ARM::D26_D27_D28: OpKind = MCK_Reg106; break; 9285 case ARM::D27_D28_D29: OpKind = MCK_Reg111; break; 9286 case ARM::D28_D29_D30: OpKind = MCK_Reg106; break; 9287 case ARM::D29_D30_D31: OpKind = MCK_Reg111; break; 9288 case ARM::D0_D2_D4: OpKind = MCK_Reg112; break; 9289 case ARM::D1_D3_D5: OpKind = MCK_Reg112; break; 9290 case ARM::D2_D4_D6: OpKind = MCK_Reg112; break; 9291 case ARM::D3_D5_D7: OpKind = MCK_Reg112; break; 9292 case ARM::D4_D6_D8: OpKind = MCK_Reg113; break; 9293 case ARM::D5_D7_D9: OpKind = MCK_Reg113; break; 9294 case ARM::D6_D8_D10: OpKind = MCK_Reg114; break; 9295 case ARM::D7_D9_D11: OpKind = MCK_Reg114; break; 9296 case ARM::D8_D10_D12: OpKind = MCK_Reg115; break; 9297 case ARM::D9_D11_D13: OpKind = MCK_Reg115; break; 9298 case ARM::D10_D12_D14: OpKind = MCK_Reg115; break; 9299 case ARM::D11_D13_D15: OpKind = MCK_Reg115; break; 9300 case ARM::D12_D14_D16: OpKind = MCK_Reg116; break; 9301 case ARM::D13_D15_D17: OpKind = MCK_Reg116; break; 9302 case ARM::D14_D16_D18: OpKind = MCK_Reg117; break; 9303 case ARM::D15_D17_D19: OpKind = MCK_Reg117; break; 9304 case ARM::D16_D18_D20: OpKind = MCK_DTripleSpc; break; 9305 case ARM::D17_D19_D21: OpKind = MCK_DTripleSpc; break; 9306 case ARM::D18_D20_D22: OpKind = MCK_DTripleSpc; break; 9307 case ARM::D19_D21_D23: OpKind = MCK_DTripleSpc; break; 9308 case ARM::D20_D22_D24: OpKind = MCK_DTripleSpc; break; 9309 case ARM::D21_D23_D25: OpKind = MCK_DTripleSpc; break; 9310 case ARM::D22_D24_D26: OpKind = MCK_DTripleSpc; break; 9311 case ARM::D23_D25_D27: OpKind = MCK_DTripleSpc; break; 9312 case ARM::D24_D26_D28: OpKind = MCK_DTripleSpc; break; 9313 case ARM::D25_D27_D29: OpKind = MCK_DTripleSpc; break; 9314 case ARM::D26_D28_D30: OpKind = MCK_DTripleSpc; break; 9315 case ARM::D27_D29_D31: OpKind = MCK_DTripleSpc; break; 9316 case ARM::D1_D2: OpKind = MCK_Reg39; break; 9317 case ARM::D3_D4: OpKind = MCK_Reg39; break; 9318 case ARM::D5_D6: OpKind = MCK_Reg39; break; 9319 case ARM::D7_D8: OpKind = MCK_Reg40; break; 9320 case ARM::D9_D10: OpKind = MCK_Reg37; break; 9321 case ARM::D11_D12: OpKind = MCK_Reg37; break; 9322 case ARM::D13_D14: OpKind = MCK_Reg37; break; 9323 case ARM::D15_D16: OpKind = MCK_Reg38; break; 9324 case ARM::D17_D18: OpKind = MCK_DPair; break; 9325 case ARM::D19_D20: OpKind = MCK_DPair; break; 9326 case ARM::D21_D22: OpKind = MCK_DPair; break; 9327 case ARM::D23_D24: OpKind = MCK_DPair; break; 9328 case ARM::D25_D26: OpKind = MCK_DPair; break; 9329 case ARM::D27_D28: OpKind = MCK_DPair; break; 9330 case ARM::D29_D30: OpKind = MCK_DPair; break; 9331 case ARM::D1_D2_D3_D4: OpKind = MCK_Reg119; break; 9332 case ARM::D3_D4_D5_D6: OpKind = MCK_Reg119; break; 9333 case ARM::D5_D6_D7_D8: OpKind = MCK_Reg120; break; 9334 case ARM::D7_D8_D9_D10: OpKind = MCK_Reg121; break; 9335 case ARM::D9_D10_D11_D12: OpKind = MCK_Reg122; break; 9336 case ARM::D11_D12_D13_D14: OpKind = MCK_Reg122; break; 9337 case ARM::D13_D14_D15_D16: OpKind = MCK_Reg123; break; 9338 case ARM::D15_D16_D17_D18: OpKind = MCK_Reg124; break; 9339 case ARM::D17_D18_D19_D20: OpKind = MCK_Reg125; break; 9340 case ARM::D19_D20_D21_D22: OpKind = MCK_Reg125; break; 9341 case ARM::D21_D22_D23_D24: OpKind = MCK_Reg125; break; 9342 case ARM::D23_D24_D25_D26: OpKind = MCK_Reg125; break; 9343 case ARM::D25_D26_D27_D28: OpKind = MCK_Reg125; break; 9344 case ARM::D27_D28_D29_D30: OpKind = MCK_Reg125; break; 9346 return isSubclass(OpKind, Kind) ? (unsigned)MCTargetAsmParser::Match_Success :