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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/ARM/ARMGenAsmMatcher.inc 6134 return MCK__EXCLAIM_; // "!"
9379 case MCK__EXCLAIM_: return "MCK__EXCLAIM_";
10505 { 373 /* fldmdbx */, ARM::FLDMXDB_UPD, Convert__Reg1_1__Tie0_2_2__CondCode2_0__DPRRegList1_3, AMFBS_HasFPRegs, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_, MCK_DPRRegList }, },
10507 { 381 /* fldmiax */, ARM::FLDMXIA_UPD, Convert__Reg1_1__Tie0_2_2__CondCode2_0__DPRRegList1_3, AMFBS_HasFPRegs, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_, MCK_DPRRegList }, },
10511 { 408 /* fstmdbx */, ARM::FSTMXDB_UPD, Convert__Reg1_1__Tie0_2_2__CondCode2_0__DPRRegList1_3, AMFBS_HasFPRegs, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_, MCK_DPRRegList }, },
10513 { 416 /* fstmiax */, ARM::FSTMXIA_UPD, Convert__Reg1_1__Tie0_2_2__CondCode2_0__DPRRegList1_3, AMFBS_HasFPRegs, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_, MCK_DPRRegList }, },
10548 { 502 /* ldc */, ARM::LDC_PRE, Convert__CoprocNum1_1__CoprocReg1_2__AddrMode52_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_AddrMode5, MCK__EXCLAIM_ }, },
10549 { 502 /* ldc */, ARM::t2LDC_PRE, Convert__CoprocNum1_1__CoprocReg1_2__AddrMode52_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_AddrMode5, MCK__EXCLAIM_ }, },
10556 { 506 /* ldc2 */, ARM::LDC2_PRE, Convert__CoprocNum1_0__CoprocReg1_1__AddrMode52_2, AMFBS_IsARM_PreV8, { MCK_CoprocNum, MCK_CoprocReg, MCK_AddrMode5, MCK__EXCLAIM_ }, },
10559 { 506 /* ldc2 */, ARM::t2LDC2_PRE, Convert__CoprocNum1_1__CoprocReg1_2__AddrMode52_3__CondCode2_0, AMFBS_PreV8_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_AddrMode5, MCK__EXCLAIM_ }, },
10564 { 511 /* ldc2l */, ARM::LDC2L_PRE, Convert__CoprocNum1_0__CoprocReg1_1__AddrMode52_2, AMFBS_IsARM_PreV8, { MCK_CoprocNum, MCK_CoprocReg, MCK_AddrMode5, MCK__EXCLAIM_ }, },
10567 { 511 /* ldc2l */, ARM::t2LDC2L_PRE, Convert__CoprocNum1_1__CoprocReg1_2__AddrMode52_3__CondCode2_0, AMFBS_PreV8_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_AddrMode5, MCK__EXCLAIM_ }, },
10572 { 517 /* ldcl */, ARM::LDCL_PRE, Convert__CoprocNum1_1__CoprocReg1_2__AddrMode52_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_AddrMode5, MCK__EXCLAIM_ }, },
10573 { 517 /* ldcl */, ARM::t2LDCL_PRE, Convert__CoprocNum1_1__CoprocReg1_2__AddrMode52_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_AddrMode5, MCK__EXCLAIM_ }, },
10582 { 522 /* ldm */, ARM::tLDMIA, Convert__Reg1_1__CondCode2_0__RegList1_3, AMFBS_IsThumb, { MCK_CondCode, MCK_tGPR, MCK__EXCLAIM_, MCK_RegList }, },
10583 { 522 /* ldm */, ARM::LDMIA_UPD, Convert__Reg1_1__Tie0_2_2__CondCode2_0__RegList1_3, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_, MCK_RegList }, },
10584 { 522 /* ldm */, ARM::t2LDMIA_UPD, Convert__Reg1_1__Tie0_2_2__CondCode2_0__RegList1_3, AMFBS_IsThumb2, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_, MCK_RegList }, },
10586 { 522 /* ldm */, ARM::t2LDMIA_UPD, Convert__Reg1_2__Tie0_3_3__CondCode2_0__RegList1_4, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPR, MCK__EXCLAIM_, MCK_RegList }, },
10587 { 522 /* ldm */, ARM::sysLDMIA_UPD, Convert__Reg1_1__Tie0_2_2__CondCode2_0__RegList1_3, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_, MCK_RegList, MCK__94_ }, },
10589 { 526 /* ldmda */, ARM::LDMDA_UPD, Convert__Reg1_1__Tie0_2_2__CondCode2_0__RegList1_3, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_, MCK_RegList }, },
10591 { 526 /* ldmda */, ARM::sysLDMDA_UPD, Convert__Reg1_1__Tie0_2_2__CondCode2_0__RegList1_3, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_, MCK_RegList, MCK__94_ }, },
10595 { 532 /* ldmdb */, ARM::LDMDB_UPD, Convert__Reg1_1__Tie0_2_2__CondCode2_0__RegList1_3, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_, MCK_RegList }, },
10596 { 532 /* ldmdb */, ARM::t2LDMDB_UPD, Convert__Reg1_1__Tie0_2_2__CondCode2_0__RegList1_3, AMFBS_IsThumb2, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_, MCK_RegList }, },
10598 { 532 /* ldmdb */, ARM::t2LDMDB_UPD, Convert__Reg1_2__Tie0_3_3__CondCode2_0__RegList1_4, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPR, MCK__EXCLAIM_, MCK_RegList }, },
10599 { 532 /* ldmdb */, ARM::sysLDMDB_UPD, Convert__Reg1_1__Tie0_2_2__CondCode2_0__RegList1_3, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_, MCK_RegList, MCK__94_ }, },
10601 { 538 /* ldmib */, ARM::LDMIB_UPD, Convert__Reg1_1__Tie0_2_2__CondCode2_0__RegList1_3, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_, MCK_RegList }, },
10603 { 538 /* ldmib */, ARM::sysLDMIB_UPD, Convert__Reg1_1__Tie0_2_2__CondCode2_0__RegList1_3, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_, MCK_RegList, MCK__94_ }, },
10623 { 544 /* ldr */, ARM::LDR_PRE_IMM, Convert__Reg1_1__imm_95_0__MemImm12Offset2_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemImm12Offset, MCK__EXCLAIM_ }, },
10624 { 544 /* ldr */, ARM::t2LDR_PRE, Convert__Reg1_1__imm_95_0__MemImm8Offset2_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_GPR, MCK_MemImm8Offset, MCK__EXCLAIM_ }, },
10628 { 544 /* ldr */, ARM::LDR_PRE_REG, Convert__Reg1_1__imm_95_0__MemRegOffset3_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemRegOffset, MCK__EXCLAIM_ }, },
10642 { 548 /* ldrb */, ARM::LDRB_PRE_IMM, Convert__Reg1_1__imm_95_0__MemImm12Offset2_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemImm12Offset, MCK__EXCLAIM_ }, },
10643 { 548 /* ldrb */, ARM::t2LDRB_PRE, Convert__Reg1_1__imm_95_0__MemImm8Offset2_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_GPR, MCK_MemImm8Offset, MCK__EXCLAIM_ }, },
10647 { 548 /* ldrb */, ARM::LDRB_PRE_REG, Convert__Reg1_1__imm_95_0__MemRegOffset3_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemRegOffset, MCK__EXCLAIM_ }, },
10654 { 559 /* ldrd */, ARM::t2LDRD_PRE, Convert__Reg1_1__Reg1_2__imm_95_0__MemImm8s4Offset2_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_MemImm8s4Offset, MCK__EXCLAIM_ }, },
10656 { 559 /* ldrd */, ARM::LDRD_PRE, Convert__Reg1_1__Reg1_2__imm_95_0__AddrMode33_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_AddrMode3, MCK__EXCLAIM_ }, },
10678 { 591 /* ldrh */, ARM::LDRH_PRE, Convert__Reg1_1__imm_95_0__AddrMode33_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_AddrMode3, MCK__EXCLAIM_ }, },
10679 { 591 /* ldrh */, ARM::t2LDRH_PRE, Convert__Reg1_1__imm_95_0__MemImm8Offset2_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_GPR, MCK_MemImm8Offset, MCK__EXCLAIM_ }, },
10696 { 602 /* ldrsb */, ARM::LDRSB_PRE, Convert__Reg1_1__imm_95_0__AddrMode33_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_AddrMode3, MCK__EXCLAIM_ }, },
10697 { 602 /* ldrsb */, ARM::t2LDRSB_PRE, Convert__Reg1_1__imm_95_0__MemImm8Offset2_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_GPR, MCK_MemImm8Offset, MCK__EXCLAIM_ }, },
10714 { 615 /* ldrsh */, ARM::LDRSH_PRE, Convert__Reg1_1__imm_95_0__AddrMode33_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_AddrMode3, MCK__EXCLAIM_ }, },
10715 { 615 /* ldrsh */, ARM::t2LDRSH_PRE, Convert__Reg1_1__imm_95_0__MemImm8Offset2_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_GPR, MCK_MemImm8Offset, MCK__EXCLAIM_ }, },
10973 { 877 /* rfeda */, ARM::RFEDA_UPD, Convert__Reg1_0, AMFBS_IsARM, { MCK_GPR, MCK__EXCLAIM_ }, },
10975 { 883 /* rfedb */, ARM::RFEDB_UPD, Convert__Reg1_0, AMFBS_IsARM, { MCK_GPR, MCK__EXCLAIM_ }, },
10977 { 883 /* rfedb */, ARM::t2RFEDBW, Convert__Reg1_1__CondCode2_0, AMFBS_IsThumb2_IsNotMClass, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_ }, },
10979 { 889 /* rfeia */, ARM::RFEIA_UPD, Convert__Reg1_0, AMFBS_IsARM, { MCK_GPR, MCK__EXCLAIM_ }, },
10981 { 889 /* rfeia */, ARM::t2RFEIAW, Convert__Reg1_1__CondCode2_0, AMFBS_IsThumb2_IsNotMClass, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_ }, },
10983 { 895 /* rfeib */, ARM::RFEIB_UPD, Convert__Reg1_0, AMFBS_IsARM, { MCK_GPR, MCK__EXCLAIM_ }, },
11169 { 1382 /* srsda */, ARM::SRSDA_UPD, Convert__Imm0_311_0, AMFBS_IsARM, { MCK_Imm0_31, MCK__EXCLAIM_ }, },
11170 { 1382 /* srsda */, ARM::SRSDA_UPD, Convert__Imm0_311_2, AMFBS_IsARM, { MCK_GPRsp, MCK__EXCLAIM_, MCK_Imm0_31 }, },
11174 { 1388 /* srsdb */, ARM::SRSDB_UPD, Convert__Imm0_311_0, AMFBS_IsARM, { MCK_Imm0_31, MCK__EXCLAIM_ }, },
11175 { 1388 /* srsdb */, ARM::SRSDB_UPD, Convert__Imm0_311_2, AMFBS_IsARM, { MCK_GPRsp, MCK__EXCLAIM_, MCK_Imm0_31 }, },
11177 { 1388 /* srsdb */, ARM::t2SRSDB_UPD, Convert__Imm0_311_1__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_Imm0_31, MCK__EXCLAIM_ }, },
11178 { 1388 /* srsdb */, ARM::t2SRSDB_UPD, Convert__Imm0_311_3__CondCode2_0, AMFBS_IsThumb2_IsNotMClass, { MCK_CondCode, MCK_GPRsp, MCK__EXCLAIM_, MCK_Imm0_31 }, },
11184 { 1407 /* srsia */, ARM::SRSIA_UPD, Convert__Imm0_311_0, AMFBS_IsARM, { MCK_Imm0_31, MCK__EXCLAIM_ }, },
11185 { 1407 /* srsia */, ARM::SRSIA_UPD, Convert__Imm0_311_2, AMFBS_IsARM, { MCK_GPRsp, MCK__EXCLAIM_, MCK_Imm0_31 }, },
11187 { 1407 /* srsia */, ARM::t2SRSIA_UPD, Convert__Imm0_311_1__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_Imm0_31, MCK__EXCLAIM_ }, },
11188 { 1407 /* srsia */, ARM::t2SRSIA_UPD, Convert__Imm0_311_3__CondCode2_0, AMFBS_IsThumb2_IsNotMClass, { MCK_CondCode, MCK_GPRsp, MCK__EXCLAIM_, MCK_Imm0_31 }, },
11191 { 1413 /* srsib */, ARM::SRSIB_UPD, Convert__Imm0_311_0, AMFBS_IsARM, { MCK_Imm0_31, MCK__EXCLAIM_ }, },
11192 { 1413 /* srsib */, ARM::SRSIB_UPD, Convert__Imm0_311_2, AMFBS_IsARM, { MCK_GPRsp, MCK__EXCLAIM_, MCK_Imm0_31 }, },
11209 { 1454 /* stc */, ARM::STC_PRE, Convert__CoprocNum1_1__CoprocReg1_2__AddrMode52_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_AddrMode5, MCK__EXCLAIM_ }, },
11210 { 1454 /* stc */, ARM::t2STC_PRE, Convert__CoprocNum1_1__CoprocReg1_2__AddrMode52_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_AddrMode5, MCK__EXCLAIM_ }, },
11217 { 1458 /* stc2 */, ARM::STC2_PRE, Convert__CoprocNum1_0__CoprocReg1_1__AddrMode52_2, AMFBS_IsARM_PreV8, { MCK_CoprocNum, MCK_CoprocReg, MCK_AddrMode5, MCK__EXCLAIM_ }, },
11220 { 1458 /* stc2 */, ARM::t2STC2_PRE, Convert__CoprocNum1_1__CoprocReg1_2__AddrMode52_3__CondCode2_0, AMFBS_PreV8_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_AddrMode5, MCK__EXCLAIM_ }, },
11225 { 1463 /* stc2l */, ARM::STC2L_PRE, Convert__CoprocNum1_0__CoprocReg1_1__AddrMode52_2, AMFBS_IsARM_PreV8, { MCK_CoprocNum, MCK_CoprocReg, MCK_AddrMode5, MCK__EXCLAIM_ }, },
11228 { 1463 /* stc2l */, ARM::t2STC2L_PRE, Convert__CoprocNum1_1__CoprocReg1_2__AddrMode52_3__CondCode2_0, AMFBS_PreV8_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_AddrMode5, MCK__EXCLAIM_ }, },
11233 { 1469 /* stcl */, ARM::STCL_PRE, Convert__CoprocNum1_1__CoprocReg1_2__AddrMode52_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_AddrMode5, MCK__EXCLAIM_ }, },
11234 { 1469 /* stcl */, ARM::t2STCL_PRE, Convert__CoprocNum1_1__CoprocReg1_2__AddrMode52_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_CoprocNum, MCK_CoprocReg, MCK_AddrMode5, MCK__EXCLAIM_ }, },
11257 { 1515 /* stm */, ARM::tSTMIA_UPD, Convert__Reg1_1__Tie0_2_2__CondCode2_0__RegList1_3, AMFBS_IsThumb, { MCK_CondCode, MCK_tGPR, MCK__EXCLAIM_, MCK_RegList }, },
11258 { 1515 /* stm */, ARM::STMIA_UPD, Convert__Reg1_1__Tie0_2_2__CondCode2_0__RegList1_3, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_, MCK_RegList }, },
11259 { 1515 /* stm */, ARM::t2STMIA_UPD, Convert__Reg1_1__Tie0_2_2__CondCode2_0__RegList1_3, AMFBS_IsThumb2, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_, MCK_RegList }, },
11261 { 1515 /* stm */, ARM::t2STMIA_UPD, Convert__Reg1_2__Tie0_3_3__CondCode2_0__RegList1_4, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPR, MCK__EXCLAIM_, MCK_RegList }, },
11262 { 1515 /* stm */, ARM::sysSTMIA_UPD, Convert__Reg1_1__Tie0_2_2__CondCode2_0__RegList1_3, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_, MCK_RegList, MCK__94_ }, },
11264 { 1519 /* stmda */, ARM::STMDA_UPD, Convert__Reg1_1__Tie0_2_2__CondCode2_0__RegList1_3, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_, MCK_RegList }, },
11266 { 1519 /* stmda */, ARM::sysSTMDA_UPD, Convert__Reg1_1__Tie0_2_2__CondCode2_0__RegList1_3, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_, MCK_RegList, MCK__94_ }, },
11270 { 1525 /* stmdb */, ARM::STMDB_UPD, Convert__Reg1_1__Tie0_2_2__CondCode2_0__RegList1_3, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_, MCK_RegList }, },
11271 { 1525 /* stmdb */, ARM::t2STMDB_UPD, Convert__Reg1_1__Tie0_2_2__CondCode2_0__RegList1_3, AMFBS_IsThumb2, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_, MCK_RegList }, },
11273 { 1525 /* stmdb */, ARM::t2STMDB_UPD, Convert__Reg1_2__Tie0_3_3__CondCode2_0__RegList1_4, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_GPR, MCK__EXCLAIM_, MCK_RegList }, },
11274 { 1525 /* stmdb */, ARM::sysSTMDB_UPD, Convert__Reg1_1__Tie0_2_2__CondCode2_0__RegList1_3, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_, MCK_RegList, MCK__94_ }, },
11276 { 1531 /* stmib */, ARM::STMIB_UPD, Convert__Reg1_1__Tie0_2_2__CondCode2_0__RegList1_3, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_, MCK_RegList }, },
11278 { 1531 /* stmib */, ARM::sysSTMIB_UPD, Convert__Reg1_1__Tie0_2_2__CondCode2_0__RegList1_3, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_, MCK_RegList, MCK__94_ }, },
11289 { 1537 /* str */, ARM::t2STR_PRE, Convert__imm_95_0__Reg1_1__MemImm8Offset2_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_GPRnopc, MCK_MemImm8Offset, MCK__EXCLAIM_ }, },
11291 { 1537 /* str */, ARM::STR_PRE_IMM, Convert__imm_95_0__Reg1_1__MemImm12Offset2_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemImm12Offset, MCK__EXCLAIM_ }, },
11294 { 1537 /* str */, ARM::STR_PRE_REG, Convert__imm_95_0__Reg1_1__MemRegOffset3_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemRegOffset, MCK__EXCLAIM_ }, },
11304 { 1541 /* strb */, ARM::t2STRB_PRE, Convert__imm_95_0__Reg1_1__MemImm8Offset2_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_MemImm8Offset, MCK__EXCLAIM_ }, },
11306 { 1541 /* strb */, ARM::STRB_PRE_IMM, Convert__imm_95_0__Reg1_1__MemImm12Offset2_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemImm12Offset, MCK__EXCLAIM_ }, },
11309 { 1541 /* strb */, ARM::STRB_PRE_REG, Convert__imm_95_0__Reg1_1__MemRegOffset3_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_MemRegOffset, MCK__EXCLAIM_ }, },
11316 { 1552 /* strd */, ARM::t2STRD_PRE, Convert__imm_95_0__Reg1_1__Reg1_2__MemImm8s4Offset2_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_MemImm8s4Offset, MCK__EXCLAIM_ }, },
11318 { 1552 /* strd */, ARM::STRD_PRE, Convert__imm_95_0__Reg1_1__Reg1_2__AddrMode33_3__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_AddrMode3, MCK__EXCLAIM_ }, },
11336 { 1584 /* strh */, ARM::t2STRH_PRE, Convert__imm_95_0__Reg1_1__MemImm8Offset2_2__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_MemImm8Offset, MCK__EXCLAIM_ }, },
11338 { 1584 /* strh */, ARM::STRH_PRE, Convert__imm_95_0__Reg1_1__AddrMode33_2__CondCode2_0, AMFBS_IsARM, { MCK_CondCode, MCK_GPR, MCK_AddrMode3, MCK__EXCLAIM_ }, },
12563 { 2348 /* vld1 */, ARM::VLD1DUPq16wb_fixed, Convert__VecListDPairAllLanes1_2__imm_95_0__DupAlignedMemory162_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListDPairAllLanes, MCK_DupAlignedMemory16, MCK__EXCLAIM_ }, },
12565 { 2348 /* vld1 */, ARM::VLD1q16wb_fixed, Convert__VecListDPair1_2__imm_95_0__AlignedMemory64or1282_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListDPair, MCK_AlignedMemory64or128, MCK__EXCLAIM_ }, },
12567 { 2348 /* vld1 */, ARM::VLD1d16Qwb_fixed, Convert__VecListFourD1_2__imm_95_0__AlignedMemory64or128or2562_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListFourD, MCK_AlignedMemory64or128or256, MCK__EXCLAIM_ }, },
12569 { 2348 /* vld1 */, ARM::VLD1DUPd16wb_fixed, Convert__VecListOneDAllLanes1_2__imm_95_0__DupAlignedMemory162_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListOneDAllLanes, MCK_DupAlignedMemory16, MCK__EXCLAIM_ }, },
12571 { 2348 /* vld1 */, ARM::VLD1d16wb_fixed, Convert__VecListOneD1_2__imm_95_0__AlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListOneD, MCK_AlignedMemory64, MCK__EXCLAIM_ }, },
12573 { 2348 /* vld1 */, ARM::VLD1LNdWB_fixed_Asm_16, Convert__VecListOneDHWordIndexed2_2__AlignedMemory162_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListOneDHWordIndexed, MCK_AlignedMemory16, MCK__EXCLAIM_ }, },
12575 { 2348 /* vld1 */, ARM::VLD1d16Twb_fixed, Convert__VecListThreeD1_2__imm_95_0__AlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListThreeD, MCK_AlignedMemory64, MCK__EXCLAIM_ }, },
12577 { 2348 /* vld1 */, ARM::VLD1DUPq32wb_fixed, Convert__VecListDPairAllLanes1_2__imm_95_0__DupAlignedMemory322_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListDPairAllLanes, MCK_DupAlignedMemory32, MCK__EXCLAIM_ }, },
12579 { 2348 /* vld1 */, ARM::VLD1q32wb_fixed, Convert__VecListDPair1_2__imm_95_0__AlignedMemory64or1282_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListDPair, MCK_AlignedMemory64or128, MCK__EXCLAIM_ }, },
12581 { 2348 /* vld1 */, ARM::VLD1d32Qwb_fixed, Convert__VecListFourD1_2__imm_95_0__AlignedMemory64or128or2562_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListFourD, MCK_AlignedMemory64or128or256, MCK__EXCLAIM_ }, },
12583 { 2348 /* vld1 */, ARM::VLD1DUPd32wb_fixed, Convert__VecListOneDAllLanes1_2__imm_95_0__DupAlignedMemory322_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListOneDAllLanes, MCK_DupAlignedMemory32, MCK__EXCLAIM_ }, },
12585 { 2348 /* vld1 */, ARM::VLD1d32wb_fixed, Convert__VecListOneD1_2__imm_95_0__AlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListOneD, MCK_AlignedMemory64, MCK__EXCLAIM_ }, },
12587 { 2348 /* vld1 */, ARM::VLD1LNdWB_fixed_Asm_32, Convert__VecListOneDWordIndexed2_2__AlignedMemory322_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListOneDWordIndexed, MCK_AlignedMemory32, MCK__EXCLAIM_ }, },
12589 { 2348 /* vld1 */, ARM::VLD1d32Twb_fixed, Convert__VecListThreeD1_2__imm_95_0__AlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListThreeD, MCK_AlignedMemory64, MCK__EXCLAIM_ }, },
12591 { 2348 /* vld1 */, ARM::VLD1q64wb_fixed, Convert__VecListDPair1_2__imm_95_0__AlignedMemory64or1282_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_VecListDPair, MCK_AlignedMemory64or128, MCK__EXCLAIM_ }, },
12593 { 2348 /* vld1 */, ARM::VLD1d64Qwb_fixed, Convert__VecListFourD1_2__imm_95_0__AlignedMemory64or128or2562_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_VecListFourD, MCK_AlignedMemory64or128or256, MCK__EXCLAIM_ }, },
12595 { 2348 /* vld1 */, ARM::VLD1d64wb_fixed, Convert__VecListOneD1_2__imm_95_0__AlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_VecListOneD, MCK_AlignedMemory64, MCK__EXCLAIM_ }, },
12597 { 2348 /* vld1 */, ARM::VLD1d64Twb_fixed, Convert__VecListThreeD1_2__imm_95_0__AlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_VecListThreeD, MCK_AlignedMemory64, MCK__EXCLAIM_ }, },
12599 { 2348 /* vld1 */, ARM::VLD1DUPq8wb_fixed, Convert__VecListDPairAllLanes1_2__imm_95_0__DupAlignedMemoryNone2_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListDPairAllLanes, MCK_DupAlignedMemoryNone, MCK__EXCLAIM_ }, },
12601 { 2348 /* vld1 */, ARM::VLD1q8wb_fixed, Convert__VecListDPair1_2__imm_95_0__AlignedMemory64or1282_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListDPair, MCK_AlignedMemory64or128, MCK__EXCLAIM_ }, },
12603 { 2348 /* vld1 */, ARM::VLD1d8Qwb_fixed, Convert__VecListFourD1_2__imm_95_0__AlignedMemory64or128or2562_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListFourD, MCK_AlignedMemory64or128or256, MCK__EXCLAIM_ }, },
12605 { 2348 /* vld1 */, ARM::VLD1DUPd8wb_fixed, Convert__VecListOneDAllLanes1_2__imm_95_0__DupAlignedMemoryNone2_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListOneDAllLanes, MCK_DupAlignedMemoryNone, MCK__EXCLAIM_ }, },
12607 { 2348 /* vld1 */, ARM::VLD1d8wb_fixed, Convert__VecListOneD1_2__imm_95_0__AlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListOneD, MCK_AlignedMemory64, MCK__EXCLAIM_ }, },
12609 { 2348 /* vld1 */, ARM::VLD1LNdWB_fixed_Asm_8, Convert__VecListOneDByteIndexed2_2__AlignedMemoryNone2_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListOneDByteIndexed, MCK_AlignedMemoryNone, MCK__EXCLAIM_ }, },
12611 { 2348 /* vld1 */, ARM::VLD1d8Twb_fixed, Convert__VecListThreeD1_2__imm_95_0__AlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListThreeD, MCK_AlignedMemory64, MCK__EXCLAIM_ }, },
12639 { 2353 /* vld2 */, ARM::VLD2DUPd16wb_fixed, Convert__VecListDPairAllLanes1_2__imm_95_0__DupAlignedMemory322_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListDPairAllLanes, MCK_DupAlignedMemory32, MCK__EXCLAIM_ }, },
12641 { 2353 /* vld2 */, ARM::VLD2d16wb_fixed, Convert__VecListDPair1_2__imm_95_0__AlignedMemory64or1282_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListDPair, MCK_AlignedMemory64or128, MCK__EXCLAIM_ }, },
12643 { 2353 /* vld2 */, ARM::VLD2DUPd16x2wb_fixed, Convert__VecListDPairSpacedAllLanes1_2__imm_95_0__DupAlignedMemory322_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListDPairSpacedAllLanes, MCK_DupAlignedMemory32, MCK__EXCLAIM_ }, },
12645 { 2353 /* vld2 */, ARM::VLD2b16wb_fixed, Convert__VecListDPairSpaced1_2__imm_95_0__AlignedMemory64or1282_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListDPairSpaced, MCK_AlignedMemory64or128, MCK__EXCLAIM_ }, },
12647 { 2353 /* vld2 */, ARM::VLD2q16wb_fixed, Convert__VecListFourD1_2__imm_95_0__AlignedMemory64or128or2562_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListFourD, MCK_AlignedMemory64or128or256, MCK__EXCLAIM_ }, },
12649 { 2353 /* vld2 */, ARM::VLD2LNdWB_fixed_Asm_16, Convert__VecListTwoDHWordIndexed2_2__AlignedMemory322_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListTwoDHWordIndexed, MCK_AlignedMemory32, MCK__EXCLAIM_ }, },
12651 { 2353 /* vld2 */, ARM::VLD2LNqWB_fixed_Asm_16, Convert__VecListTwoQHWordIndexed2_2__AlignedMemory322_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListTwoQHWordIndexed, MCK_AlignedMemory32, MCK__EXCLAIM_ }, },
12653 { 2353 /* vld2 */, ARM::VLD2DUPd32wb_fixed, Convert__VecListDPairAllLanes1_2__imm_95_0__DupAlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListDPairAllLanes, MCK_DupAlignedMemory64, MCK__EXCLAIM_ }, },
12655 { 2353 /* vld2 */, ARM::VLD2d32wb_fixed, Convert__VecListDPair1_2__imm_95_0__AlignedMemory64or1282_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListDPair, MCK_AlignedMemory64or128, MCK__EXCLAIM_ }, },
12657 { 2353 /* vld2 */, ARM::VLD2DUPd32x2wb_fixed, Convert__VecListDPairSpacedAllLanes1_2__imm_95_0__DupAlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListDPairSpacedAllLanes, MCK_DupAlignedMemory64, MCK__EXCLAIM_ }, },
12659 { 2353 /* vld2 */, ARM::VLD2b32wb_fixed, Convert__VecListDPairSpaced1_2__imm_95_0__AlignedMemory64or1282_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListDPairSpaced, MCK_AlignedMemory64or128, MCK__EXCLAIM_ }, },
12661 { 2353 /* vld2 */, ARM::VLD2q32wb_fixed, Convert__VecListFourD1_2__imm_95_0__AlignedMemory64or128or2562_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListFourD, MCK_AlignedMemory64or128or256, MCK__EXCLAIM_ }, },
12663 { 2353 /* vld2 */, ARM::VLD2LNdWB_fixed_Asm_32, Convert__VecListTwoDWordIndexed2_2__AlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListTwoDWordIndexed, MCK_AlignedMemory64, MCK__EXCLAIM_ }, },
12665 { 2353 /* vld2 */, ARM::VLD2LNqWB_fixed_Asm_32, Convert__VecListTwoQWordIndexed2_2__AlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListTwoQWordIndexed, MCK_AlignedMemory64, MCK__EXCLAIM_ }, },
12667 { 2353 /* vld2 */, ARM::VLD2DUPd8wb_fixed, Convert__VecListDPairAllLanes1_2__imm_95_0__DupAlignedMemory162_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListDPairAllLanes, MCK_DupAlignedMemory16, MCK__EXCLAIM_ }, },
12669 { 2353 /* vld2 */, ARM::VLD2d8wb_fixed, Convert__VecListDPair1_2__imm_95_0__AlignedMemory64or1282_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListDPair, MCK_AlignedMemory64or128, MCK__EXCLAIM_ }, },
12671 { 2353 /* vld2 */, ARM::VLD2DUPd8x2wb_fixed, Convert__VecListDPairSpacedAllLanes1_2__imm_95_0__DupAlignedMemory162_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListDPairSpacedAllLanes, MCK_DupAlignedMemory16, MCK__EXCLAIM_ }, },
12673 { 2353 /* vld2 */, ARM::VLD2b8wb_fixed, Convert__VecListDPairSpaced1_2__imm_95_0__AlignedMemory64or1282_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListDPairSpaced, MCK_AlignedMemory64or128, MCK__EXCLAIM_ }, },
12675 { 2353 /* vld2 */, ARM::VLD2q8wb_fixed, Convert__VecListFourD1_2__imm_95_0__AlignedMemory64or128or2562_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListFourD, MCK_AlignedMemory64or128or256, MCK__EXCLAIM_ }, },
12677 { 2353 /* vld2 */, ARM::VLD2LNdWB_fixed_Asm_8, Convert__VecListTwoDByteIndexed2_2__AlignedMemory162_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListTwoDByteIndexed, MCK_AlignedMemory16, MCK__EXCLAIM_ }, },
12682 { 2358 /* vld20 */, ARM::MVE_VLD20_16_wb, Convert__VecListTwoMQ1_1__MemNoOffsetT2NoSp1_2__Tie0_1_1__Tie1_3_3, AMFBS_HasMVEInt, { MCK__DOT_16, MCK_VecListTwoMQ, MCK_MemNoOffsetT2NoSp, MCK__EXCLAIM_ }, },
12683 { 2358 /* vld20 */, ARM::MVE_VLD20_32_wb, Convert__VecListTwoMQ1_1__MemNoOffsetT2NoSp1_2__Tie0_1_1__Tie1_3_3, AMFBS_HasMVEInt, { MCK__DOT_32, MCK_VecListTwoMQ, MCK_MemNoOffsetT2NoSp, MCK__EXCLAIM_ }, },
12684 { 2358 /* vld20 */, ARM::MVE_VLD20_8_wb, Convert__VecListTwoMQ1_1__MemNoOffsetT2NoSp1_2__Tie0_1_1__Tie1_3_3, AMFBS_HasMVEInt, { MCK__DOT_8, MCK_VecListTwoMQ, MCK_MemNoOffsetT2NoSp, MCK__EXCLAIM_ }, },
12688 { 2364 /* vld21 */, ARM::MVE_VLD21_16_wb, Convert__VecListTwoMQ1_1__MemNoOffsetT2NoSp1_2__Tie0_1_1__Tie1_3_3, AMFBS_HasMVEInt, { MCK__DOT_16, MCK_VecListTwoMQ, MCK_MemNoOffsetT2NoSp, MCK__EXCLAIM_ }, },
12689 { 2364 /* vld21 */, ARM::MVE_VLD21_32_wb, Convert__VecListTwoMQ1_1__MemNoOffsetT2NoSp1_2__Tie0_1_1__Tie1_3_3, AMFBS_HasMVEInt, { MCK__DOT_32, MCK_VecListTwoMQ, MCK_MemNoOffsetT2NoSp, MCK__EXCLAIM_ }, },
12690 { 2364 /* vld21 */, ARM::MVE_VLD21_8_wb, Convert__VecListTwoMQ1_1__MemNoOffsetT2NoSp1_2__Tie0_1_1__Tie1_3_3, AMFBS_HasMVEInt, { MCK__DOT_8, MCK_VecListTwoMQ, MCK_MemNoOffsetT2NoSp, MCK__EXCLAIM_ }, },
12708 { 2370 /* vld3 */, ARM::VLD3DUPdWB_fixed_Asm_16, Convert__VecListThreeDAllLanes1_2__DupAlignedMemoryNone2_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListThreeDAllLanes, MCK_DupAlignedMemoryNone, MCK__EXCLAIM_ }, },
12710 { 2370 /* vld3 */, ARM::VLD3dWB_fixed_Asm_16, Convert__VecListThreeD1_2__AlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListThreeD, MCK_AlignedMemory64, MCK__EXCLAIM_ }, },
12712 { 2370 /* vld3 */, ARM::VLD3LNdWB_fixed_Asm_16, Convert__VecListThreeDHWordIndexed2_2__AlignedMemoryNone2_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListThreeDHWordIndexed, MCK_AlignedMemoryNone, MCK__EXCLAIM_ }, },
12714 { 2370 /* vld3 */, ARM::VLD3DUPqWB_fixed_Asm_16, Convert__VecListThreeQAllLanes1_2__DupAlignedMemoryNone2_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListThreeQAllLanes, MCK_DupAlignedMemoryNone, MCK__EXCLAIM_ }, },
12716 { 2370 /* vld3 */, ARM::VLD3qWB_fixed_Asm_16, Convert__VecListThreeQ1_2__AlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListThreeQ, MCK_AlignedMemory64, MCK__EXCLAIM_ }, },
12718 { 2370 /* vld3 */, ARM::VLD3LNqWB_fixed_Asm_16, Convert__VecListThreeQHWordIndexed2_2__AlignedMemoryNone2_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListThreeQHWordIndexed, MCK_AlignedMemoryNone, MCK__EXCLAIM_ }, },
12720 { 2370 /* vld3 */, ARM::VLD3DUPdWB_fixed_Asm_32, Convert__VecListThreeDAllLanes1_2__DupAlignedMemoryNone2_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListThreeDAllLanes, MCK_DupAlignedMemoryNone, MCK__EXCLAIM_ }, },
12722 { 2370 /* vld3 */, ARM::VLD3dWB_fixed_Asm_32, Convert__VecListThreeD1_2__AlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListThreeD, MCK_AlignedMemory64, MCK__EXCLAIM_ }, },
12724 { 2370 /* vld3 */, ARM::VLD3LNdWB_fixed_Asm_32, Convert__VecListThreeDWordIndexed2_2__AlignedMemoryNone2_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListThreeDWordIndexed, MCK_AlignedMemoryNone, MCK__EXCLAIM_ }, },
12726 { 2370 /* vld3 */, ARM::VLD3DUPqWB_fixed_Asm_32, Convert__VecListThreeQAllLanes1_2__DupAlignedMemoryNone2_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListThreeQAllLanes, MCK_DupAlignedMemoryNone, MCK__EXCLAIM_ }, },
12728 { 2370 /* vld3 */, ARM::VLD3qWB_fixed_Asm_32, Convert__VecListThreeQ1_2__AlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListThreeQ, MCK_AlignedMemory64, MCK__EXCLAIM_ }, },
12730 { 2370 /* vld3 */, ARM::VLD3LNqWB_fixed_Asm_32, Convert__VecListThreeQWordIndexed2_2__AlignedMemoryNone2_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListThreeQWordIndexed, MCK_AlignedMemoryNone, MCK__EXCLAIM_ }, },
12732 { 2370 /* vld3 */, ARM::VLD3DUPdWB_fixed_Asm_8, Convert__VecListThreeDAllLanes1_2__DupAlignedMemoryNone2_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListThreeDAllLanes, MCK_DupAlignedMemoryNone, MCK__EXCLAIM_ }, },
12734 { 2370 /* vld3 */, ARM::VLD3dWB_fixed_Asm_8, Convert__VecListThreeD1_2__AlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListThreeD, MCK_AlignedMemory64, MCK__EXCLAIM_ }, },
12736 { 2370 /* vld3 */, ARM::VLD3LNdWB_fixed_Asm_8, Convert__VecListThreeDByteIndexed2_2__AlignedMemoryNone2_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListThreeDByteIndexed, MCK_AlignedMemoryNone, MCK__EXCLAIM_ }, },
12738 { 2370 /* vld3 */, ARM::VLD3DUPqWB_fixed_Asm_8, Convert__VecListThreeQAllLanes1_2__DupAlignedMemoryNone2_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListThreeQAllLanes, MCK_DupAlignedMemoryNone, MCK__EXCLAIM_ }, },
12740 { 2370 /* vld3 */, ARM::VLD3qWB_fixed_Asm_8, Convert__VecListThreeQ1_2__AlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListThreeQ, MCK_AlignedMemory64, MCK__EXCLAIM_ }, },
12783 { 2375 /* vld4 */, ARM::VLD4DUPdWB_fixed_Asm_16, Convert__VecListFourDAllLanes1_2__DupAlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListFourDAllLanes, MCK_DupAlignedMemory64, MCK__EXCLAIM_ }, },
12785 { 2375 /* vld4 */, ARM::VLD4dWB_fixed_Asm_16, Convert__VecListFourD1_2__AlignedMemory64or128or2562_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListFourD, MCK_AlignedMemory64or128or256, MCK__EXCLAIM_ }, },
12787 { 2375 /* vld4 */, ARM::VLD4LNdWB_fixed_Asm_16, Convert__VecListFourDHWordIndexed2_2__AlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListFourDHWordIndexed, MCK_AlignedMemory64, MCK__EXCLAIM_ }, },
12789 { 2375 /* vld4 */, ARM::VLD4DUPqWB_fixed_Asm_16, Convert__VecListFourQAllLanes1_2__DupAlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListFourQAllLanes, MCK_DupAlignedMemory64, MCK__EXCLAIM_ }, },
12791 { 2375 /* vld4 */, ARM::VLD4qWB_fixed_Asm_16, Convert__VecListFourQ1_2__AlignedMemory64or128or2562_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListFourQ, MCK_AlignedMemory64or128or256, MCK__EXCLAIM_ }, },
12793 { 2375 /* vld4 */, ARM::VLD4LNqWB_fixed_Asm_16, Convert__VecListFourQHWordIndexed2_2__AlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListFourQHWordIndexed, MCK_AlignedMemory64, MCK__EXCLAIM_ }, },
12795 { 2375 /* vld4 */, ARM::VLD4DUPdWB_fixed_Asm_32, Convert__VecListFourDAllLanes1_2__DupAlignedMemory64or1282_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListFourDAllLanes, MCK_DupAlignedMemory64or128, MCK__EXCLAIM_ }, },
12797 { 2375 /* vld4 */, ARM::VLD4dWB_fixed_Asm_32, Convert__VecListFourD1_2__AlignedMemory64or128or2562_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListFourD, MCK_AlignedMemory64or128or256, MCK__EXCLAIM_ }, },
12799 { 2375 /* vld4 */, ARM::VLD4LNdWB_fixed_Asm_32, Convert__VecListFourDWordIndexed2_2__AlignedMemory64or1282_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListFourDWordIndexed, MCK_AlignedMemory64or128, MCK__EXCLAIM_ }, },
12801 { 2375 /* vld4 */, ARM::VLD4DUPqWB_fixed_Asm_32, Convert__VecListFourQAllLanes1_2__DupAlignedMemory64or1282_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListFourQAllLanes, MCK_DupAlignedMemory64or128, MCK__EXCLAIM_ }, },
12803 { 2375 /* vld4 */, ARM::VLD4qWB_fixed_Asm_32, Convert__VecListFourQ1_2__AlignedMemory64or128or2562_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListFourQ, MCK_AlignedMemory64or128or256, MCK__EXCLAIM_ }, },
12805 { 2375 /* vld4 */, ARM::VLD4LNqWB_fixed_Asm_32, Convert__VecListFourQWordIndexed2_2__AlignedMemory64or1282_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListFourQWordIndexed, MCK_AlignedMemory64or128, MCK__EXCLAIM_ }, },
12807 { 2375 /* vld4 */, ARM::VLD4DUPdWB_fixed_Asm_8, Convert__VecListFourDAllLanes1_2__DupAlignedMemory322_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListFourDAllLanes, MCK_DupAlignedMemory32, MCK__EXCLAIM_ }, },
12809 { 2375 /* vld4 */, ARM::VLD4dWB_fixed_Asm_8, Convert__VecListFourD1_2__AlignedMemory64or128or2562_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListFourD, MCK_AlignedMemory64or128or256, MCK__EXCLAIM_ }, },
12811 { 2375 /* vld4 */, ARM::VLD4LNdWB_fixed_Asm_8, Convert__VecListFourDByteIndexed2_2__AlignedMemory322_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListFourDByteIndexed, MCK_AlignedMemory32, MCK__EXCLAIM_ }, },
12813 { 2375 /* vld4 */, ARM::VLD4DUPqWB_fixed_Asm_8, Convert__VecListFourQAllLanes1_2__DupAlignedMemory322_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListFourQAllLanes, MCK_DupAlignedMemory32, MCK__EXCLAIM_ }, },
12815 { 2375 /* vld4 */, ARM::VLD4qWB_fixed_Asm_8, Convert__VecListFourQ1_2__AlignedMemory64or128or2562_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListFourQ, MCK_AlignedMemory64or128or256, MCK__EXCLAIM_ }, },
12844 { 2380 /* vld40 */, ARM::MVE_VLD40_16_wb, Convert__VecListFourMQ1_1__MemNoOffsetT2NoSp1_2__Tie0_1_1__Tie1_3_3, AMFBS_HasMVEInt, { MCK__DOT_16, MCK_VecListFourMQ, MCK_MemNoOffsetT2NoSp, MCK__EXCLAIM_ }, },
12845 { 2380 /* vld40 */, ARM::MVE_VLD40_32_wb, Convert__VecListFourMQ1_1__MemNoOffsetT2NoSp1_2__Tie0_1_1__Tie1_3_3, AMFBS_HasMVEInt, { MCK__DOT_32, MCK_VecListFourMQ, MCK_MemNoOffsetT2NoSp, MCK__EXCLAIM_ }, },
12846 { 2380 /* vld40 */, ARM::MVE_VLD40_8_wb, Convert__VecListFourMQ1_1__MemNoOffsetT2NoSp1_2__Tie0_1_1__Tie1_3_3, AMFBS_HasMVEInt, { MCK__DOT_8, MCK_VecListFourMQ, MCK_MemNoOffsetT2NoSp, MCK__EXCLAIM_ }, },
12850 { 2386 /* vld41 */, ARM::MVE_VLD41_16_wb, Convert__VecListFourMQ1_1__MemNoOffsetT2NoSp1_2__Tie0_1_1__Tie1_3_3, AMFBS_HasMVEInt, { MCK__DOT_16, MCK_VecListFourMQ, MCK_MemNoOffsetT2NoSp, MCK__EXCLAIM_ }, },
12851 { 2386 /* vld41 */, ARM::MVE_VLD41_32_wb, Convert__VecListFourMQ1_1__MemNoOffsetT2NoSp1_2__Tie0_1_1__Tie1_3_3, AMFBS_HasMVEInt, { MCK__DOT_32, MCK_VecListFourMQ, MCK_MemNoOffsetT2NoSp, MCK__EXCLAIM_ }, },
12852 { 2386 /* vld41 */, ARM::MVE_VLD41_8_wb, Convert__VecListFourMQ1_1__MemNoOffsetT2NoSp1_2__Tie0_1_1__Tie1_3_3, AMFBS_HasMVEInt, { MCK__DOT_8, MCK_VecListFourMQ, MCK_MemNoOffsetT2NoSp, MCK__EXCLAIM_ }, },
12856 { 2392 /* vld42 */, ARM::MVE_VLD42_16_wb, Convert__VecListFourMQ1_1__MemNoOffsetT2NoSp1_2__Tie0_1_1__Tie1_3_3, AMFBS_HasMVEInt, { MCK__DOT_16, MCK_VecListFourMQ, MCK_MemNoOffsetT2NoSp, MCK__EXCLAIM_ }, },
12857 { 2392 /* vld42 */, ARM::MVE_VLD42_32_wb, Convert__VecListFourMQ1_1__MemNoOffsetT2NoSp1_2__Tie0_1_1__Tie1_3_3, AMFBS_HasMVEInt, { MCK__DOT_32, MCK_VecListFourMQ, MCK_MemNoOffsetT2NoSp, MCK__EXCLAIM_ }, },
12858 { 2392 /* vld42 */, ARM::MVE_VLD42_8_wb, Convert__VecListFourMQ1_1__MemNoOffsetT2NoSp1_2__Tie0_1_1__Tie1_3_3, AMFBS_HasMVEInt, { MCK__DOT_8, MCK_VecListFourMQ, MCK_MemNoOffsetT2NoSp, MCK__EXCLAIM_ }, },
12862 { 2398 /* vld43 */, ARM::MVE_VLD43_16_wb, Convert__VecListFourMQ1_1__MemNoOffsetT2NoSp1_2__Tie0_1_1__Tie1_3_3, AMFBS_HasMVEInt, { MCK__DOT_16, MCK_VecListFourMQ, MCK_MemNoOffsetT2NoSp, MCK__EXCLAIM_ }, },
12863 { 2398 /* vld43 */, ARM::MVE_VLD43_32_wb, Convert__VecListFourMQ1_1__MemNoOffsetT2NoSp1_2__Tie0_1_1__Tie1_3_3, AMFBS_HasMVEInt, { MCK__DOT_32, MCK_VecListFourMQ, MCK_MemNoOffsetT2NoSp, MCK__EXCLAIM_ }, },
12864 { 2398 /* vld43 */, ARM::MVE_VLD43_8_wb, Convert__VecListFourMQ1_1__MemNoOffsetT2NoSp1_2__Tie0_1_1__Tie1_3_3, AMFBS_HasMVEInt, { MCK__DOT_8, MCK_VecListFourMQ, MCK_MemNoOffsetT2NoSp, MCK__EXCLAIM_ }, },
12865 { 2404 /* vldmdb */, ARM::VLDMDDB_UPD, Convert__Reg1_1__Tie0_2_2__CondCode2_0__DPRRegList1_3, AMFBS_HasFPRegs, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_, MCK_DPRRegList }, },
12866 { 2404 /* vldmdb */, ARM::VLDMSDB_UPD, Convert__Reg1_1__Tie0_2_2__CondCode2_0__SPRRegList1_3, AMFBS_HasFPRegs, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_, MCK_SPRRegList }, },
12869 { 2411 /* vldmia */, ARM::VLDMDIA_UPD, Convert__Reg1_1__Tie0_2_2__CondCode2_0__DPRRegList1_3, AMFBS_HasFPRegs, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_, MCK_DPRRegList }, },
12870 { 2411 /* vldmia */, ARM::VLDMSIA_UPD, Convert__Reg1_1__Tie0_2_2__CondCode2_0__SPRRegList1_3, AMFBS_HasFPRegs, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_, MCK_SPRRegList }, },
12882 { 2418 /* vldr */, ARM::VLDR_FPCXTNS_pre, Convert__imm_95_0__MemImm7s4Offset2_2__CondCode2_0, AMFBS_HasV8_1MMainline_Has8MSecExt, { MCK_CondCode, MCK_FPCXTNS, MCK_MemImm7s4Offset, MCK__EXCLAIM_ }, },
12884 { 2418 /* vldr */, ARM::VLDR_FPCXTS_pre, Convert__imm_95_0__MemImm7s4Offset2_2__CondCode2_0, AMFBS_HasV8_1MMainline_Has8MSecExt, { MCK_CondCode, MCK_FPCXTS, MCK_MemImm7s4Offset, MCK__EXCLAIM_ }, },
12886 { 2418 /* vldr */, ARM::VLDR_FPSCR_pre, Convert__imm_95_0__MemImm7s4Offset2_2__CondCode2_0, AMFBS_HasFPRegs_HasV8_1MMainline, { MCK_CondCode, MCK_FPSCR, MCK_MemImm7s4Offset, MCK__EXCLAIM_ }, },
12888 { 2418 /* vldr */, ARM::VLDR_FPSCR_NZCVQC_pre, Convert__imm_95_0__MemImm7s4Offset2_2__CondCode2_0, AMFBS_HasFPRegs_HasV8_1MMainline, { MCK_CondCode, MCK_FPSCR_NZCVQC, MCK_MemImm7s4Offset, MCK__EXCLAIM_ }, },
12890 { 2418 /* vldr */, ARM::VLDR_P0_pre, Convert__imm_95_0__imm_95_0__MemImm7s4Offset2_2__CondCode2_0, AMFBS_HasV8_1MMainline_HasMVEInt, { MCK_CondCode, MCK_P0, MCK_MemImm7s4Offset, MCK__EXCLAIM_ }, },
12892 { 2418 /* vldr */, ARM::VLDR_VPR_pre, Convert__imm_95_0__MemImm7s4Offset2_2__CondCode2_0, AMFBS_HasV8_1MMainline_HasMVEInt, { MCK_CondCode, MCK_VCCR, MCK_MemImm7s4Offset, MCK__EXCLAIM_ }, },
12905 { 2423 /* vldrb */, ARM::MVE_VLDRBS16_pre, Convert__imm_95_0__Reg1_2__TMemImm7Shift0Offset2_3__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s16, MCK_MQPR, MCK_TMemImm7Shift0Offset, MCK__EXCLAIM_ }, },
12907 { 2423 /* vldrb */, ARM::MVE_VLDRBS32_pre, Convert__imm_95_0__Reg1_2__TMemImm7Shift0Offset2_3__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_MQPR, MCK_TMemImm7Shift0Offset, MCK__EXCLAIM_ }, },
12909 { 2423 /* vldrb */, ARM::MVE_VLDRBU16_pre, Convert__imm_95_0__Reg1_2__TMemImm7Shift0Offset2_3__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u16, MCK_MQPR, MCK_TMemImm7Shift0Offset, MCK__EXCLAIM_ }, },
12911 { 2423 /* vldrb */, ARM::MVE_VLDRBU32_pre, Convert__imm_95_0__Reg1_2__TMemImm7Shift0Offset2_3__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u32, MCK_MQPR, MCK_TMemImm7Shift0Offset, MCK__EXCLAIM_ }, },
12912 { 2423 /* vldrb */, ARM::MVE_VLDRBU8_pre, Convert__imm_95_0__Reg1_2__MemImm7Shift0OffsetWB2_3__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u8, MCK_MQPR, MCK_MemImm7Shift0OffsetWB, MCK__EXCLAIM_ }, },
12917 { 2429 /* vldrd */, ARM::MVE_VLDRDU64_qi_pre, Convert__imm_95_0__Reg1_2__MemRegQS3Offset2_3__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u64, MCK_MQPR, MCK_MemRegQS3Offset, MCK__EXCLAIM_ }, },
12928 { 2435 /* vldrh */, ARM::MVE_VLDRHS32_pre, Convert__imm_95_0__Reg1_2__TMemImm7Shift1Offset2_3__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_MQPR, MCK_TMemImm7Shift1Offset, MCK__EXCLAIM_ }, },
12929 { 2435 /* vldrh */, ARM::MVE_VLDRHU16_pre, Convert__imm_95_0__Reg1_2__MemImm7Shift1OffsetWB2_3__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u16, MCK_MQPR, MCK_MemImm7Shift1OffsetWB, MCK__EXCLAIM_ }, },
12932 { 2435 /* vldrh */, ARM::MVE_VLDRHU32_pre, Convert__imm_95_0__Reg1_2__TMemImm7Shift1Offset2_3__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u32, MCK_MQPR, MCK_TMemImm7Shift1Offset, MCK__EXCLAIM_ }, },
12937 { 2441 /* vldrw */, ARM::MVE_VLDRWU32_pre, Convert__imm_95_0__Reg1_2__MemImm7Shift2OffsetWB2_3__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u32, MCK_MQPR, MCK_MemImm7Shift2OffsetWB, MCK__EXCLAIM_ }, },
12939 { 2441 /* vldrw */, ARM::MVE_VLDRWU32_qi_pre, Convert__imm_95_0__Reg1_2__MemRegQS2Offset2_3__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u32, MCK_MQPR, MCK_MemRegQS2Offset, MCK__EXCLAIM_ }, },
14667 { 3770 /* vst1 */, ARM::VST1q16wb_fixed, Convert__imm_95_0__AlignedMemory64or1282_3__VecListDPair1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListDPair, MCK_AlignedMemory64or128, MCK__EXCLAIM_ }, },
14669 { 3770 /* vst1 */, ARM::VST1d16Qwb_fixed, Convert__imm_95_0__AlignedMemory64or128or2562_3__VecListFourD1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListFourD, MCK_AlignedMemory64or128or256, MCK__EXCLAIM_ }, },
14671 { 3770 /* vst1 */, ARM::VST1d16wb_fixed, Convert__imm_95_0__AlignedMemory642_3__VecListOneD1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListOneD, MCK_AlignedMemory64, MCK__EXCLAIM_ }, },
14673 { 3770 /* vst1 */, ARM::VST1LNdWB_fixed_Asm_16, Convert__VecListOneDHWordIndexed2_2__AlignedMemory162_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListOneDHWordIndexed, MCK_AlignedMemory16, MCK__EXCLAIM_ }, },
14675 { 3770 /* vst1 */, ARM::VST1d16Twb_fixed, Convert__imm_95_0__AlignedMemory642_3__VecListThreeD1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListThreeD, MCK_AlignedMemory64, MCK__EXCLAIM_ }, },
14677 { 3770 /* vst1 */, ARM::VST1q32wb_fixed, Convert__imm_95_0__AlignedMemory64or1282_3__VecListDPair1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListDPair, MCK_AlignedMemory64or128, MCK__EXCLAIM_ }, },
14679 { 3770 /* vst1 */, ARM::VST1d32Qwb_fixed, Convert__imm_95_0__AlignedMemory64or128or2562_3__VecListFourD1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListFourD, MCK_AlignedMemory64or128or256, MCK__EXCLAIM_ }, },
14681 { 3770 /* vst1 */, ARM::VST1d32wb_fixed, Convert__imm_95_0__AlignedMemory642_3__VecListOneD1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListOneD, MCK_AlignedMemory64, MCK__EXCLAIM_ }, },
14683 { 3770 /* vst1 */, ARM::VST1LNdWB_fixed_Asm_32, Convert__VecListOneDWordIndexed2_2__AlignedMemory322_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListOneDWordIndexed, MCK_AlignedMemory32, MCK__EXCLAIM_ }, },
14685 { 3770 /* vst1 */, ARM::VST1d32Twb_fixed, Convert__imm_95_0__AlignedMemory642_3__VecListThreeD1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListThreeD, MCK_AlignedMemory64, MCK__EXCLAIM_ }, },
14687 { 3770 /* vst1 */, ARM::VST1q64wb_fixed, Convert__imm_95_0__AlignedMemory64or1282_3__VecListDPair1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_VecListDPair, MCK_AlignedMemory64or128, MCK__EXCLAIM_ }, },
14689 { 3770 /* vst1 */, ARM::VST1d64Qwb_fixed, Convert__imm_95_0__AlignedMemory64or128or2562_3__VecListFourD1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_VecListFourD, MCK_AlignedMemory64or128or256, MCK__EXCLAIM_ }, },
14691 { 3770 /* vst1 */, ARM::VST1d64wb_fixed, Convert__imm_95_0__AlignedMemory642_3__VecListOneD1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_VecListOneD, MCK_AlignedMemory64, MCK__EXCLAIM_ }, },
14693 { 3770 /* vst1 */, ARM::VST1d64Twb_fixed, Convert__imm_95_0__AlignedMemory642_3__VecListThreeD1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_64, MCK_VecListThreeD, MCK_AlignedMemory64, MCK__EXCLAIM_ }, },
14695 { 3770 /* vst1 */, ARM::VST1q8wb_fixed, Convert__imm_95_0__AlignedMemory64or1282_3__VecListDPair1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListDPair, MCK_AlignedMemory64or128, MCK__EXCLAIM_ }, },
14697 { 3770 /* vst1 */, ARM::VST1d8Qwb_fixed, Convert__imm_95_0__AlignedMemory64or128or2562_3__VecListFourD1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListFourD, MCK_AlignedMemory64or128or256, MCK__EXCLAIM_ }, },
14699 { 3770 /* vst1 */, ARM::VST1d8wb_fixed, Convert__imm_95_0__AlignedMemory642_3__VecListOneD1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListOneD, MCK_AlignedMemory64, MCK__EXCLAIM_ }, },
14701 { 3770 /* vst1 */, ARM::VST1LNdWB_fixed_Asm_8, Convert__VecListOneDByteIndexed2_2__AlignedMemoryNone2_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListOneDByteIndexed, MCK_AlignedMemoryNone, MCK__EXCLAIM_ }, },
14703 { 3770 /* vst1 */, ARM::VST1d8Twb_fixed, Convert__imm_95_0__AlignedMemory642_3__VecListThreeD1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListThreeD, MCK_AlignedMemory64, MCK__EXCLAIM_ }, },
14725 { 3775 /* vst2 */, ARM::VST2d16wb_fixed, Convert__imm_95_0__AlignedMemory64or1282_3__VecListDPair1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListDPair, MCK_AlignedMemory64or128, MCK__EXCLAIM_ }, },
14727 { 3775 /* vst2 */, ARM::VST2b16wb_fixed, Convert__imm_95_0__AlignedMemory64or1282_3__VecListDPairSpaced1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListDPairSpaced, MCK_AlignedMemory64or128, MCK__EXCLAIM_ }, },
14729 { 3775 /* vst2 */, ARM::VST2q16wb_fixed, Convert__imm_95_0__AlignedMemory64or128or2562_3__VecListFourD1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListFourD, MCK_AlignedMemory64or128or256, MCK__EXCLAIM_ }, },
14731 { 3775 /* vst2 */, ARM::VST2LNdWB_fixed_Asm_16, Convert__VecListTwoDHWordIndexed2_2__AlignedMemory322_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListTwoDHWordIndexed, MCK_AlignedMemory32, MCK__EXCLAIM_ }, },
14733 { 3775 /* vst2 */, ARM::VST2LNqWB_fixed_Asm_16, Convert__VecListTwoQHWordIndexed2_2__AlignedMemory322_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListTwoQHWordIndexed, MCK_AlignedMemory32, MCK__EXCLAIM_ }, },
14735 { 3775 /* vst2 */, ARM::VST2d32wb_fixed, Convert__imm_95_0__AlignedMemory64or1282_3__VecListDPair1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListDPair, MCK_AlignedMemory64or128, MCK__EXCLAIM_ }, },
14737 { 3775 /* vst2 */, ARM::VST2b32wb_fixed, Convert__imm_95_0__AlignedMemory64or1282_3__VecListDPairSpaced1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListDPairSpaced, MCK_AlignedMemory64or128, MCK__EXCLAIM_ }, },
14739 { 3775 /* vst2 */, ARM::VST2q32wb_fixed, Convert__imm_95_0__AlignedMemory64or128or2562_3__VecListFourD1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListFourD, MCK_AlignedMemory64or128or256, MCK__EXCLAIM_ }, },
14741 { 3775 /* vst2 */, ARM::VST2LNdWB_fixed_Asm_32, Convert__VecListTwoDWordIndexed2_2__AlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListTwoDWordIndexed, MCK_AlignedMemory64, MCK__EXCLAIM_ }, },
14743 { 3775 /* vst2 */, ARM::VST2LNqWB_fixed_Asm_32, Convert__VecListTwoQWordIndexed2_2__AlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListTwoQWordIndexed, MCK_AlignedMemory64, MCK__EXCLAIM_ }, },
14745 { 3775 /* vst2 */, ARM::VST2d8wb_fixed, Convert__imm_95_0__AlignedMemory64or1282_3__VecListDPair1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListDPair, MCK_AlignedMemory64or128, MCK__EXCLAIM_ }, },
14747 { 3775 /* vst2 */, ARM::VST2b8wb_fixed, Convert__imm_95_0__AlignedMemory64or1282_3__VecListDPairSpaced1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListDPairSpaced, MCK_AlignedMemory64or128, MCK__EXCLAIM_ }, },
14749 { 3775 /* vst2 */, ARM::VST2q8wb_fixed, Convert__imm_95_0__AlignedMemory64or128or2562_3__VecListFourD1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListFourD, MCK_AlignedMemory64or128or256, MCK__EXCLAIM_ }, },
14751 { 3775 /* vst2 */, ARM::VST2LNdWB_fixed_Asm_8, Convert__VecListTwoDByteIndexed2_2__AlignedMemory162_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListTwoDByteIndexed, MCK_AlignedMemory16, MCK__EXCLAIM_ }, },
14756 { 3780 /* vst20 */, ARM::MVE_VST20_16_wb, Convert__MemNoOffsetT2NoSp1_2__VecListTwoMQ1_1__Tie0_3_3, AMFBS_HasMVEInt, { MCK__DOT_16, MCK_VecListTwoMQ, MCK_MemNoOffsetT2NoSp, MCK__EXCLAIM_ }, },
14757 { 3780 /* vst20 */, ARM::MVE_VST20_32_wb, Convert__MemNoOffsetT2NoSp1_2__VecListTwoMQ1_1__Tie0_3_3, AMFBS_HasMVEInt, { MCK__DOT_32, MCK_VecListTwoMQ, MCK_MemNoOffsetT2NoSp, MCK__EXCLAIM_ }, },
14758 { 3780 /* vst20 */, ARM::MVE_VST20_8_wb, Convert__MemNoOffsetT2NoSp1_2__VecListTwoMQ1_1__Tie0_3_3, AMFBS_HasMVEInt, { MCK__DOT_8, MCK_VecListTwoMQ, MCK_MemNoOffsetT2NoSp, MCK__EXCLAIM_ }, },
14762 { 3786 /* vst21 */, ARM::MVE_VST21_16_wb, Convert__MemNoOffsetT2NoSp1_2__VecListTwoMQ1_1__Tie0_3_3, AMFBS_HasMVEInt, { MCK__DOT_16, MCK_VecListTwoMQ, MCK_MemNoOffsetT2NoSp, MCK__EXCLAIM_ }, },
14763 { 3786 /* vst21 */, ARM::MVE_VST21_32_wb, Convert__MemNoOffsetT2NoSp1_2__VecListTwoMQ1_1__Tie0_3_3, AMFBS_HasMVEInt, { MCK__DOT_32, MCK_VecListTwoMQ, MCK_MemNoOffsetT2NoSp, MCK__EXCLAIM_ }, },
14764 { 3786 /* vst21 */, ARM::MVE_VST21_8_wb, Convert__MemNoOffsetT2NoSp1_2__VecListTwoMQ1_1__Tie0_3_3, AMFBS_HasMVEInt, { MCK__DOT_8, MCK_VecListTwoMQ, MCK_MemNoOffsetT2NoSp, MCK__EXCLAIM_ }, },
14776 { 3792 /* vst3 */, ARM::VST3dWB_fixed_Asm_16, Convert__VecListThreeD1_2__AlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListThreeD, MCK_AlignedMemory64, MCK__EXCLAIM_ }, },
14778 { 3792 /* vst3 */, ARM::VST3LNdWB_fixed_Asm_16, Convert__VecListThreeDHWordIndexed2_2__AlignedMemoryNone2_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListThreeDHWordIndexed, MCK_AlignedMemoryNone, MCK__EXCLAIM_ }, },
14780 { 3792 /* vst3 */, ARM::VST3qWB_fixed_Asm_16, Convert__VecListThreeQ1_2__AlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListThreeQ, MCK_AlignedMemory64, MCK__EXCLAIM_ }, },
14782 { 3792 /* vst3 */, ARM::VST3LNqWB_fixed_Asm_16, Convert__VecListThreeQHWordIndexed2_2__AlignedMemoryNone2_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListThreeQHWordIndexed, MCK_AlignedMemoryNone, MCK__EXCLAIM_ }, },
14784 { 3792 /* vst3 */, ARM::VST3dWB_fixed_Asm_32, Convert__VecListThreeD1_2__AlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListThreeD, MCK_AlignedMemory64, MCK__EXCLAIM_ }, },
14786 { 3792 /* vst3 */, ARM::VST3LNdWB_fixed_Asm_32, Convert__VecListThreeDWordIndexed2_2__AlignedMemoryNone2_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListThreeDWordIndexed, MCK_AlignedMemoryNone, MCK__EXCLAIM_ }, },
14788 { 3792 /* vst3 */, ARM::VST3qWB_fixed_Asm_32, Convert__VecListThreeQ1_2__AlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListThreeQ, MCK_AlignedMemory64, MCK__EXCLAIM_ }, },
14790 { 3792 /* vst3 */, ARM::VST3LNqWB_fixed_Asm_32, Convert__VecListThreeQWordIndexed2_2__AlignedMemoryNone2_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListThreeQWordIndexed, MCK_AlignedMemoryNone, MCK__EXCLAIM_ }, },
14792 { 3792 /* vst3 */, ARM::VST3dWB_fixed_Asm_8, Convert__VecListThreeD1_2__AlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListThreeD, MCK_AlignedMemory64, MCK__EXCLAIM_ }, },
14794 { 3792 /* vst3 */, ARM::VST3LNdWB_fixed_Asm_8, Convert__VecListThreeDByteIndexed2_2__AlignedMemoryNone2_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListThreeDByteIndexed, MCK_AlignedMemoryNone, MCK__EXCLAIM_ }, },
14796 { 3792 /* vst3 */, ARM::VST3qWB_fixed_Asm_8, Convert__VecListThreeQ1_2__AlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListThreeQ, MCK_AlignedMemory64, MCK__EXCLAIM_ }, },
14821 { 3797 /* vst4 */, ARM::VST4dWB_fixed_Asm_16, Convert__VecListFourD1_2__AlignedMemory64or128or2562_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListFourD, MCK_AlignedMemory64or128or256, MCK__EXCLAIM_ }, },
14823 { 3797 /* vst4 */, ARM::VST4LNdWB_fixed_Asm_16, Convert__VecListFourDHWordIndexed2_2__AlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListFourDHWordIndexed, MCK_AlignedMemory64, MCK__EXCLAIM_ }, },
14825 { 3797 /* vst4 */, ARM::VST4qWB_fixed_Asm_16, Convert__VecListFourQ1_2__AlignedMemory64or128or2562_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListFourQ, MCK_AlignedMemory64or128or256, MCK__EXCLAIM_ }, },
14827 { 3797 /* vst4 */, ARM::VST4LNqWB_fixed_Asm_16, Convert__VecListFourQHWordIndexed2_2__AlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListFourQHWordIndexed, MCK_AlignedMemory64, MCK__EXCLAIM_ }, },
14829 { 3797 /* vst4 */, ARM::VST4dWB_fixed_Asm_32, Convert__VecListFourD1_2__AlignedMemory64or128or2562_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListFourD, MCK_AlignedMemory64or128or256, MCK__EXCLAIM_ }, },
14831 { 3797 /* vst4 */, ARM::VST4LNdWB_fixed_Asm_32, Convert__VecListFourDWordIndexed2_2__AlignedMemory64or1282_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListFourDWordIndexed, MCK_AlignedMemory64or128, MCK__EXCLAIM_ }, },
14833 { 3797 /* vst4 */, ARM::VST4qWB_fixed_Asm_32, Convert__VecListFourQ1_2__AlignedMemory64or128or2562_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListFourQ, MCK_AlignedMemory64or128or256, MCK__EXCLAIM_ }, },
14835 { 3797 /* vst4 */, ARM::VST4LNqWB_fixed_Asm_32, Convert__VecListFourQWordIndexed2_2__AlignedMemory64or1282_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListFourQWordIndexed, MCK_AlignedMemory64or128, MCK__EXCLAIM_ }, },
14837 { 3797 /* vst4 */, ARM::VST4dWB_fixed_Asm_8, Convert__VecListFourD1_2__AlignedMemory64or128or2562_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListFourD, MCK_AlignedMemory64or128or256, MCK__EXCLAIM_ }, },
14839 { 3797 /* vst4 */, ARM::VST4LNdWB_fixed_Asm_8, Convert__VecListFourDByteIndexed2_2__AlignedMemory322_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListFourDByteIndexed, MCK_AlignedMemory32, MCK__EXCLAIM_ }, },
14841 { 3797 /* vst4 */, ARM::VST4qWB_fixed_Asm_8, Convert__VecListFourQ1_2__AlignedMemory64or128or2562_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListFourQ, MCK_AlignedMemory64or128or256, MCK__EXCLAIM_ }, },
14858 { 3802 /* vst40 */, ARM::MVE_VST40_16_wb, Convert__MemNoOffsetT2NoSp1_2__VecListFourMQ1_1__Tie0_3_3, AMFBS_HasMVEInt, { MCK__DOT_16, MCK_VecListFourMQ, MCK_MemNoOffsetT2NoSp, MCK__EXCLAIM_ }, },
14859 { 3802 /* vst40 */, ARM::MVE_VST40_32_wb, Convert__MemNoOffsetT2NoSp1_2__VecListFourMQ1_1__Tie0_3_3, AMFBS_HasMVEInt, { MCK__DOT_32, MCK_VecListFourMQ, MCK_MemNoOffsetT2NoSp, MCK__EXCLAIM_ }, },
14860 { 3802 /* vst40 */, ARM::MVE_VST40_8_wb, Convert__MemNoOffsetT2NoSp1_2__VecListFourMQ1_1__Tie0_3_3, AMFBS_HasMVEInt, { MCK__DOT_8, MCK_VecListFourMQ, MCK_MemNoOffsetT2NoSp, MCK__EXCLAIM_ }, },
14864 { 3808 /* vst41 */, ARM::MVE_VST41_16_wb, Convert__MemNoOffsetT2NoSp1_2__VecListFourMQ1_1__Tie0_3_3, AMFBS_HasMVEInt, { MCK__DOT_16, MCK_VecListFourMQ, MCK_MemNoOffsetT2NoSp, MCK__EXCLAIM_ }, },
14865 { 3808 /* vst41 */, ARM::MVE_VST41_32_wb, Convert__MemNoOffsetT2NoSp1_2__VecListFourMQ1_1__Tie0_3_3, AMFBS_HasMVEInt, { MCK__DOT_32, MCK_VecListFourMQ, MCK_MemNoOffsetT2NoSp, MCK__EXCLAIM_ }, },
14866 { 3808 /* vst41 */, ARM::MVE_VST41_8_wb, Convert__MemNoOffsetT2NoSp1_2__VecListFourMQ1_1__Tie0_3_3, AMFBS_HasMVEInt, { MCK__DOT_8, MCK_VecListFourMQ, MCK_MemNoOffsetT2NoSp, MCK__EXCLAIM_ }, },
14870 { 3814 /* vst42 */, ARM::MVE_VST42_16_wb, Convert__MemNoOffsetT2NoSp1_2__VecListFourMQ1_1__Tie0_3_3, AMFBS_HasMVEInt, { MCK__DOT_16, MCK_VecListFourMQ, MCK_MemNoOffsetT2NoSp, MCK__EXCLAIM_ }, },
14871 { 3814 /* vst42 */, ARM::MVE_VST42_32_wb, Convert__MemNoOffsetT2NoSp1_2__VecListFourMQ1_1__Tie0_3_3, AMFBS_HasMVEInt, { MCK__DOT_32, MCK_VecListFourMQ, MCK_MemNoOffsetT2NoSp, MCK__EXCLAIM_ }, },
14872 { 3814 /* vst42 */, ARM::MVE_VST42_8_wb, Convert__MemNoOffsetT2NoSp1_2__VecListFourMQ1_1__Tie0_3_3, AMFBS_HasMVEInt, { MCK__DOT_8, MCK_VecListFourMQ, MCK_MemNoOffsetT2NoSp, MCK__EXCLAIM_ }, },
14876 { 3820 /* vst43 */, ARM::MVE_VST43_16_wb, Convert__MemNoOffsetT2NoSp1_2__VecListFourMQ1_1__Tie0_3_3, AMFBS_HasMVEInt, { MCK__DOT_16, MCK_VecListFourMQ, MCK_MemNoOffsetT2NoSp, MCK__EXCLAIM_ }, },
14877 { 3820 /* vst43 */, ARM::MVE_VST43_32_wb, Convert__MemNoOffsetT2NoSp1_2__VecListFourMQ1_1__Tie0_3_3, AMFBS_HasMVEInt, { MCK__DOT_32, MCK_VecListFourMQ, MCK_MemNoOffsetT2NoSp, MCK__EXCLAIM_ }, },
14878 { 3820 /* vst43 */, ARM::MVE_VST43_8_wb, Convert__MemNoOffsetT2NoSp1_2__VecListFourMQ1_1__Tie0_3_3, AMFBS_HasMVEInt, { MCK__DOT_8, MCK_VecListFourMQ, MCK_MemNoOffsetT2NoSp, MCK__EXCLAIM_ }, },
14879 { 3826 /* vstmdb */, ARM::VSTMDDB_UPD, Convert__Reg1_1__Tie0_2_2__CondCode2_0__DPRRegList1_3, AMFBS_HasFPRegs, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_, MCK_DPRRegList }, },
14880 { 3826 /* vstmdb */, ARM::VSTMSDB_UPD, Convert__Reg1_1__Tie0_2_2__CondCode2_0__SPRRegList1_3, AMFBS_HasFPRegs, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_, MCK_SPRRegList }, },
14883 { 3833 /* vstmia */, ARM::VSTMDIA_UPD, Convert__Reg1_1__Tie0_2_2__CondCode2_0__DPRRegList1_3, AMFBS_HasFPRegs, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_, MCK_DPRRegList }, },
14884 { 3833 /* vstmia */, ARM::VSTMSIA_UPD, Convert__Reg1_1__Tie0_2_2__CondCode2_0__SPRRegList1_3, AMFBS_HasFPRegs, { MCK_CondCode, MCK_GPR, MCK__EXCLAIM_, MCK_SPRRegList }, },
14896 { 3840 /* vstr */, ARM::VSTR_FPCXTNS_pre, Convert__imm_95_0__MemImm7s4Offset2_2__CondCode2_0, AMFBS_HasV8_1MMainline_Has8MSecExt, { MCK_CondCode, MCK_FPCXTNS, MCK_MemImm7s4Offset, MCK__EXCLAIM_ }, },
14898 { 3840 /* vstr */, ARM::VSTR_FPCXTS_pre, Convert__imm_95_0__MemImm7s4Offset2_2__CondCode2_0, AMFBS_HasV8_1MMainline_Has8MSecExt, { MCK_CondCode, MCK_FPCXTS, MCK_MemImm7s4Offset, MCK__EXCLAIM_ }, },
14900 { 3840 /* vstr */, ARM::VSTR_FPSCR_pre, Convert__imm_95_0__MemImm7s4Offset2_2__CondCode2_0, AMFBS_HasFPRegs_HasV8_1MMainline, { MCK_CondCode, MCK_FPSCR, MCK_MemImm7s4Offset, MCK__EXCLAIM_ }, },
14902 { 3840 /* vstr */, ARM::VSTR_FPSCR_NZCVQC_pre, Convert__imm_95_0__MemImm7s4Offset2_2__CondCode2_0, AMFBS_HasFPRegs_HasV8_1MMainline, { MCK_CondCode, MCK_FPSCR_NZCVQC, MCK_MemImm7s4Offset, MCK__EXCLAIM_ }, },
14904 { 3840 /* vstr */, ARM::VSTR_P0_pre, Convert__imm_95_0__imm_95_0__MemImm7s4Offset2_2__CondCode2_0, AMFBS_HasV8_1MMainline_HasMVEInt, { MCK_CondCode, MCK_P0, MCK_MemImm7s4Offset, MCK__EXCLAIM_ }, },
14906 { 3840 /* vstr */, ARM::VSTR_VPR_pre, Convert__imm_95_0__MemImm7s4Offset2_2__CondCode2_0, AMFBS_HasV8_1MMainline_HasMVEInt, { MCK_CondCode, MCK_VCCR, MCK_MemImm7s4Offset, MCK__EXCLAIM_ }, },
14915 { 3845 /* vstrb */, ARM::MVE_VSTRB16_pre, Convert__imm_95_0__Reg1_2__TMemImm7Shift0Offset2_3__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_16, MCK_MQPR, MCK_TMemImm7Shift0Offset, MCK__EXCLAIM_ }, },
14917 { 3845 /* vstrb */, ARM::MVE_VSTRB32_pre, Convert__imm_95_0__Reg1_2__TMemImm7Shift0Offset2_3__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_32, MCK_MQPR, MCK_TMemImm7Shift0Offset, MCK__EXCLAIM_ }, },
14918 { 3845 /* vstrb */, ARM::MVE_VSTRBU8_pre, Convert__imm_95_0__Reg1_2__MemImm7Shift0OffsetWB2_3__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_8, MCK_MQPR, MCK_MemImm7Shift0OffsetWB, MCK__EXCLAIM_ }, },
14923 { 3851 /* vstrd */, ARM::MVE_VSTRD64_qi_pre, Convert__imm_95_0__Reg1_2__MemRegQS3Offset2_3__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_64, MCK_MQPR, MCK_MemRegQS3Offset, MCK__EXCLAIM_ }, },
14930 { 3857 /* vstrh */, ARM::MVE_VSTRHU16_pre, Convert__imm_95_0__Reg1_2__MemImm7Shift1OffsetWB2_3__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_16, MCK_MQPR, MCK_MemImm7Shift1OffsetWB, MCK__EXCLAIM_ }, },
14933 { 3857 /* vstrh */, ARM::MVE_VSTRH32_pre, Convert__imm_95_0__Reg1_2__TMemImm7Shift1Offset2_3__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_32, MCK_MQPR, MCK_TMemImm7Shift1Offset, MCK__EXCLAIM_ }, },
14938 { 3863 /* vstrw */, ARM::MVE_VSTRWU32_pre, Convert__imm_95_0__Reg1_2__MemImm7Shift2OffsetWB2_3__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_32, MCK_MQPR, MCK_MemImm7Shift2OffsetWB, MCK__EXCLAIM_ }, },
14940 { 3863 /* vstrw */, ARM::MVE_VSTRW32_qi_pre, Convert__imm_95_0__Reg1_2__MemRegQS2Offset2_3__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_32, MCK_MQPR, MCK_MemRegQS2Offset, MCK__EXCLAIM_ }, },