reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced

References

 6278         return MCK__DOT_s32;	 // ".s32"
 6338   case MCK__DOT_s32:
 9364   case MCK__DOT_s32: return "MCK__DOT_s32";
11551   { 1960 /* vaba */, ARM::VABAsv4i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR, MCK_QPR }, },
11552   { 1960 /* vaba */, ARM::VABAsv2i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR, MCK_DPR }, },
11562   { 1965 /* vabal */, ARM::VABALsv2i64, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_DPR, MCK_DPR }, },
11568   { 1971 /* vabav */, ARM::MVE_VABAVs32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_rGPR, MCK_MQPR, MCK_MQPR }, },
11575   { 1977 /* vabd */, ARM::VABDsv4i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR }, },
11576   { 1977 /* vabd */, ARM::VABDsv2i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR }, },
11591   { 1977 /* vabd */, ARM::VABDsv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR, MCK_QPR }, },
11592   { 1977 /* vabd */, ARM::VABDsv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR, MCK_DPR }, },
11606   { 1977 /* vabd */, ARM::MVE_VABDs32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
11614   { 1982 /* vabdl */, ARM::VABDLsv2i64, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_DPR, MCK_DPR }, },
11621   { 1988 /* vabs */, ARM::VABSv4i32, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR }, },
11622   { 1988 /* vabs */, ARM::VABSv2i32, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR }, },
11633   { 1988 /* vabs */, ARM::MVE_VABSs32, Convert__Reg1_2__Reg1_3__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s32, MCK_MQPR, MCK_MQPR }, },
11715   { 2040 /* vaddl */, ARM::VADDLsv2i64, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_DPR, MCK_DPR }, },
11720   { 2046 /* vaddlv */, ARM::MVE_VADDLVs32no_acc, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_tGPREven, MCK_tGPROdd, MCK_MQPR }, },
11722   { 2053 /* vaddlva */, ARM::MVE_VADDLVs32acc, Convert__Reg1_2__Reg1_3__Tie0_1_1__Tie1_1_1__Reg1_4__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_tGPREven, MCK_tGPROdd, MCK_MQPR }, },
11725   { 2061 /* vaddv */, ARM::MVE_VADDVs32no_acc, Convert__Reg1_2__Reg1_3__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_tGPREven, MCK_MQPR }, },
11731   { 2067 /* vaddva */, ARM::MVE_VADDVs32acc, Convert__Reg1_2__Tie0_1_1__Reg1_3__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_tGPREven, MCK_MQPR }, },
11737   { 2074 /* vaddw */, ARM::VADDWsv2i64, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_DPR }, },
11743   { 2074 /* vaddw */, ARM::VADDWsv2i64, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR, MCK_DPR }, },
11780   { 2080 /* vand */, ARM::MVE_VAND, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
11814   { 2085 /* vbic */, ARM::MVE_VBIC, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
11910   { 2122 /* vcge */, ARM::VCGEzv4i32, Convert__Reg1_2__Reg1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK__HASH_0 }, },
11911   { 2122 /* vcge */, ARM::VCGEsv4i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR }, },
11912   { 2122 /* vcge */, ARM::VCGEzv2i32, Convert__Reg1_2__Reg1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK__HASH_0 }, },
11913   { 2122 /* vcge */, ARM::VCGEsv2i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR }, },
11936   { 2122 /* vcge */, ARM::VCGEzv4i32, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR, MCK__HASH_0 }, },
11937   { 2122 /* vcge */, ARM::VCGEsv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR, MCK_QPR }, },
11938   { 2122 /* vcge */, ARM::VCGEzv2i32, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR, MCK__HASH_0 }, },
11939   { 2122 /* vcge */, ARM::VCGEsv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR, MCK_DPR }, },
11962   { 2127 /* vcgt */, ARM::VCGTzv4i32, Convert__Reg1_2__Reg1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK__HASH_0 }, },
11963   { 2127 /* vcgt */, ARM::VCGTsv4i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR }, },
11964   { 2127 /* vcgt */, ARM::VCGTzv2i32, Convert__Reg1_2__Reg1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK__HASH_0 }, },
11965   { 2127 /* vcgt */, ARM::VCGTsv2i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR }, },
11988   { 2127 /* vcgt */, ARM::VCGTzv4i32, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR, MCK__HASH_0 }, },
11989   { 2127 /* vcgt */, ARM::VCGTsv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR, MCK_QPR }, },
11990   { 2127 /* vcgt */, ARM::VCGTzv2i32, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR, MCK__HASH_0 }, },
11991   { 2127 /* vcgt */, ARM::VCGTsv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR, MCK_DPR }, },
12012   { 2132 /* vcle */, ARM::VCLEzv4i32, Convert__Reg1_2__Reg1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK__HASH_0 }, },
12013   { 2132 /* vcle */, ARM::VCLEzv2i32, Convert__Reg1_2__Reg1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK__HASH_0 }, },
12024   { 2132 /* vcle */, ARM::VCLEzv4i32, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR, MCK__HASH_0 }, },
12025   { 2132 /* vcle */, ARM::VCGEsv4i32, Convert__Reg1_2__Reg1_4__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR, MCK_QPR }, },
12026   { 2132 /* vcle */, ARM::VCLEzv2i32, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR, MCK__HASH_0 }, },
12027   { 2132 /* vcle */, ARM::VCGEsv2i32, Convert__Reg1_2__Reg1_4__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR, MCK_DPR }, },
12048   { 2137 /* vcls */, ARM::VCLSv4i32, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR }, },
12049   { 2137 /* vcls */, ARM::VCLSv2i32, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR }, },
12053   { 2137 /* vcls */, ARM::MVE_VCLSs32, Convert__Reg1_2__Reg1_3__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s32, MCK_MQPR, MCK_MQPR }, },
12057   { 2142 /* vclt */, ARM::VCLTzv4i32, Convert__Reg1_2__Reg1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK__HASH_0 }, },
12058   { 2142 /* vclt */, ARM::VCLTzv2i32, Convert__Reg1_2__Reg1_2__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK__HASH_0 }, },
12069   { 2142 /* vclt */, ARM::VCLTzv4i32, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR, MCK__HASH_0 }, },
12070   { 2142 /* vclt */, ARM::VCGTsv4i32, Convert__Reg1_2__Reg1_4__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR, MCK_QPR }, },
12071   { 2142 /* vclt */, ARM::VCLTzv2i32, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR, MCK__HASH_0 }, },
12072   { 2142 /* vclt */, ARM::VCGTsv2i32, Convert__Reg1_2__Reg1_4__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR, MCK_DPR }, },
12118   { 2158 /* vcmp */, ARM::MVE_VCMPs32, Convert__imm_95_0__Reg1_3__Reg1_4__CondCodeRestrictedS1_2__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_CondCodeRestrictedS, MCK_MQPR, MCK_MQPR }, },
12119   { 2158 /* vcmp */, ARM::MVE_VCMPs32r, Convert__imm_95_0__Reg1_3__Reg1_4__CondCodeRestrictedS1_2__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_CondCodeRestrictedS, MCK_MQPR, MCK_GPRwithZR }, },
12154   { 2185 /* vcvt */, ARM::VCVTf2sq, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK__DOT_f32, MCK_QPR, MCK_QPR }, },
12155   { 2185 /* vcvt */, ARM::VCVTf2sd, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK__DOT_f32, MCK_DPR, MCK_DPR }, },
12156   { 2185 /* vcvt */, ARM::VTOSIZS, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK__DOT_s32, MCK__DOT_f32, MCK_HPR, MCK_HPR }, },
12157   { 2185 /* vcvt */, ARM::VTOSIZD, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasVFP2_HasDPVFP, { MCK_CondCode, MCK__DOT_s32, MCK__DOT_f64, MCK_HPR, MCK_DPR }, },
12158   { 2185 /* vcvt */, ARM::VTOSIZH, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_s32, MCK__DOT_f16, MCK_HPR, MCK_HPR }, },
12166   { 2185 /* vcvt */, ARM::VCVTs2fq, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK__DOT_s32, MCK_QPR, MCK_QPR }, },
12167   { 2185 /* vcvt */, ARM::VCVTs2fd, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK__DOT_s32, MCK_DPR, MCK_DPR }, },
12168   { 2185 /* vcvt */, ARM::VSITOS, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK__DOT_f32, MCK__DOT_s32, MCK_HPR, MCK_HPR }, },
12174   { 2185 /* vcvt */, ARM::VSITOD, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasVFP2_HasDPVFP, { MCK_CondCode, MCK__DOT_f64, MCK__DOT_s32, MCK_DPR, MCK_HPR }, },
12179   { 2185 /* vcvt */, ARM::VSITOH, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK__DOT_s32, MCK_HPR, MCK_HPR }, },
12185   { 2185 /* vcvt */, ARM::MVE_VCVTs32f32z, Convert__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_s32, MCK__DOT_f32, MCK_MQPR, MCK_MQPR }, },
12188   { 2185 /* vcvt */, ARM::MVE_VCVTf32s32n, Convert__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_f32, MCK__DOT_s32, MCK_MQPR, MCK_MQPR }, },
12199   { 2185 /* vcvt */, ARM::VCVTf2sq, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK__DOT_f32, MCK_QPR, MCK_QPR, MCK__HASH_0 }, },
12200   { 2185 /* vcvt */, ARM::VCVTf2xsq, Convert__Reg1_3__Reg1_4__Imm1_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK__DOT_f32, MCK_QPR, MCK_QPR, MCK_Imm }, },
12201   { 2185 /* vcvt */, ARM::VCVTf2sd, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK__DOT_f32, MCK_DPR, MCK_DPR, MCK__HASH_0 }, },
12202   { 2185 /* vcvt */, ARM::VCVTf2xsd, Convert__Reg1_3__Reg1_4__Imm1_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK__DOT_f32, MCK_DPR, MCK_DPR, MCK_Imm }, },
12203   { 2185 /* vcvt */, ARM::VTOSLS, Convert__Reg1_3__Tie0_4_5__FBits321_5__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK__DOT_s32, MCK__DOT_f32, MCK_HPR, MCK_HPR, MCK_FBits32 }, },
12204   { 2185 /* vcvt */, ARM::VTOSLD, Convert__Reg1_3__Tie0_4_5__FBits321_5__CondCode2_0, AMFBS_HasVFP2_HasDPVFP, { MCK_CondCode, MCK__DOT_s32, MCK__DOT_f64, MCK_DPR, MCK_DPR, MCK_FBits32 }, },
12205   { 2185 /* vcvt */, ARM::VTOSLH, Convert__Reg1_3__Tie0_4_5__FBits321_5__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_s32, MCK__DOT_f16, MCK_HPR, MCK_HPR, MCK_FBits32 }, },
12221   { 2185 /* vcvt */, ARM::VCVTs2fq, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK__DOT_s32, MCK_QPR, MCK_QPR, MCK__HASH_0 }, },
12222   { 2185 /* vcvt */, ARM::VCVTxs2fq, Convert__Reg1_3__Reg1_4__Imm1_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK__DOT_s32, MCK_QPR, MCK_QPR, MCK_Imm }, },
12223   { 2185 /* vcvt */, ARM::VCVTs2fd, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK__DOT_s32, MCK_DPR, MCK_DPR, MCK__HASH_0 }, },
12224   { 2185 /* vcvt */, ARM::VCVTxs2fd, Convert__Reg1_3__Reg1_4__Imm1_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_f32, MCK__DOT_s32, MCK_DPR, MCK_DPR, MCK_Imm }, },
12225   { 2185 /* vcvt */, ARM::VSLTOS, Convert__Reg1_3__Tie0_4_5__FBits321_5__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK__DOT_f32, MCK__DOT_s32, MCK_HPR, MCK_HPR, MCK_FBits32 }, },
12233   { 2185 /* vcvt */, ARM::VSLTOD, Convert__Reg1_3__Tie0_4_5__FBits321_5__CondCode2_0, AMFBS_HasVFP2_HasDPVFP, { MCK_CondCode, MCK__DOT_f64, MCK__DOT_s32, MCK_DPR, MCK_DPR, MCK_FBits32 }, },
12241   { 2185 /* vcvt */, ARM::VSLTOH, Convert__Reg1_3__Tie0_4_5__FBits321_5__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK__DOT_s32, MCK_HPR, MCK_HPR, MCK_FBits32 }, },
12249   { 2185 /* vcvt */, ARM::MVE_VCVTs32f32_fix, Convert__Reg1_3__Reg1_4__MVEVcvtImm321_5__VPTPredR3_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_s32, MCK__DOT_f32, MCK_MQPR, MCK_MQPR, MCK_MVEVcvtImm32 }, },
12252   { 2185 /* vcvt */, ARM::MVE_VCVTf32s32_fix, Convert__Reg1_3__Reg1_4__MVEVcvtImm321_5__VPTPredR3_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_f32, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_MVEVcvtImm32 }, },
12258   { 2190 /* vcvta */, ARM::VCVTANSQf, Convert__Reg1_2__Reg1_3, AMFBS_HasV8_HasNEON, { MCK__DOT_s32, MCK__DOT_f32, MCK_QPR, MCK_QPR }, },
12259   { 2190 /* vcvta */, ARM::VCVTANSDf, Convert__Reg1_2__Reg1_3, AMFBS_HasV8_HasNEON, { MCK__DOT_s32, MCK__DOT_f32, MCK_DPR, MCK_DPR }, },
12260   { 2190 /* vcvta */, ARM::VCVTASS, Convert__Reg1_2__Reg1_3, AMFBS_HasFPARMv8, { MCK__DOT_s32, MCK__DOT_f32, MCK_HPR, MCK_HPR }, },
12261   { 2190 /* vcvta */, ARM::VCVTASD, Convert__Reg1_2__Reg1_3, AMFBS_HasFPARMv8_HasDPVFP, { MCK__DOT_s32, MCK__DOT_f64, MCK_HPR, MCK_DPR }, },
12262   { 2190 /* vcvta */, ARM::VCVTASH, Convert__Reg1_2__Reg1_3, AMFBS_HasFullFP16, { MCK__DOT_s32, MCK__DOT_f16, MCK_HPR, MCK_HPR }, },
12271   { 2190 /* vcvta */, ARM::MVE_VCVTs32f32a, Convert__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_s32, MCK__DOT_f32, MCK_MQPR, MCK_MQPR }, },
12282   { 2202 /* vcvtm */, ARM::VCVTMNSQf, Convert__Reg1_2__Reg1_3, AMFBS_HasV8_HasNEON, { MCK__DOT_s32, MCK__DOT_f32, MCK_QPR, MCK_QPR }, },
12283   { 2202 /* vcvtm */, ARM::VCVTMNSDf, Convert__Reg1_2__Reg1_3, AMFBS_HasV8_HasNEON, { MCK__DOT_s32, MCK__DOT_f32, MCK_DPR, MCK_DPR }, },
12284   { 2202 /* vcvtm */, ARM::VCVTMSS, Convert__Reg1_2__Reg1_3, AMFBS_HasFPARMv8, { MCK__DOT_s32, MCK__DOT_f32, MCK_HPR, MCK_HPR }, },
12285   { 2202 /* vcvtm */, ARM::VCVTMSD, Convert__Reg1_2__Reg1_3, AMFBS_HasFPARMv8_HasDPVFP, { MCK__DOT_s32, MCK__DOT_f64, MCK_HPR, MCK_DPR }, },
12286   { 2202 /* vcvtm */, ARM::VCVTMSH, Convert__Reg1_2__Reg1_3, AMFBS_HasFullFP16, { MCK__DOT_s32, MCK__DOT_f16, MCK_HPR, MCK_HPR }, },
12295   { 2202 /* vcvtm */, ARM::MVE_VCVTs32f32m, Convert__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_s32, MCK__DOT_f32, MCK_MQPR, MCK_MQPR }, },
12300   { 2208 /* vcvtn */, ARM::VCVTNNSQf, Convert__Reg1_2__Reg1_3, AMFBS_HasV8_HasNEON, { MCK__DOT_s32, MCK__DOT_f32, MCK_QPR, MCK_QPR }, },
12301   { 2208 /* vcvtn */, ARM::VCVTNNSDf, Convert__Reg1_2__Reg1_3, AMFBS_HasV8_HasNEON, { MCK__DOT_s32, MCK__DOT_f32, MCK_DPR, MCK_DPR }, },
12302   { 2208 /* vcvtn */, ARM::VCVTNSS, Convert__Reg1_2__Reg1_3, AMFBS_HasFPARMv8, { MCK__DOT_s32, MCK__DOT_f32, MCK_HPR, MCK_HPR }, },
12303   { 2208 /* vcvtn */, ARM::VCVTNSD, Convert__Reg1_2__Reg1_3, AMFBS_HasFPARMv8_HasDPVFP, { MCK__DOT_s32, MCK__DOT_f64, MCK_HPR, MCK_DPR }, },
12304   { 2208 /* vcvtn */, ARM::VCVTNSH, Convert__Reg1_2__Reg1_3, AMFBS_HasFullFP16, { MCK__DOT_s32, MCK__DOT_f16, MCK_HPR, MCK_HPR }, },
12313   { 2208 /* vcvtn */, ARM::MVE_VCVTs32f32n, Convert__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_s32, MCK__DOT_f32, MCK_MQPR, MCK_MQPR }, },
12318   { 2214 /* vcvtp */, ARM::VCVTPNSQf, Convert__Reg1_2__Reg1_3, AMFBS_HasV8_HasNEON, { MCK__DOT_s32, MCK__DOT_f32, MCK_QPR, MCK_QPR }, },
12319   { 2214 /* vcvtp */, ARM::VCVTPNSDf, Convert__Reg1_2__Reg1_3, AMFBS_HasV8_HasNEON, { MCK__DOT_s32, MCK__DOT_f32, MCK_DPR, MCK_DPR }, },
12320   { 2214 /* vcvtp */, ARM::VCVTPSS, Convert__Reg1_2__Reg1_3, AMFBS_HasFPARMv8, { MCK__DOT_s32, MCK__DOT_f32, MCK_HPR, MCK_HPR }, },
12321   { 2214 /* vcvtp */, ARM::VCVTPSD, Convert__Reg1_2__Reg1_3, AMFBS_HasFPARMv8_HasDPVFP, { MCK__DOT_s32, MCK__DOT_f64, MCK_HPR, MCK_DPR }, },
12322   { 2214 /* vcvtp */, ARM::VCVTPSH, Convert__Reg1_2__Reg1_3, AMFBS_HasFullFP16, { MCK__DOT_s32, MCK__DOT_f16, MCK_HPR, MCK_HPR }, },
12331   { 2214 /* vcvtp */, ARM::MVE_VCVTs32f32p, Convert__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_s32, MCK__DOT_f32, MCK_MQPR, MCK_MQPR }, },
12334   { 2220 /* vcvtr */, ARM::VTOSIRS, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK__DOT_s32, MCK__DOT_f32, MCK_HPR, MCK_HPR }, },
12335   { 2220 /* vcvtr */, ARM::VTOSIRD, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasVFP2_HasDPVFP, { MCK_CondCode, MCK__DOT_s32, MCK__DOT_f64, MCK_HPR, MCK_DPR }, },
12336   { 2220 /* vcvtr */, ARM::VTOSIRH, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_s32, MCK__DOT_f16, MCK_HPR, MCK_HPR }, },
12395   { 2255 /* veor */, ARM::MVE_VEOR, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
12457   { 2305 /* vhadd */, ARM::VHADDsv4i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR }, },
12458   { 2305 /* vhadd */, ARM::VHADDsv2i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR }, },
12469   { 2305 /* vhadd */, ARM::VHADDsv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR, MCK_QPR }, },
12470   { 2305 /* vhadd */, ARM::VHADDsv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR, MCK_DPR }, },
12481   { 2305 /* vhadd */, ARM::MVE_VHADDs32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
12482   { 2305 /* vhadd */, ARM::MVE_VHADD_qr_s32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_rGPR }, },
12492   { 2311 /* vhcadd */, ARM::MVE_VHCADDs32, Convert__Reg1_2__Reg1_3__Reg1_4__ComplexRotationOdd1_5__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_MQPR, MCK_ComplexRotationOdd }, },
12496   { 2318 /* vhsub */, ARM::VHSUBsv4i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR }, },
12497   { 2318 /* vhsub */, ARM::VHSUBsv2i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR }, },
12508   { 2318 /* vhsub */, ARM::VHSUBsv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR, MCK_QPR }, },
12509   { 2318 /* vhsub */, ARM::VHSUBsv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR, MCK_DPR }, },
12520   { 2318 /* vhsub */, ARM::MVE_VHSUBs32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
12521   { 2318 /* vhsub */, ARM::MVE_VHSUB_qr_s32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_rGPR }, },
12537   { 2342 /* vjcvt */, ARM::VJCVT, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasFPARMv8_HasV8_3a, { MCK_CondCode, MCK__DOT_s32, MCK__DOT_f64, MCK_HPR, MCK_DPR }, },
12896   { 2423 /* vldrb */, ARM::MVE_VLDRBS32_rq, Convert__Reg1_2__MemRegRQS0Offset2_3__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_MQPR, MCK_MemRegRQS0Offset }, },
12897   { 2423 /* vldrb */, ARM::MVE_VLDRBS32, Convert__Reg1_2__TMemImm7Shift0Offset2_3__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_MQPR, MCK_TMemImm7Shift0Offset }, },
12906   { 2423 /* vldrb */, ARM::MVE_VLDRBS32_post, Convert__MemNoOffsetT1_3__Reg1_2__Tie0_4_4__Imm7Shift01_4__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_MQPR, MCK_MemNoOffsetT, MCK_Imm7Shift0 }, },
12907   { 2423 /* vldrb */, ARM::MVE_VLDRBS32_pre, Convert__imm_95_0__Reg1_2__TMemImm7Shift0Offset2_3__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_MQPR, MCK_TMemImm7Shift0Offset, MCK__EXCLAIM_ }, },
12918   { 2435 /* vldrh */, ARM::MVE_VLDRHS32_rq_u, Convert__Reg1_2__MemRegRQS0Offset2_3__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_MQPR, MCK_MemRegRQS0Offset }, },
12919   { 2435 /* vldrh */, ARM::MVE_VLDRHS32_rq, Convert__Reg1_2__MemRegRQS1Offset2_3__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_MQPR, MCK_MemRegRQS1Offset }, },
12920   { 2435 /* vldrh */, ARM::MVE_VLDRHS32, Convert__Reg1_2__TMemImm7Shift1Offset2_3__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_MQPR, MCK_TMemImm7Shift1Offset }, },
12927   { 2435 /* vldrh */, ARM::MVE_VLDRHS32_post, Convert__MemNoOffsetT1_3__Reg1_2__Tie0_4_4__Imm7Shift11_4__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_MQPR, MCK_MemNoOffsetT, MCK_Imm7Shift1 }, },
12928   { 2435 /* vldrh */, ARM::MVE_VLDRHS32_pre, Convert__imm_95_0__Reg1_2__TMemImm7Shift1Offset2_3__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_MQPR, MCK_TMemImm7Shift1Offset, MCK__EXCLAIM_ }, },
12944   { 2459 /* vmax */, ARM::VMAXsv4i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR }, },
12945   { 2459 /* vmax */, ARM::VMAXsv2i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR }, },
12960   { 2459 /* vmax */, ARM::VMAXsv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR, MCK_QPR }, },
12961   { 2459 /* vmax */, ARM::VMAXsv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR, MCK_DPR }, },
12975   { 2459 /* vmax */, ARM::MVE_VMAXs32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
12981   { 2464 /* vmaxa */, ARM::MVE_VMAXAs32, Convert__Reg1_2__Tie0_1_1__Reg1_3__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_MQPR, MCK_MQPR }, },
12984   { 2470 /* vmaxav */, ARM::MVE_VMAXAVs32, Convert__Reg1_2__Tie0_3_3__Reg1_3__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_rGPR, MCK_MQPR }, },
13002   { 2509 /* vmaxv */, ARM::MVE_VMAXVs32, Convert__Reg1_2__Tie0_3_3__Reg1_3__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_rGPR, MCK_MQPR }, },
13009   { 2515 /* vmin */, ARM::VMINsv4i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR }, },
13010   { 2515 /* vmin */, ARM::VMINsv2i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR }, },
13025   { 2515 /* vmin */, ARM::VMINsv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR, MCK_QPR }, },
13026   { 2515 /* vmin */, ARM::VMINsv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR, MCK_DPR }, },
13040   { 2515 /* vmin */, ARM::MVE_VMINs32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13046   { 2520 /* vmina */, ARM::MVE_VMINAs32, Convert__Reg1_2__Tie0_1_1__Reg1_3__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_MQPR, MCK_MQPR }, },
13049   { 2526 /* vminav */, ARM::MVE_VMINAVs32, Convert__Reg1_2__Tie0_3_3__Reg1_3__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_rGPR, MCK_MQPR }, },
13067   { 2565 /* vminv */, ARM::MVE_VMINVs32, Convert__Reg1_2__Tie0_3_3__Reg1_3__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_rGPR, MCK_MQPR }, },
13086   { 2571 /* vmla */, ARM::MVE_VMLA_qr_s32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_rGPR }, },
13100   { 2576 /* vmladav */, ARM::MVE_VMLADAVs32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_tGPREven, MCK_MQPR, MCK_MQPR }, },
13106   { 2584 /* vmladava */, ARM::MVE_VMLADAVas32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_tGPREven, MCK_MQPR, MCK_MQPR }, },
13112   { 2593 /* vmladavax */, ARM::MVE_VMLADAVaxs32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_tGPREven, MCK_MQPR, MCK_MQPR }, },
13115   { 2603 /* vmladavx */, ARM::MVE_VMLADAVxs32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_tGPREven, MCK_MQPR, MCK_MQPR }, },
13118   { 2612 /* vmlal */, ARM::VMLALsv2i64, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_DPR, MCK_DPR }, },
13124   { 2612 /* vmlal */, ARM::VMLALslsv2i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VectorIndex321_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_DPR, MCK_DPR_VFP2, MCK_VectorIndex32 }, },
13128   { 2618 /* vmlaldav */, ARM::MVE_VMLALDAVs32, Convert__Reg1_2__Reg1_3__Reg1_4__Reg1_5__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_tGPREven, MCK_tGPROdd, MCK_MQPR, MCK_MQPR }, },
13132   { 2627 /* vmlaldava */, ARM::MVE_VMLALDAVas32, Convert__Reg1_2__Reg1_3__Tie0_1_1__Tie1_1_1__Reg1_4__Reg1_5__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_tGPREven, MCK_tGPROdd, MCK_MQPR, MCK_MQPR }, },
13136   { 2637 /* vmlaldavax */, ARM::MVE_VMLALDAVaxs32, Convert__Reg1_2__Reg1_3__Tie0_1_1__Tie1_1_1__Reg1_4__Reg1_5__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_tGPREven, MCK_tGPROdd, MCK_MQPR, MCK_MQPR }, },
13138   { 2648 /* vmlaldavx */, ARM::MVE_VMLALDAVxs32, Convert__Reg1_2__Reg1_3__Reg1_4__Reg1_5__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_tGPREven, MCK_tGPROdd, MCK_MQPR, MCK_MQPR }, },
13140   { 2658 /* vmlalv */, ARM::MVE_VMLALDAVs32, Convert__Reg1_2__Reg1_3__Reg1_4__Reg1_5__VPTPredN2_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredN, MCK__DOT_s32, MCK_tGPREven, MCK_tGPROdd, MCK_MQPR, MCK_MQPR }, },
13144   { 2665 /* vmlalva */, ARM::MVE_VMLALDAVas32, Convert__Reg1_2__Reg1_3__Tie0_3_3__Tie1_4_4__Reg1_4__Reg1_5__VPTPredN2_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredN, MCK__DOT_s32, MCK_tGPREven, MCK_tGPROdd, MCK_MQPR, MCK_MQPR }, },
13148   { 2673 /* vmlas */, ARM::MVE_VMLAS_qr_s32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_rGPR }, },
13154   { 2679 /* vmlav */, ARM::MVE_VMLADAVs32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredN2_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredN, MCK__DOT_s32, MCK_tGPREven, MCK_MQPR, MCK_MQPR }, },
13160   { 2685 /* vmlava */, ARM::MVE_VMLADAVas32, Convert__Reg1_2__Tie0_3_3__Reg1_3__Reg1_4__VPTPredN2_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredN, MCK__DOT_s32, MCK_tGPREven, MCK_MQPR, MCK_MQPR }, },
13187   { 2697 /* vmlsdav */, ARM::MVE_VMLSDAVs32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_tGPREven, MCK_MQPR, MCK_MQPR }, },
13190   { 2705 /* vmlsdava */, ARM::MVE_VMLSDAVas32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_tGPREven, MCK_MQPR, MCK_MQPR }, },
13193   { 2714 /* vmlsdavax */, ARM::MVE_VMLSDAVaxs32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_tGPREven, MCK_MQPR, MCK_MQPR }, },
13196   { 2724 /* vmlsdavx */, ARM::MVE_VMLSDAVxs32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_tGPREven, MCK_MQPR, MCK_MQPR }, },
13199   { 2733 /* vmlsl */, ARM::VMLSLsv2i64, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_DPR, MCK_DPR }, },
13205   { 2733 /* vmlsl */, ARM::VMLSLslsv2i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VectorIndex321_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_DPR, MCK_DPR_VFP2, MCK_VectorIndex32 }, },
13209   { 2739 /* vmlsldav */, ARM::MVE_VMLSLDAVs32, Convert__Reg1_2__Reg1_3__Reg1_4__Reg1_5__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_tGPREven, MCK_tGPROdd, MCK_MQPR, MCK_MQPR }, },
13211   { 2748 /* vmlsldava */, ARM::MVE_VMLSLDAVas32, Convert__Reg1_2__Reg1_3__Tie0_1_1__Tie1_1_1__Reg1_4__Reg1_5__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_tGPREven, MCK_tGPROdd, MCK_MQPR, MCK_MQPR }, },
13213   { 2758 /* vmlsldavax */, ARM::MVE_VMLSLDAVaxs32, Convert__Reg1_2__Reg1_3__Tie0_1_1__Tie1_1_1__Reg1_4__Reg1_5__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_tGPREven, MCK_tGPROdd, MCK_MQPR, MCK_MQPR }, },
13215   { 2769 /* vmlsldavx */, ARM::MVE_VMLSLDAVxs32, Convert__Reg1_2__Reg1_3__Reg1_4__Reg1_5__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_tGPREven, MCK_tGPROdd, MCK_MQPR, MCK_MQPR }, },
13299   { 2784 /* vmovl */, ARM::VMOVLsv2i64, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_DPR }, },
13401   { 2845 /* vmulh */, ARM::MVE_VMULHs32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13408   { 2851 /* vmull */, ARM::VMULLsv2i64, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_DPR, MCK_DPR }, },
13415   { 2851 /* vmull */, ARM::VMULLslsv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__VectorIndex321_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_DPR, MCK_DPR_VFP2, MCK_VectorIndex32 }, },
13419   { 2857 /* vmullb */, ARM::MVE_VMULLs32bh, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13427   { 2864 /* vmullt */, ARM::MVE_VMULLs32th, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13467   { 2876 /* vneg */, ARM::VNEGs32q, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR }, },
13468   { 2876 /* vneg */, ARM::VNEGs32d, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR }, },
13479   { 2876 /* vneg */, ARM::MVE_VNEGs32, Convert__Reg1_2__Reg1_3__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s32, MCK_MQPR, MCK_MQPR }, },
13502   { 2899 /* vorn */, ARM::MVE_VORN, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13544   { 2904 /* vorr */, ARM::MVE_VORR, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13556   { 2909 /* vpadal */, ARM::VPADALsv4i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR }, },
13557   { 2909 /* vpadal */, ARM::VPADALsv2i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR }, },
13578   { 2922 /* vpaddl */, ARM::VPADDLsv4i32, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR }, },
13579   { 2922 /* vpaddl */, ARM::VPADDLsv2i32, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR }, },
13589   { 2929 /* vpmax */, ARM::VPMAXs32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR }, },
13597   { 2929 /* vpmax */, ARM::VPMAXs32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR, MCK_DPR }, },
13605   { 2935 /* vpmin */, ARM::VPMINs32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR }, },
13613   { 2935 /* vpmin */, ARM::VPMINs32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR, MCK_DPR }, },
13633   { 2952 /* vpsel */, ARM::MVE_VPSEL, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredN2_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredN, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13646   { 2963 /* vpt */, ARM::MVE_VPTv4s32, Convert__ITMask1_0__Reg1_3__Reg1_4__CondCodeRestrictedS1_2, AMFBS_HasMVEInt, { MCK_ITMask, MCK__DOT_s32, MCK_CondCodeRestrictedS, MCK_MQPR, MCK_MQPR }, },
13647   { 2963 /* vpt */, ARM::MVE_VPTv4s32r, Convert__ITMask1_0__Reg1_3__Reg1_4__CondCodeRestrictedS1_2, AMFBS_HasMVEInt, { MCK_ITMask, MCK__DOT_s32, MCK_CondCodeRestrictedS, MCK_MQPR, MCK_GPRwithZR }, },
13678   { 2973 /* vqabs */, ARM::VQABSv4i32, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR }, },
13679   { 2973 /* vqabs */, ARM::VQABSv2i32, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR }, },
13683   { 2973 /* vqabs */, ARM::MVE_VQABSs32, Convert__Reg1_2__Reg1_3__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s32, MCK_MQPR, MCK_MQPR }, },
13687   { 2979 /* vqadd */, ARM::VQADDsv4i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR }, },
13688   { 2979 /* vqadd */, ARM::VQADDsv2i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR }, },
13703   { 2979 /* vqadd */, ARM::VQADDsv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR, MCK_QPR }, },
13704   { 2979 /* vqadd */, ARM::VQADDsv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR, MCK_DPR }, },
13719   { 2979 /* vqadd */, ARM::MVE_VQADDs32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13720   { 2979 /* vqadd */, ARM::MVE_VQADD_qr_s32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_rGPR }, },
13730   { 2985 /* vqdmladh */, ARM::MVE_VQDMLADHs32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13733   { 2994 /* vqdmladhx */, ARM::MVE_VQDMLADHXs32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13736   { 3004 /* vqdmlah */, ARM::MVE_VQDMLAH_qrs32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_rGPR }, },
13739   { 3012 /* vqdmlal */, ARM::VQDMLALv2i64, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_DPR, MCK_DPR }, },
13741   { 3012 /* vqdmlal */, ARM::VQDMLALslv2i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VectorIndex321_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_DPR, MCK_DPR_VFP2, MCK_VectorIndex32 }, },
13743   { 3020 /* vqdmlash */, ARM::MVE_VQDMLASH_qrs32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_rGPR }, },
13746   { 3029 /* vqdmlsdh */, ARM::MVE_VQDMLSDHs32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13749   { 3038 /* vqdmlsdhx */, ARM::MVE_VQDMLSDHXs32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13752   { 3048 /* vqdmlsl */, ARM::VQDMLSLv2i64, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_DPR, MCK_DPR }, },
13754   { 3048 /* vqdmlsl */, ARM::VQDMLSLslv2i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VectorIndex321_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_DPR, MCK_DPR_VFP2, MCK_VectorIndex32 }, },
13757   { 3056 /* vqdmulh */, ARM::VQDMULHv4i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR }, },
13758   { 3056 /* vqdmulh */, ARM::VQDMULHv2i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR }, },
13761   { 3056 /* vqdmulh */, ARM::VQDMULHv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR, MCK_QPR }, },
13762   { 3056 /* vqdmulh */, ARM::VQDMULHv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR, MCK_DPR }, },
13765   { 3056 /* vqdmulh */, ARM::MVE_VQDMULHi32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13766   { 3056 /* vqdmulh */, ARM::MVE_VQDMULH_qr_s32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_rGPR }, },
13771   { 3056 /* vqdmulh */, ARM::VQDMULHslv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__VectorIndex321_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR, MCK_DPR_VFP2, MCK_VectorIndex32 }, },
13772   { 3056 /* vqdmulh */, ARM::VQDMULHslv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__VectorIndex321_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR, MCK_DPR_VFP2, MCK_VectorIndex32 }, },
13774   { 3064 /* vqdmull */, ARM::VQDMULLv2i64, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_DPR, MCK_DPR }, },
13776   { 3064 /* vqdmull */, ARM::VQDMULLslv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__VectorIndex321_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_DPR, MCK_DPR_VFP2, MCK_VectorIndex32 }, },
13779   { 3072 /* vqdmullb */, ARM::MVE_VQDMULLs32bh, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13780   { 3072 /* vqdmullb */, ARM::MVE_VQDMULL_qr_s32bh, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_rGPR }, },
13783   { 3081 /* vqdmullt */, ARM::MVE_VQDMULLs32th, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13784   { 3081 /* vqdmullt */, ARM::MVE_VQDMULL_qr_s32th, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_rGPR }, },
13786   { 3090 /* vqmovn */, ARM::VQMOVNsv4i16, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_QPR }, },
13792   { 3097 /* vqmovnb */, ARM::MVE_VQMOVNs32bh, Convert__Reg1_2__Tie0_1_1__Reg1_3__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_MQPR, MCK_MQPR }, },
13796   { 3105 /* vqmovnt */, ARM::MVE_VQMOVNs32th, Convert__Reg1_2__Tie0_1_1__Reg1_3__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_MQPR, MCK_MQPR }, },
13800   { 3113 /* vqmovun */, ARM::VQMOVNsuv4i16, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_QPR }, },
13803   { 3121 /* vqmovunb */, ARM::MVE_VQMOVUNs32bh, Convert__Reg1_2__Tie0_1_1__Reg1_3__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_MQPR, MCK_MQPR }, },
13805   { 3130 /* vqmovunt */, ARM::MVE_VQMOVUNs32th, Convert__Reg1_2__Tie0_1_1__Reg1_3__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_MQPR, MCK_MQPR }, },
13808   { 3139 /* vqneg */, ARM::VQNEGv4i32, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR }, },
13809   { 3139 /* vqneg */, ARM::VQNEGv2i32, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR }, },
13813   { 3139 /* vqneg */, ARM::MVE_VQNEGs32, Convert__Reg1_2__Reg1_3__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s32, MCK_MQPR, MCK_MQPR }, },
13816   { 3145 /* vqrdmladh */, ARM::MVE_VQRDMLADHs32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13819   { 3155 /* vqrdmladhx */, ARM::MVE_VQRDMLADHXs32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13823   { 3166 /* vqrdmlah */, ARM::VQRDMLAHv4i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON_HasV8_1a, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR, MCK_QPR }, },
13824   { 3166 /* vqrdmlah */, ARM::VQRDMLAHv2i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON_HasV8_1a, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR, MCK_DPR }, },
13826   { 3166 /* vqrdmlah */, ARM::MVE_VQRDMLAH_qrs32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_rGPR }, },
13830   { 3166 /* vqrdmlah */, ARM::VQRDMLAHslv4i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VectorIndex321_5__CondCode2_0, AMFBS_HasNEON_HasV8_1a, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR, MCK_DPR_VFP2, MCK_VectorIndex32 }, },
13831   { 3166 /* vqrdmlah */, ARM::VQRDMLAHslv2i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VectorIndex321_5__CondCode2_0, AMFBS_HasNEON_HasV8_1a, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR, MCK_DPR_VFP2, MCK_VectorIndex32 }, },
13833   { 3175 /* vqrdmlash */, ARM::MVE_VQRDMLASH_qrs32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_rGPR }, },
13836   { 3185 /* vqrdmlsdh */, ARM::MVE_VQRDMLSDHs32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13839   { 3195 /* vqrdmlsdhx */, ARM::MVE_VQRDMLSDHXs32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13843   { 3206 /* vqrdmlsh */, ARM::VQRDMLSHv4i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON_HasV8_1a, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR, MCK_QPR }, },
13844   { 3206 /* vqrdmlsh */, ARM::VQRDMLSHv2i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON_HasV8_1a, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR, MCK_DPR }, },
13847   { 3206 /* vqrdmlsh */, ARM::VQRDMLSHslv4i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VectorIndex321_5__CondCode2_0, AMFBS_HasNEON_HasV8_1a, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR, MCK_DPR_VFP2, MCK_VectorIndex32 }, },
13848   { 3206 /* vqrdmlsh */, ARM::VQRDMLSHslv2i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__VectorIndex321_5__CondCode2_0, AMFBS_HasNEON_HasV8_1a, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR, MCK_DPR_VFP2, MCK_VectorIndex32 }, },
13851   { 3215 /* vqrdmulh */, ARM::VQRDMULHv4i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR }, },
13852   { 3215 /* vqrdmulh */, ARM::VQRDMULHv2i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR }, },
13855   { 3215 /* vqrdmulh */, ARM::VQRDMULHv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR, MCK_QPR }, },
13856   { 3215 /* vqrdmulh */, ARM::VQRDMULHv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR, MCK_DPR }, },
13859   { 3215 /* vqrdmulh */, ARM::MVE_VQRDMULHi32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13860   { 3215 /* vqrdmulh */, ARM::MVE_VQRDMULH_qr_s32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_rGPR }, },
13865   { 3215 /* vqrdmulh */, ARM::VQRDMULHslv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__VectorIndex321_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR, MCK_DPR_VFP2, MCK_VectorIndex32 }, },
13866   { 3215 /* vqrdmulh */, ARM::VQRDMULHslv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__VectorIndex321_5__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR, MCK_DPR_VFP2, MCK_VectorIndex32 }, },
13869   { 3224 /* vqrshl */, ARM::VQRSHLsv4i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR }, },
13870   { 3224 /* vqrshl */, ARM::VQRSHLsv2i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR }, },
13884   { 3224 /* vqrshl */, ARM::MVE_VQRSHL_qrs32, Convert__Reg1_2__Tie0_1_1__Reg1_3__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_MQPR, MCK_rGPR }, },
13891   { 3224 /* vqrshl */, ARM::VQRSHLsv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR, MCK_QPR }, },
13892   { 3224 /* vqrshl */, ARM::VQRSHLsv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR, MCK_DPR }, },
13906   { 3224 /* vqrshl */, ARM::MVE_VQRSHL_by_vecs32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13912   { 3231 /* vqrshrn */, ARM::VQRSHRNsv4i16, Convert__Reg1_2__Reg1_3__ShrImm161_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_QPR, MCK_ShrImm16 }, },
13918   { 3239 /* vqrshrnb */, ARM::MVE_VQRSHRNbhs32, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm161_4__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_ShrImm16 }, },
13922   { 3248 /* vqrshrnt */, ARM::MVE_VQRSHRNths32, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm161_4__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_ShrImm16 }, },
13926   { 3257 /* vqrshrun */, ARM::VQRSHRUNv4i16, Convert__Reg1_2__Reg1_3__ShrImm161_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_QPR, MCK_ShrImm16 }, },
13929   { 3266 /* vqrshrunb */, ARM::MVE_VQRSHRUNs32bh, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm161_4__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_ShrImm16 }, },
13931   { 3276 /* vqrshrunt */, ARM::MVE_VQRSHRUNs32th, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm161_4__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_ShrImm16 }, },
13936   { 3286 /* vqshl */, ARM::VQSHLsv4i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR }, },
13937   { 3286 /* vqshl */, ARM::VQSHLsiv4i32, Convert__Reg1_2__Reg1_2__Imm1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_Imm }, },
13938   { 3286 /* vqshl */, ARM::VQSHLsv2i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR }, },
13939   { 3286 /* vqshl */, ARM::VQSHLsiv2i32, Convert__Reg1_2__Reg1_2__Imm1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_Imm }, },
13965   { 3286 /* vqshl */, ARM::MVE_VQSHL_qrs32, Convert__Reg1_2__Tie0_1_1__Reg1_3__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_MQPR, MCK_rGPR }, },
13974   { 3286 /* vqshl */, ARM::VQSHLsv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR, MCK_QPR }, },
13975   { 3286 /* vqshl */, ARM::VQSHLsiv4i32, Convert__Reg1_2__Reg1_3__Imm1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR, MCK_Imm }, },
13976   { 3286 /* vqshl */, ARM::VQSHLsv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR, MCK_DPR }, },
13977   { 3286 /* vqshl */, ARM::VQSHLsiv2i32, Convert__Reg1_2__Reg1_3__Imm1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR, MCK_Imm }, },
14004   { 3286 /* vqshl */, ARM::MVE_VQSHL_by_vecs32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
14005   { 3286 /* vqshl */, ARM::MVE_VSLIimms32, Convert__Reg1_2__Reg1_3__Imm0_311_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_Imm0_31 }, },
14016   { 3292 /* vqshlu */, ARM::VQSHLsuv4i32, Convert__Reg1_2__Reg1_2__Imm1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_Imm }, },
14017   { 3292 /* vqshlu */, ARM::VQSHLsuv2i32, Convert__Reg1_2__Reg1_2__Imm1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_Imm }, },
14024   { 3292 /* vqshlu */, ARM::VQSHLsuv4i32, Convert__Reg1_2__Reg1_3__Imm1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR, MCK_Imm }, },
14025   { 3292 /* vqshlu */, ARM::VQSHLsuv2i32, Convert__Reg1_2__Reg1_3__Imm1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR, MCK_Imm }, },
14031   { 3292 /* vqshlu */, ARM::MVE_VQSHLU_imms32, Convert__Reg1_2__Reg1_3__Imm0_311_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_Imm0_31 }, },
14034   { 3299 /* vqshrn */, ARM::VQSHRNsv4i16, Convert__Reg1_2__Reg1_3__ShrImm161_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_QPR, MCK_ShrImm16 }, },
14040   { 3306 /* vqshrnb */, ARM::MVE_VQSHRNbhs32, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm161_4__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_ShrImm16 }, },
14044   { 3314 /* vqshrnt */, ARM::MVE_VQSHRNths32, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm161_4__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_ShrImm16 }, },
14048   { 3322 /* vqshrun */, ARM::VQSHRUNv4i16, Convert__Reg1_2__Reg1_3__ShrImm161_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_QPR, MCK_ShrImm16 }, },
14051   { 3330 /* vqshrunb */, ARM::MVE_VQSHRUNs32bh, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm161_4__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_ShrImm16 }, },
14053   { 3339 /* vqshrunt */, ARM::MVE_VQSHRUNs32th, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm161_4__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_ShrImm16 }, },
14056   { 3348 /* vqsub */, ARM::VQSUBsv4i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR }, },
14057   { 3348 /* vqsub */, ARM::VQSUBsv2i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR }, },
14072   { 3348 /* vqsub */, ARM::VQSUBsv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR, MCK_QPR }, },
14073   { 3348 /* vqsub */, ARM::VQSUBsv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR, MCK_DPR }, },
14088   { 3348 /* vqsub */, ARM::MVE_VQSUBs32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
14089   { 3348 /* vqsub */, ARM::MVE_VQSUB_qr_s32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_rGPR }, },
14135   { 3397 /* vrhadd */, ARM::VRHADDsv4i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR }, },
14136   { 3397 /* vrhadd */, ARM::VRHADDsv2i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR }, },
14147   { 3397 /* vrhadd */, ARM::VRHADDsv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR, MCK_QPR }, },
14148   { 3397 /* vrhadd */, ARM::VRHADDsv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR, MCK_DPR }, },
14158   { 3397 /* vrhadd */, ARM::MVE_VRHADDs32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
14261   { 3453 /* vrmlaldavh */, ARM::MVE_VRMLALDAVHs32, Convert__Reg1_2__Reg1_3__Reg1_4__Reg1_5__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_tGPREven, MCK_tGPROdd, MCK_MQPR, MCK_MQPR }, },
14263   { 3464 /* vrmlaldavha */, ARM::MVE_VRMLALDAVHas32, Convert__Reg1_2__Reg1_3__Tie0_1_1__Tie1_1_1__Reg1_4__Reg1_5__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_tGPREven, MCK_tGPROdd, MCK_MQPR, MCK_MQPR }, },
14265   { 3476 /* vrmlaldavhax */, ARM::MVE_VRMLALDAVHaxs32, Convert__Reg1_2__Reg1_3__Tie0_1_1__Tie1_1_1__Reg1_4__Reg1_5__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_tGPREven, MCK_tGPROdd, MCK_MQPR, MCK_MQPR }, },
14266   { 3489 /* vrmlaldavhx */, ARM::MVE_VRMLALDAVHxs32, Convert__Reg1_2__Reg1_3__Reg1_4__Reg1_5__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_tGPREven, MCK_tGPROdd, MCK_MQPR, MCK_MQPR }, },
14267   { 3501 /* vrmlalvh */, ARM::MVE_VRMLALDAVHs32, Convert__Reg1_2__Reg1_3__Reg1_4__Reg1_5__VPTPredN2_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredN, MCK__DOT_s32, MCK_tGPREven, MCK_tGPROdd, MCK_MQPR, MCK_MQPR }, },
14269   { 3510 /* vrmlalvha */, ARM::MVE_VRMLALDAVHas32, Convert__Reg1_2__Reg1_3__Tie0_3_3__Tie1_4_4__Reg1_4__Reg1_5__VPTPredN2_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredN, MCK__DOT_s32, MCK_tGPREven, MCK_tGPROdd, MCK_MQPR, MCK_MQPR }, },
14271   { 3520 /* vrmlsldavh */, ARM::MVE_VRMLSLDAVHs32, Convert__Reg1_2__Reg1_3__Reg1_4__Reg1_5__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_tGPREven, MCK_tGPROdd, MCK_MQPR, MCK_MQPR }, },
14272   { 3531 /* vrmlsldavha */, ARM::MVE_VRMLSLDAVHas32, Convert__Reg1_2__Reg1_3__Tie0_1_1__Tie1_1_1__Reg1_4__Reg1_5__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_tGPREven, MCK_tGPROdd, MCK_MQPR, MCK_MQPR }, },
14273   { 3543 /* vrmlsldavhax */, ARM::MVE_VRMLSLDAVHaxs32, Convert__Reg1_2__Reg1_3__Tie0_1_1__Tie1_1_1__Reg1_4__Reg1_5__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_tGPREven, MCK_tGPROdd, MCK_MQPR, MCK_MQPR }, },
14274   { 3556 /* vrmlsldavhx */, ARM::MVE_VRMLSLDAVHxs32, Convert__Reg1_2__Reg1_3__Reg1_4__Reg1_5__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_tGPREven, MCK_tGPROdd, MCK_MQPR, MCK_MQPR }, },
14276   { 3568 /* vrmulh */, ARM::MVE_VRMULHs32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
14283   { 3575 /* vrshl */, ARM::VRSHLsv4i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR }, },
14284   { 3575 /* vrshl */, ARM::VRSHLsv2i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR }, },
14298   { 3575 /* vrshl */, ARM::MVE_VRSHL_qrs32, Convert__Reg1_2__Tie0_1_1__Reg1_3__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_MQPR, MCK_rGPR }, },
14305   { 3575 /* vrshl */, ARM::VRSHLsv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR, MCK_QPR }, },
14306   { 3575 /* vrshl */, ARM::VRSHLsv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR, MCK_DPR }, },
14320   { 3575 /* vrshl */, ARM::MVE_VRSHL_by_vecs32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
14327   { 3581 /* vrshr */, ARM::VRSHRsv4i32, Convert__Reg1_2__Reg1_2__ShrImm321_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_ShrImm32 }, },
14328   { 3581 /* vrshr */, ARM::VRSHRsv2i32, Convert__Reg1_2__Reg1_2__ShrImm321_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_ShrImm32 }, },
14343   { 3581 /* vrshr */, ARM::VRSHRsv4i32, Convert__Reg1_2__Reg1_3__ShrImm321_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR, MCK_ShrImm32 }, },
14344   { 3581 /* vrshr */, ARM::VRSHRsv2i32, Convert__Reg1_2__Reg1_3__ShrImm321_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR, MCK_ShrImm32 }, },
14358   { 3581 /* vrshr */, ARM::MVE_VRSHR_imms32, Convert__Reg1_2__Reg1_3__ShrImm321_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_ShrImm32 }, },
14386   { 3626 /* vrsra */, ARM::VRSRAsv4i32, Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm321_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_ShrImm32 }, },
14387   { 3626 /* vrsra */, ARM::VRSRAsv2i32, Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm321_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_ShrImm32 }, },
14402   { 3626 /* vrsra */, ARM::VRSRAsv4i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm321_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR, MCK_ShrImm32 }, },
14403   { 3626 /* vrsra */, ARM::VRSRAsv2i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm321_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR, MCK_ShrImm32 }, },
14441   { 3693 /* vshl */, ARM::VSHLsv4i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR }, },
14442   { 3693 /* vshl */, ARM::VSHLsv2i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR }, },
14464   { 3693 /* vshl */, ARM::MVE_VSHL_qrs32, Convert__Reg1_2__Tie0_1_1__Reg1_3__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_MQPR, MCK_rGPR }, },
14471   { 3693 /* vshl */, ARM::VSHLsv4i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR, MCK_QPR }, },
14472   { 3693 /* vshl */, ARM::VSHLsv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR, MCK_DPR }, },
14494   { 3693 /* vshl */, ARM::MVE_VSHL_by_vecs32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
14504   { 3704 /* vshll */, ARM::VSHLLsv2i64, Convert__Reg1_2__Reg1_3__Imm1_311_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_DPR, MCK_Imm1_31 }, },
14530   { 3724 /* vshr */, ARM::VSHRsv4i32, Convert__Reg1_2__Reg1_2__ShrImm321_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_ShrImm32 }, },
14531   { 3724 /* vshr */, ARM::VSHRsv2i32, Convert__Reg1_2__Reg1_2__ShrImm321_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_ShrImm32 }, },
14546   { 3724 /* vshr */, ARM::VSHRsv4i32, Convert__Reg1_2__Reg1_3__ShrImm321_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR, MCK_ShrImm32 }, },
14547   { 3724 /* vshr */, ARM::VSHRsv2i32, Convert__Reg1_2__Reg1_3__ShrImm321_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR, MCK_ShrImm32 }, },
14561   { 3724 /* vshr */, ARM::MVE_VSHR_imms32, Convert__Reg1_2__Reg1_3__ShrImm321_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_ShrImm32 }, },
14599   { 3760 /* vsra */, ARM::VSRAsv4i32, Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm321_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_ShrImm32 }, },
14600   { 3760 /* vsra */, ARM::VSRAsv2i32, Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm321_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_ShrImm32 }, },
14615   { 3760 /* vsra */, ARM::VSRAsv4i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm321_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR, MCK_ShrImm32 }, },
14616   { 3760 /* vsra */, ARM::VSRAsv2i32, Convert__Reg1_2__Tie0_1_1__Reg1_3__ShrImm321_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_DPR, MCK_DPR, MCK_ShrImm32 }, },
14985   { 3881 /* vsubl */, ARM::VSUBLsv2i64, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_DPR, MCK_DPR }, },
14991   { 3887 /* vsubw */, ARM::VSUBWsv2i64, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_DPR }, },
14997   { 3887 /* vsubw */, ARM::VSUBWsv2i64, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_s32, MCK_QPR, MCK_QPR, MCK_DPR }, },