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reference to multiple definitions → definitions
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References

gen/lib/Target/ARM/ARMGenAsmMatcher.inc
 8397   case MCK_VecListThreeQAllLanes: {
 9657   case MCK_VecListThreeQAllLanes: return "MCK_VecListThreeQAllLanes";
12694   { 2370 /* vld3 */, ARM::VLD3DUPqAsm_16, Convert__VecListThreeQAllLanes1_2__DupAlignedMemoryNone2_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListThreeQAllLanes, MCK_DupAlignedMemoryNone }, },
12700   { 2370 /* vld3 */, ARM::VLD3DUPqAsm_32, Convert__VecListThreeQAllLanes1_2__DupAlignedMemoryNone2_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListThreeQAllLanes, MCK_DupAlignedMemoryNone }, },
12706   { 2370 /* vld3 */, ARM::VLD3DUPqAsm_8, Convert__VecListThreeQAllLanes1_2__DupAlignedMemoryNone2_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListThreeQAllLanes, MCK_DupAlignedMemoryNone }, },
12714   { 2370 /* vld3 */, ARM::VLD3DUPqWB_fixed_Asm_16, Convert__VecListThreeQAllLanes1_2__DupAlignedMemoryNone2_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListThreeQAllLanes, MCK_DupAlignedMemoryNone, MCK__EXCLAIM_ }, },
12715   { 2370 /* vld3 */, ARM::VLD3DUPqWB_register_Asm_16, Convert__VecListThreeQAllLanes1_2__DupAlignedMemoryNone2_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListThreeQAllLanes, MCK_DupAlignedMemoryNone, MCK_rGPR }, },
12726   { 2370 /* vld3 */, ARM::VLD3DUPqWB_fixed_Asm_32, Convert__VecListThreeQAllLanes1_2__DupAlignedMemoryNone2_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListThreeQAllLanes, MCK_DupAlignedMemoryNone, MCK__EXCLAIM_ }, },
12727   { 2370 /* vld3 */, ARM::VLD3DUPqWB_register_Asm_32, Convert__VecListThreeQAllLanes1_2__DupAlignedMemoryNone2_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListThreeQAllLanes, MCK_DupAlignedMemoryNone, MCK_rGPR }, },
12738   { 2370 /* vld3 */, ARM::VLD3DUPqWB_fixed_Asm_8, Convert__VecListThreeQAllLanes1_2__DupAlignedMemoryNone2_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListThreeQAllLanes, MCK_DupAlignedMemoryNone, MCK__EXCLAIM_ }, },
12739   { 2370 /* vld3 */, ARM::VLD3DUPqWB_register_Asm_8, Convert__VecListThreeQAllLanes1_2__DupAlignedMemoryNone2_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListThreeQAllLanes, MCK_DupAlignedMemoryNone, MCK_rGPR }, },
15844   { 2370 /* vld3 */, 4 /* 2 */, MCK_VecListThreeQAllLanes, AMFBS_HasNEON },
15850   { 2370 /* vld3 */, 4 /* 2 */, MCK_VecListThreeQAllLanes, AMFBS_HasNEON },
15856   { 2370 /* vld3 */, 4 /* 2 */, MCK_VecListThreeQAllLanes, AMFBS_HasNEON },
15864   { 2370 /* vld3 */, 4 /* 2 */, MCK_VecListThreeQAllLanes, AMFBS_HasNEON },
15865   { 2370 /* vld3 */, 4 /* 2 */, MCK_VecListThreeQAllLanes, AMFBS_HasNEON },
15876   { 2370 /* vld3 */, 4 /* 2 */, MCK_VecListThreeQAllLanes, AMFBS_HasNEON },
15877   { 2370 /* vld3 */, 4 /* 2 */, MCK_VecListThreeQAllLanes, AMFBS_HasNEON },
15888   { 2370 /* vld3 */, 4 /* 2 */, MCK_VecListThreeQAllLanes, AMFBS_HasNEON },
15889   { 2370 /* vld3 */, 4 /* 2 */, MCK_VecListThreeQAllLanes, AMFBS_HasNEON },
16301   case MCK_VecListThreeQAllLanes: