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reference to multiple definitions → definitions
unreferenced

References

gen/lib/Target/ARM/ARMGenAsmMatcher.inc
 8299   case MCK_VecListFourQAllLanes: {
 9643   case MCK_VecListFourQAllLanes: return "MCK_VecListFourQAllLanes";
12769   { 2375 /* vld4 */, ARM::VLD4DUPqAsm_16, Convert__VecListFourQAllLanes1_2__DupAlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListFourQAllLanes, MCK_DupAlignedMemory64 }, },
12775   { 2375 /* vld4 */, ARM::VLD4DUPqAsm_32, Convert__VecListFourQAllLanes1_2__DupAlignedMemory64or1282_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListFourQAllLanes, MCK_DupAlignedMemory64or128 }, },
12781   { 2375 /* vld4 */, ARM::VLD4DUPqAsm_8, Convert__VecListFourQAllLanes1_2__DupAlignedMemory322_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListFourQAllLanes, MCK_DupAlignedMemory32 }, },
12789   { 2375 /* vld4 */, ARM::VLD4DUPqWB_fixed_Asm_16, Convert__VecListFourQAllLanes1_2__DupAlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListFourQAllLanes, MCK_DupAlignedMemory64, MCK__EXCLAIM_ }, },
12790   { 2375 /* vld4 */, ARM::VLD4DUPqWB_register_Asm_16, Convert__VecListFourQAllLanes1_2__DupAlignedMemory642_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListFourQAllLanes, MCK_DupAlignedMemory64, MCK_rGPR }, },
12801   { 2375 /* vld4 */, ARM::VLD4DUPqWB_fixed_Asm_32, Convert__VecListFourQAllLanes1_2__DupAlignedMemory64or1282_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListFourQAllLanes, MCK_DupAlignedMemory64or128, MCK__EXCLAIM_ }, },
12802   { 2375 /* vld4 */, ARM::VLD4DUPqWB_register_Asm_32, Convert__VecListFourQAllLanes1_2__DupAlignedMemory64or1282_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListFourQAllLanes, MCK_DupAlignedMemory64or128, MCK_rGPR }, },
12813   { 2375 /* vld4 */, ARM::VLD4DUPqWB_fixed_Asm_8, Convert__VecListFourQAllLanes1_2__DupAlignedMemory322_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListFourQAllLanes, MCK_DupAlignedMemory32, MCK__EXCLAIM_ }, },
12814   { 2375 /* vld4 */, ARM::VLD4DUPqWB_register_Asm_8, Convert__VecListFourQAllLanes1_2__DupAlignedMemory322_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListFourQAllLanes, MCK_DupAlignedMemory32, MCK_rGPR }, },
15895   { 2375 /* vld4 */, 4 /* 2 */, MCK_VecListFourQAllLanes, AMFBS_HasNEON },
15901   { 2375 /* vld4 */, 4 /* 2 */, MCK_VecListFourQAllLanes, AMFBS_HasNEON },
15907   { 2375 /* vld4 */, 4 /* 2 */, MCK_VecListFourQAllLanes, AMFBS_HasNEON },
15915   { 2375 /* vld4 */, 4 /* 2 */, MCK_VecListFourQAllLanes, AMFBS_HasNEON },
15916   { 2375 /* vld4 */, 4 /* 2 */, MCK_VecListFourQAllLanes, AMFBS_HasNEON },
15927   { 2375 /* vld4 */, 4 /* 2 */, MCK_VecListFourQAllLanes, AMFBS_HasNEON },
15928   { 2375 /* vld4 */, 4 /* 2 */, MCK_VecListFourQAllLanes, AMFBS_HasNEON },
15939   { 2375 /* vld4 */, 4 /* 2 */, MCK_VecListFourQAllLanes, AMFBS_HasNEON },
15940   { 2375 /* vld4 */, 4 /* 2 */, MCK_VecListFourQAllLanes, AMFBS_HasNEON },
16273   case MCK_VecListFourQAllLanes: