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reference to multiple definitions → definitions
unreferenced

References

gen/lib/Target/ARM/ARMGenAsmMatcher.inc
 8264   case MCK_VecListFourDAllLanes: {
 9638   case MCK_VecListFourDAllLanes: return "MCK_VecListFourDAllLanes";
12766   { 2375 /* vld4 */, ARM::VLD4DUPdAsm_16, Convert__VecListFourDAllLanes1_2__DupAlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListFourDAllLanes, MCK_DupAlignedMemory64 }, },
12772   { 2375 /* vld4 */, ARM::VLD4DUPdAsm_32, Convert__VecListFourDAllLanes1_2__DupAlignedMemory64or1282_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListFourDAllLanes, MCK_DupAlignedMemory64or128 }, },
12778   { 2375 /* vld4 */, ARM::VLD4DUPdAsm_8, Convert__VecListFourDAllLanes1_2__DupAlignedMemory322_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListFourDAllLanes, MCK_DupAlignedMemory32 }, },
12783   { 2375 /* vld4 */, ARM::VLD4DUPdWB_fixed_Asm_16, Convert__VecListFourDAllLanes1_2__DupAlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListFourDAllLanes, MCK_DupAlignedMemory64, MCK__EXCLAIM_ }, },
12784   { 2375 /* vld4 */, ARM::VLD4DUPdWB_register_Asm_16, Convert__VecListFourDAllLanes1_2__DupAlignedMemory642_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListFourDAllLanes, MCK_DupAlignedMemory64, MCK_rGPR }, },
12795   { 2375 /* vld4 */, ARM::VLD4DUPdWB_fixed_Asm_32, Convert__VecListFourDAllLanes1_2__DupAlignedMemory64or1282_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListFourDAllLanes, MCK_DupAlignedMemory64or128, MCK__EXCLAIM_ }, },
12796   { 2375 /* vld4 */, ARM::VLD4DUPdWB_register_Asm_32, Convert__VecListFourDAllLanes1_2__DupAlignedMemory64or1282_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListFourDAllLanes, MCK_DupAlignedMemory64or128, MCK_rGPR }, },
12807   { 2375 /* vld4 */, ARM::VLD4DUPdWB_fixed_Asm_8, Convert__VecListFourDAllLanes1_2__DupAlignedMemory322_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListFourDAllLanes, MCK_DupAlignedMemory32, MCK__EXCLAIM_ }, },
12808   { 2375 /* vld4 */, ARM::VLD4DUPdWB_register_Asm_8, Convert__VecListFourDAllLanes1_2__DupAlignedMemory322_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListFourDAllLanes, MCK_DupAlignedMemory32, MCK_rGPR }, },
15892   { 2375 /* vld4 */, 4 /* 2 */, MCK_VecListFourDAllLanes, AMFBS_HasNEON },
15898   { 2375 /* vld4 */, 4 /* 2 */, MCK_VecListFourDAllLanes, AMFBS_HasNEON },
15904   { 2375 /* vld4 */, 4 /* 2 */, MCK_VecListFourDAllLanes, AMFBS_HasNEON },
15909   { 2375 /* vld4 */, 4 /* 2 */, MCK_VecListFourDAllLanes, AMFBS_HasNEON },
15910   { 2375 /* vld4 */, 4 /* 2 */, MCK_VecListFourDAllLanes, AMFBS_HasNEON },
15921   { 2375 /* vld4 */, 4 /* 2 */, MCK_VecListFourDAllLanes, AMFBS_HasNEON },
15922   { 2375 /* vld4 */, 4 /* 2 */, MCK_VecListFourDAllLanes, AMFBS_HasNEON },
15933   { 2375 /* vld4 */, 4 /* 2 */, MCK_VecListFourDAllLanes, AMFBS_HasNEON },
15934   { 2375 /* vld4 */, 4 /* 2 */, MCK_VecListFourDAllLanes, AMFBS_HasNEON },
16263   case MCK_VecListFourDAllLanes: