reference, declaration → definition definition → references, declarations, derived classes, virtual overrides reference to multiple definitions → definitions unreferenced |
8236 case MCK_VecListDPairAllLanes: { 9634 case MCK_VecListDPairAllLanes: return "MCK_VecListDPairAllLanes"; 12538 { 2348 /* vld1 */, ARM::VLD1DUPq16, Convert__VecListDPairAllLanes1_2__DupAlignedMemory162_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListDPairAllLanes, MCK_DupAlignedMemory16 }, }, 12545 { 2348 /* vld1 */, ARM::VLD1DUPq32, Convert__VecListDPairAllLanes1_2__DupAlignedMemory322_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListDPairAllLanes, MCK_DupAlignedMemory32 }, }, 12556 { 2348 /* vld1 */, ARM::VLD1DUPq8, Convert__VecListDPairAllLanes1_2__DupAlignedMemoryNone2_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListDPairAllLanes, MCK_DupAlignedMemoryNone }, }, 12563 { 2348 /* vld1 */, ARM::VLD1DUPq16wb_fixed, Convert__VecListDPairAllLanes1_2__imm_95_0__DupAlignedMemory162_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListDPairAllLanes, MCK_DupAlignedMemory16, MCK__EXCLAIM_ }, }, 12564 { 2348 /* vld1 */, ARM::VLD1DUPq16wb_register, Convert__VecListDPairAllLanes1_2__imm_95_0__DupAlignedMemory162_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListDPairAllLanes, MCK_DupAlignedMemory16, MCK_rGPR }, }, 12577 { 2348 /* vld1 */, ARM::VLD1DUPq32wb_fixed, Convert__VecListDPairAllLanes1_2__imm_95_0__DupAlignedMemory322_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListDPairAllLanes, MCK_DupAlignedMemory32, MCK__EXCLAIM_ }, }, 12578 { 2348 /* vld1 */, ARM::VLD1DUPq32wb_register, Convert__VecListDPairAllLanes1_2__imm_95_0__DupAlignedMemory322_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListDPairAllLanes, MCK_DupAlignedMemory32, MCK_rGPR }, }, 12599 { 2348 /* vld1 */, ARM::VLD1DUPq8wb_fixed, Convert__VecListDPairAllLanes1_2__imm_95_0__DupAlignedMemoryNone2_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListDPairAllLanes, MCK_DupAlignedMemoryNone, MCK__EXCLAIM_ }, }, 12600 { 2348 /* vld1 */, ARM::VLD1DUPq8wb_register, Convert__VecListDPairAllLanes1_2__imm_95_0__DupAlignedMemoryNone2_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListDPairAllLanes, MCK_DupAlignedMemoryNone, MCK_rGPR }, }, 12619 { 2353 /* vld2 */, ARM::VLD2DUPd16, Convert__VecListDPairAllLanes1_2__DupAlignedMemory322_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListDPairAllLanes, MCK_DupAlignedMemory32 }, }, 12626 { 2353 /* vld2 */, ARM::VLD2DUPd32, Convert__VecListDPairAllLanes1_2__DupAlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListDPairAllLanes, MCK_DupAlignedMemory64 }, }, 12633 { 2353 /* vld2 */, ARM::VLD2DUPd8, Convert__VecListDPairAllLanes1_2__DupAlignedMemory162_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListDPairAllLanes, MCK_DupAlignedMemory16 }, }, 12639 { 2353 /* vld2 */, ARM::VLD2DUPd16wb_fixed, Convert__VecListDPairAllLanes1_2__imm_95_0__DupAlignedMemory322_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListDPairAllLanes, MCK_DupAlignedMemory32, MCK__EXCLAIM_ }, }, 12640 { 2353 /* vld2 */, ARM::VLD2DUPd16wb_register, Convert__VecListDPairAllLanes1_2__imm_95_0__DupAlignedMemory322_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_16, MCK_VecListDPairAllLanes, MCK_DupAlignedMemory32, MCK_rGPR }, }, 12653 { 2353 /* vld2 */, ARM::VLD2DUPd32wb_fixed, Convert__VecListDPairAllLanes1_2__imm_95_0__DupAlignedMemory642_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListDPairAllLanes, MCK_DupAlignedMemory64, MCK__EXCLAIM_ }, }, 12654 { 2353 /* vld2 */, ARM::VLD2DUPd32wb_register, Convert__VecListDPairAllLanes1_2__imm_95_0__DupAlignedMemory642_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_32, MCK_VecListDPairAllLanes, MCK_DupAlignedMemory64, MCK_rGPR }, }, 12667 { 2353 /* vld2 */, ARM::VLD2DUPd8wb_fixed, Convert__VecListDPairAllLanes1_2__imm_95_0__DupAlignedMemory162_3__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListDPairAllLanes, MCK_DupAlignedMemory16, MCK__EXCLAIM_ }, }, 12668 { 2353 /* vld2 */, ARM::VLD2DUPd8wb_register, Convert__VecListDPairAllLanes1_2__imm_95_0__DupAlignedMemory162_3__Reg1_4__CondCode2_0, AMFBS_HasNEON, { MCK_CondCode, MCK__DOT_8, MCK_VecListDPairAllLanes, MCK_DupAlignedMemory16, MCK_rGPR }, }, 15694 { 2348 /* vld1 */, 4 /* 2 */, MCK_VecListDPairAllLanes, AMFBS_HasNEON }, 15701 { 2348 /* vld1 */, 4 /* 2 */, MCK_VecListDPairAllLanes, AMFBS_HasNEON }, 15712 { 2348 /* vld1 */, 4 /* 2 */, MCK_VecListDPairAllLanes, AMFBS_HasNEON }, 15719 { 2348 /* vld1 */, 4 /* 2 */, MCK_VecListDPairAllLanes, AMFBS_HasNEON }, 15720 { 2348 /* vld1 */, 4 /* 2 */, MCK_VecListDPairAllLanes, AMFBS_HasNEON }, 15733 { 2348 /* vld1 */, 4 /* 2 */, MCK_VecListDPairAllLanes, AMFBS_HasNEON }, 15734 { 2348 /* vld1 */, 4 /* 2 */, MCK_VecListDPairAllLanes, AMFBS_HasNEON }, 15755 { 2348 /* vld1 */, 4 /* 2 */, MCK_VecListDPairAllLanes, AMFBS_HasNEON }, 15756 { 2348 /* vld1 */, 4 /* 2 */, MCK_VecListDPairAllLanes, AMFBS_HasNEON }, 15769 { 2353 /* vld2 */, 4 /* 2 */, MCK_VecListDPairAllLanes, AMFBS_HasNEON }, 15776 { 2353 /* vld2 */, 4 /* 2 */, MCK_VecListDPairAllLanes, AMFBS_HasNEON }, 15783 { 2353 /* vld2 */, 4 /* 2 */, MCK_VecListDPairAllLanes, AMFBS_HasNEON }, 15789 { 2353 /* vld2 */, 4 /* 2 */, MCK_VecListDPairAllLanes, AMFBS_HasNEON }, 15790 { 2353 /* vld2 */, 4 /* 2 */, MCK_VecListDPairAllLanes, AMFBS_HasNEON }, 15803 { 2353 /* vld2 */, 4 /* 2 */, MCK_VecListDPairAllLanes, AMFBS_HasNEON }, 15804 { 2353 /* vld2 */, 4 /* 2 */, MCK_VecListDPairAllLanes, AMFBS_HasNEON }, 15817 { 2353 /* vld2 */, 4 /* 2 */, MCK_VecListDPairAllLanes, AMFBS_HasNEON }, 15818 { 2353 /* vld2 */, 4 /* 2 */, MCK_VecListDPairAllLanes, AMFBS_HasNEON }, 16255 case MCK_VecListDPairAllLanes: