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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/ARM/ARMGenAsmMatcher.inc 8211 case MCK_VPTPredR: {
9631 case MCK_VPTPredR: return "MCK_VPTPredR";
11605 { 1977 /* vabd */, ARM::MVE_VABDs16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
11606 { 1977 /* vabd */, ARM::MVE_VABDs32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
11607 { 1977 /* vabd */, ARM::MVE_VABDs8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
11608 { 1977 /* vabd */, ARM::MVE_VABDu16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
11609 { 1977 /* vabd */, ARM::MVE_VABDu32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
11610 { 1977 /* vabd */, ARM::MVE_VABDu8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
11611 { 1977 /* vabd */, ARM::MVE_VABDf32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_f32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
11612 { 1977 /* vabd */, ARM::MVE_VABDf16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_f16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
11632 { 1988 /* vabs */, ARM::MVE_VABSs16, Convert__Reg1_2__Reg1_3__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s16, MCK_MQPR, MCK_MQPR }, },
11633 { 1988 /* vabs */, ARM::MVE_VABSs32, Convert__Reg1_2__Reg1_3__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s32, MCK_MQPR, MCK_MQPR }, },
11634 { 1988 /* vabs */, ARM::MVE_VABSs8, Convert__Reg1_2__Reg1_3__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s8, MCK_MQPR, MCK_MQPR }, },
11635 { 1988 /* vabs */, ARM::MVE_VABSf32, Convert__Reg1_2__Reg1_3__VPTPredR3_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_f32, MCK_MQPR, MCK_MQPR }, },
11636 { 1988 /* vabs */, ARM::MVE_VABSf16, Convert__Reg1_2__Reg1_3__VPTPredR3_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_f16, MCK_MQPR, MCK_MQPR }, },
11669 { 2017 /* vadc */, ARM::MVE_VADC, Convert__Reg1_2__imm_95_0__Reg1_3__Reg1_4__imm_95_0__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_i32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
11670 { 2022 /* vadci */, ARM::MVE_VADCI, Convert__Reg1_2__imm_95_0__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_i32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
11701 { 2028 /* vadd */, ARM::MVE_VADDf32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_f32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
11702 { 2028 /* vadd */, ARM::MVE_VADD_qr_f32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_f32, MCK_MQPR, MCK_MQPR, MCK_rGPR }, },
11703 { 2028 /* vadd */, ARM::MVE_VADDi16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_i16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
11704 { 2028 /* vadd */, ARM::MVE_VADD_qr_i16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_i16, MCK_MQPR, MCK_MQPR, MCK_rGPR }, },
11705 { 2028 /* vadd */, ARM::MVE_VADDi32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_i32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
11706 { 2028 /* vadd */, ARM::MVE_VADD_qr_i32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_i32, MCK_MQPR, MCK_MQPR, MCK_rGPR }, },
11707 { 2028 /* vadd */, ARM::MVE_VADDi8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_i8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
11708 { 2028 /* vadd */, ARM::MVE_VADD_qr_i8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_i8, MCK_MQPR, MCK_MQPR, MCK_rGPR }, },
11709 { 2028 /* vadd */, ARM::MVE_VADDf16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_f16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
11710 { 2028 /* vadd */, ARM::MVE_VADD_qr_f16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_f16, MCK_MQPR, MCK_MQPR, MCK_rGPR }, },
11770 { 2080 /* vand */, ARM::MVE_VAND, Convert__Reg1_1__Reg1_2__Reg1_3__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
11779 { 2080 /* vand */, ARM::MVE_VAND, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
11780 { 2080 /* vand */, ARM::MVE_VAND, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
11781 { 2080 /* vand */, ARM::MVE_VAND, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_s8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
11782 { 2080 /* vand */, ARM::MVE_VAND, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_u16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
11783 { 2080 /* vand */, ARM::MVE_VAND, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_u32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
11784 { 2080 /* vand */, ARM::MVE_VAND, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_u8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
11785 { 2080 /* vand */, ARM::MVE_VAND, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_f32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
11786 { 2080 /* vand */, ARM::MVE_VAND, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_i16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
11787 { 2080 /* vand */, ARM::MVE_VAND, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_i32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
11788 { 2080 /* vand */, ARM::MVE_VAND, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_i8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
11789 { 2080 /* vand */, ARM::MVE_VAND, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_f16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
11804 { 2085 /* vbic */, ARM::MVE_VBIC, Convert__Reg1_1__Reg1_2__Reg1_3__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
11813 { 2085 /* vbic */, ARM::MVE_VBIC, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
11814 { 2085 /* vbic */, ARM::MVE_VBIC, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
11815 { 2085 /* vbic */, ARM::MVE_VBIC, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_s8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
11816 { 2085 /* vbic */, ARM::MVE_VBIC, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_u16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
11817 { 2085 /* vbic */, ARM::MVE_VBIC, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_u32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
11818 { 2085 /* vbic */, ARM::MVE_VBIC, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_u8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
11819 { 2085 /* vbic */, ARM::MVE_VBIC, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_f32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
11820 { 2085 /* vbic */, ARM::MVE_VBIC, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_i16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
11821 { 2085 /* vbic */, ARM::MVE_VBIC, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_i32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
11822 { 2085 /* vbic */, ARM::MVE_VBIC, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_i8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
11823 { 2085 /* vbic */, ARM::MVE_VBIC, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_f16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
11844 { 2100 /* vbrsr */, ARM::MVE_VBRSR16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_16, MCK_MQPR, MCK_MQPR, MCK_rGPR }, },
11845 { 2100 /* vbrsr */, ARM::MVE_VBRSR32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_32, MCK_MQPR, MCK_MQPR, MCK_rGPR }, },
11846 { 2100 /* vbrsr */, ARM::MVE_VBRSR8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_8, MCK_MQPR, MCK_MQPR, MCK_rGPR }, },
11861 { 2111 /* vcadd */, ARM::MVE_VCADDf32, Convert__Reg1_2__Reg1_3__Reg1_4__ComplexRotationOdd1_5__VPTPredR3_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_f32, MCK_MQPR, MCK_MQPR, MCK_MQPR, MCK_ComplexRotationOdd }, },
11862 { 2111 /* vcadd */, ARM::MVE_VCADDi16, Convert__Reg1_2__Reg1_3__Reg1_4__ComplexRotationOdd1_5__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_i16, MCK_MQPR, MCK_MQPR, MCK_MQPR, MCK_ComplexRotationOdd }, },
11863 { 2111 /* vcadd */, ARM::MVE_VCADDi32, Convert__Reg1_2__Reg1_3__Reg1_4__ComplexRotationOdd1_5__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_i32, MCK_MQPR, MCK_MQPR, MCK_MQPR, MCK_ComplexRotationOdd }, },
11864 { 2111 /* vcadd */, ARM::MVE_VCADDi8, Convert__Reg1_2__Reg1_3__Reg1_4__ComplexRotationOdd1_5__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_i8, MCK_MQPR, MCK_MQPR, MCK_MQPR, MCK_ComplexRotationOdd }, },
11865 { 2111 /* vcadd */, ARM::MVE_VCADDf16, Convert__Reg1_2__Reg1_3__Reg1_4__ComplexRotationOdd1_5__VPTPredR3_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_f16, MCK_MQPR, MCK_MQPR, MCK_MQPR, MCK_ComplexRotationOdd }, },
12052 { 2137 /* vcls */, ARM::MVE_VCLSs16, Convert__Reg1_2__Reg1_3__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s16, MCK_MQPR, MCK_MQPR }, },
12053 { 2137 /* vcls */, ARM::MVE_VCLSs32, Convert__Reg1_2__Reg1_3__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s32, MCK_MQPR, MCK_MQPR }, },
12054 { 2137 /* vcls */, ARM::MVE_VCLSs8, Convert__Reg1_2__Reg1_3__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s8, MCK_MQPR, MCK_MQPR }, },
12097 { 2147 /* vclz */, ARM::MVE_VCLZs16, Convert__Reg1_2__Reg1_3__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_i16, MCK_MQPR, MCK_MQPR }, },
12098 { 2147 /* vclz */, ARM::MVE_VCLZs32, Convert__Reg1_2__Reg1_3__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_i32, MCK_MQPR, MCK_MQPR }, },
12099 { 2147 /* vclz */, ARM::MVE_VCLZs8, Convert__Reg1_2__Reg1_3__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_i8, MCK_MQPR, MCK_MQPR }, },
12144 { 2169 /* vcmul */, ARM::MVE_VCMULf32, Convert__Reg1_2__Reg1_3__Reg1_4__ComplexRotationEven1_5__VPTPredR3_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_f32, MCK_MQPR, MCK_MQPR, MCK_MQPR, MCK_ComplexRotationEven }, },
12145 { 2169 /* vcmul */, ARM::MVE_VCMULf16, Convert__Reg1_2__Reg1_3__Reg1_4__ComplexRotationEven1_5__VPTPredR3_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_f16, MCK_MQPR, MCK_MQPR, MCK_MQPR, MCK_ComplexRotationEven }, },
12184 { 2185 /* vcvt */, ARM::MVE_VCVTs16f16z, Convert__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_s16, MCK__DOT_f16, MCK_MQPR, MCK_MQPR }, },
12185 { 2185 /* vcvt */, ARM::MVE_VCVTs32f32z, Convert__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_s32, MCK__DOT_f32, MCK_MQPR, MCK_MQPR }, },
12186 { 2185 /* vcvt */, ARM::MVE_VCVTu16f16z, Convert__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_u16, MCK__DOT_f16, MCK_MQPR, MCK_MQPR }, },
12187 { 2185 /* vcvt */, ARM::MVE_VCVTu32f32z, Convert__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_u32, MCK__DOT_f32, MCK_MQPR, MCK_MQPR }, },
12188 { 2185 /* vcvt */, ARM::MVE_VCVTf32s32n, Convert__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_f32, MCK__DOT_s32, MCK_MQPR, MCK_MQPR }, },
12189 { 2185 /* vcvt */, ARM::MVE_VCVTf32u32n, Convert__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_f32, MCK__DOT_u32, MCK_MQPR, MCK_MQPR }, },
12190 { 2185 /* vcvt */, ARM::MVE_VCVTf16s16n, Convert__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_f16, MCK__DOT_s16, MCK_MQPR, MCK_MQPR }, },
12191 { 2185 /* vcvt */, ARM::MVE_VCVTf16u16n, Convert__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_f16, MCK__DOT_u16, MCK_MQPR, MCK_MQPR }, },
12248 { 2185 /* vcvt */, ARM::MVE_VCVTs16f16_fix, Convert__Reg1_3__Reg1_4__MVEVcvtImm161_5__VPTPredR3_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_s16, MCK__DOT_f16, MCK_MQPR, MCK_MQPR, MCK_MVEVcvtImm16 }, },
12249 { 2185 /* vcvt */, ARM::MVE_VCVTs32f32_fix, Convert__Reg1_3__Reg1_4__MVEVcvtImm321_5__VPTPredR3_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_s32, MCK__DOT_f32, MCK_MQPR, MCK_MQPR, MCK_MVEVcvtImm32 }, },
12250 { 2185 /* vcvt */, ARM::MVE_VCVTu16f16_fix, Convert__Reg1_3__Reg1_4__MVEVcvtImm161_5__VPTPredR3_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_u16, MCK__DOT_f16, MCK_MQPR, MCK_MQPR, MCK_MVEVcvtImm16 }, },
12251 { 2185 /* vcvt */, ARM::MVE_VCVTu32f32_fix, Convert__Reg1_3__Reg1_4__MVEVcvtImm321_5__VPTPredR3_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_u32, MCK__DOT_f32, MCK_MQPR, MCK_MQPR, MCK_MVEVcvtImm32 }, },
12252 { 2185 /* vcvt */, ARM::MVE_VCVTf32s32_fix, Convert__Reg1_3__Reg1_4__MVEVcvtImm321_5__VPTPredR3_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_f32, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_MVEVcvtImm32 }, },
12253 { 2185 /* vcvt */, ARM::MVE_VCVTf32u32_fix, Convert__Reg1_3__Reg1_4__MVEVcvtImm321_5__VPTPredR3_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_f32, MCK__DOT_u32, MCK_MQPR, MCK_MQPR, MCK_MVEVcvtImm32 }, },
12254 { 2185 /* vcvt */, ARM::MVE_VCVTf16s16_fix, Convert__Reg1_3__Reg1_4__MVEVcvtImm161_5__VPTPredR3_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_f16, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_MVEVcvtImm16 }, },
12255 { 2185 /* vcvt */, ARM::MVE_VCVTf16u16_fix, Convert__Reg1_3__Reg1_4__MVEVcvtImm161_5__VPTPredR3_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_f16, MCK__DOT_u16, MCK_MQPR, MCK_MQPR, MCK_MVEVcvtImm16 }, },
12270 { 2190 /* vcvta */, ARM::MVE_VCVTs16f16a, Convert__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_s16, MCK__DOT_f16, MCK_MQPR, MCK_MQPR }, },
12271 { 2190 /* vcvta */, ARM::MVE_VCVTs32f32a, Convert__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_s32, MCK__DOT_f32, MCK_MQPR, MCK_MQPR }, },
12272 { 2190 /* vcvta */, ARM::MVE_VCVTu16f16a, Convert__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_u16, MCK__DOT_f16, MCK_MQPR, MCK_MQPR }, },
12273 { 2190 /* vcvta */, ARM::MVE_VCVTu32f32a, Convert__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_u32, MCK__DOT_f32, MCK_MQPR, MCK_MQPR }, },
12294 { 2202 /* vcvtm */, ARM::MVE_VCVTs16f16m, Convert__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_s16, MCK__DOT_f16, MCK_MQPR, MCK_MQPR }, },
12295 { 2202 /* vcvtm */, ARM::MVE_VCVTs32f32m, Convert__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_s32, MCK__DOT_f32, MCK_MQPR, MCK_MQPR }, },
12296 { 2202 /* vcvtm */, ARM::MVE_VCVTu16f16m, Convert__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_u16, MCK__DOT_f16, MCK_MQPR, MCK_MQPR }, },
12297 { 2202 /* vcvtm */, ARM::MVE_VCVTu32f32m, Convert__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_u32, MCK__DOT_f32, MCK_MQPR, MCK_MQPR }, },
12312 { 2208 /* vcvtn */, ARM::MVE_VCVTs16f16n, Convert__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_s16, MCK__DOT_f16, MCK_MQPR, MCK_MQPR }, },
12313 { 2208 /* vcvtn */, ARM::MVE_VCVTs32f32n, Convert__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_s32, MCK__DOT_f32, MCK_MQPR, MCK_MQPR }, },
12314 { 2208 /* vcvtn */, ARM::MVE_VCVTu16f16n, Convert__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_u16, MCK__DOT_f16, MCK_MQPR, MCK_MQPR }, },
12315 { 2208 /* vcvtn */, ARM::MVE_VCVTu32f32n, Convert__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_u32, MCK__DOT_f32, MCK_MQPR, MCK_MQPR }, },
12330 { 2214 /* vcvtp */, ARM::MVE_VCVTs16f16p, Convert__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_s16, MCK__DOT_f16, MCK_MQPR, MCK_MQPR }, },
12331 { 2214 /* vcvtp */, ARM::MVE_VCVTs32f32p, Convert__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_s32, MCK__DOT_f32, MCK_MQPR, MCK_MQPR }, },
12332 { 2214 /* vcvtp */, ARM::MVE_VCVTu16f16p, Convert__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_u16, MCK__DOT_f16, MCK_MQPR, MCK_MQPR }, },
12333 { 2214 /* vcvtp */, ARM::MVE_VCVTu32f32p, Convert__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_u32, MCK__DOT_f32, MCK_MQPR, MCK_MQPR }, },
12346 { 2232 /* vddup */, ARM::MVE_VDDUPu16, Convert__Reg1_2__Reg1_3__Tie1_1_1__VIDUP_imm1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u16, MCK_MQPR, MCK_tGPREven, MCK_VIDUP_imm }, },
12347 { 2232 /* vddup */, ARM::MVE_VDDUPu32, Convert__Reg1_2__Reg1_3__Tie1_1_1__VIDUP_imm1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u32, MCK_MQPR, MCK_tGPREven, MCK_VIDUP_imm }, },
12348 { 2232 /* vddup */, ARM::MVE_VDDUPu8, Convert__Reg1_2__Reg1_3__Tie1_1_1__VIDUP_imm1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u8, MCK_MQPR, MCK_tGPREven, MCK_VIDUP_imm }, },
12361 { 2243 /* vdup */, ARM::MVE_VDUP16, Convert__Reg1_2__Reg1_3__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_16, MCK_MQPR, MCK_rGPR }, },
12362 { 2243 /* vdup */, ARM::MVE_VDUP32, Convert__Reg1_2__Reg1_3__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_32, MCK_MQPR, MCK_rGPR }, },
12363 { 2243 /* vdup */, ARM::MVE_VDUP8, Convert__Reg1_2__Reg1_3__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_8, MCK_MQPR, MCK_rGPR }, },
12370 { 2248 /* vdwdup */, ARM::MVE_VDWDUPu16, Convert__Reg1_2__Reg1_3__Tie1_1_1__Reg1_4__VIDUP_imm1_5__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u16, MCK_MQPR, MCK_tGPREven, MCK_tGPROdd, MCK_VIDUP_imm }, },
12371 { 2248 /* vdwdup */, ARM::MVE_VDWDUPu32, Convert__Reg1_2__Reg1_3__Tie1_1_1__Reg1_4__VIDUP_imm1_5__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u32, MCK_MQPR, MCK_tGPREven, MCK_tGPROdd, MCK_VIDUP_imm }, },
12372 { 2248 /* vdwdup */, ARM::MVE_VDWDUPu8, Convert__Reg1_2__Reg1_3__Tie1_1_1__Reg1_4__VIDUP_imm1_5__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u8, MCK_MQPR, MCK_tGPREven, MCK_tGPROdd, MCK_VIDUP_imm }, },
12385 { 2255 /* veor */, ARM::MVE_VEOR, Convert__Reg1_1__Reg1_2__Reg1_3__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
12394 { 2255 /* veor */, ARM::MVE_VEOR, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
12395 { 2255 /* veor */, ARM::MVE_VEOR, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
12396 { 2255 /* veor */, ARM::MVE_VEOR, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_s8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
12397 { 2255 /* veor */, ARM::MVE_VEOR, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_u16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
12398 { 2255 /* veor */, ARM::MVE_VEOR, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_u32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
12399 { 2255 /* veor */, ARM::MVE_VEOR, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_u8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
12400 { 2255 /* veor */, ARM::MVE_VEOR, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_f32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
12401 { 2255 /* veor */, ARM::MVE_VEOR, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_i16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
12402 { 2255 /* veor */, ARM::MVE_VEOR, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_i32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
12403 { 2255 /* veor */, ARM::MVE_VEOR, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_i8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
12404 { 2255 /* veor */, ARM::MVE_VEOR, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_f16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
12479 { 2305 /* vhadd */, ARM::MVE_VHADDs16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
12480 { 2305 /* vhadd */, ARM::MVE_VHADD_qr_s16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_rGPR }, },
12481 { 2305 /* vhadd */, ARM::MVE_VHADDs32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
12482 { 2305 /* vhadd */, ARM::MVE_VHADD_qr_s32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_rGPR }, },
12483 { 2305 /* vhadd */, ARM::MVE_VHADDs8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
12484 { 2305 /* vhadd */, ARM::MVE_VHADD_qr_s8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s8, MCK_MQPR, MCK_MQPR, MCK_rGPR }, },
12485 { 2305 /* vhadd */, ARM::MVE_VHADDu16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
12486 { 2305 /* vhadd */, ARM::MVE_VHADD_qr_u16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u16, MCK_MQPR, MCK_MQPR, MCK_rGPR }, },
12487 { 2305 /* vhadd */, ARM::MVE_VHADDu32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
12488 { 2305 /* vhadd */, ARM::MVE_VHADD_qr_u32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u32, MCK_MQPR, MCK_MQPR, MCK_rGPR }, },
12489 { 2305 /* vhadd */, ARM::MVE_VHADDu8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
12490 { 2305 /* vhadd */, ARM::MVE_VHADD_qr_u8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u8, MCK_MQPR, MCK_MQPR, MCK_rGPR }, },
12491 { 2311 /* vhcadd */, ARM::MVE_VHCADDs16, Convert__Reg1_2__Reg1_3__Reg1_4__ComplexRotationOdd1_5__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_MQPR, MCK_ComplexRotationOdd }, },
12492 { 2311 /* vhcadd */, ARM::MVE_VHCADDs32, Convert__Reg1_2__Reg1_3__Reg1_4__ComplexRotationOdd1_5__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_MQPR, MCK_ComplexRotationOdd }, },
12493 { 2311 /* vhcadd */, ARM::MVE_VHCADDs8, Convert__Reg1_2__Reg1_3__Reg1_4__ComplexRotationOdd1_5__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s8, MCK_MQPR, MCK_MQPR, MCK_MQPR, MCK_ComplexRotationOdd }, },
12518 { 2318 /* vhsub */, ARM::MVE_VHSUBs16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
12519 { 2318 /* vhsub */, ARM::MVE_VHSUB_qr_s16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_rGPR }, },
12520 { 2318 /* vhsub */, ARM::MVE_VHSUBs32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
12521 { 2318 /* vhsub */, ARM::MVE_VHSUB_qr_s32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_rGPR }, },
12522 { 2318 /* vhsub */, ARM::MVE_VHSUBs8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
12523 { 2318 /* vhsub */, ARM::MVE_VHSUB_qr_s8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s8, MCK_MQPR, MCK_MQPR, MCK_rGPR }, },
12524 { 2318 /* vhsub */, ARM::MVE_VHSUBu16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
12525 { 2318 /* vhsub */, ARM::MVE_VHSUB_qr_u16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u16, MCK_MQPR, MCK_MQPR, MCK_rGPR }, },
12526 { 2318 /* vhsub */, ARM::MVE_VHSUBu32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
12527 { 2318 /* vhsub */, ARM::MVE_VHSUB_qr_u32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u32, MCK_MQPR, MCK_MQPR, MCK_rGPR }, },
12528 { 2318 /* vhsub */, ARM::MVE_VHSUBu8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
12529 { 2318 /* vhsub */, ARM::MVE_VHSUB_qr_u8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u8, MCK_MQPR, MCK_MQPR, MCK_rGPR }, },
12530 { 2324 /* vidup */, ARM::MVE_VIDUPu16, Convert__Reg1_2__Reg1_3__Tie1_1_1__VIDUP_imm1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u16, MCK_MQPR, MCK_tGPREven, MCK_VIDUP_imm }, },
12531 { 2324 /* vidup */, ARM::MVE_VIDUPu32, Convert__Reg1_2__Reg1_3__Tie1_1_1__VIDUP_imm1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u32, MCK_MQPR, MCK_tGPREven, MCK_VIDUP_imm }, },
12532 { 2324 /* vidup */, ARM::MVE_VIDUPu8, Convert__Reg1_2__Reg1_3__Tie1_1_1__VIDUP_imm1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u8, MCK_MQPR, MCK_tGPREven, MCK_VIDUP_imm }, },
12534 { 2335 /* viwdup */, ARM::MVE_VIWDUPu16, Convert__Reg1_2__Reg1_3__Tie1_1_1__Reg1_4__VIDUP_imm1_5__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u16, MCK_MQPR, MCK_tGPREven, MCK_tGPROdd, MCK_VIDUP_imm }, },
12535 { 2335 /* viwdup */, ARM::MVE_VIWDUPu32, Convert__Reg1_2__Reg1_3__Tie1_1_1__Reg1_4__VIDUP_imm1_5__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u32, MCK_MQPR, MCK_tGPREven, MCK_tGPROdd, MCK_VIDUP_imm }, },
12536 { 2335 /* viwdup */, ARM::MVE_VIWDUPu8, Convert__Reg1_2__Reg1_3__Tie1_1_1__Reg1_4__VIDUP_imm1_5__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u8, MCK_MQPR, MCK_tGPREven, MCK_tGPROdd, MCK_VIDUP_imm }, },
12974 { 2459 /* vmax */, ARM::MVE_VMAXs16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
12975 { 2459 /* vmax */, ARM::MVE_VMAXs32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
12976 { 2459 /* vmax */, ARM::MVE_VMAXs8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
12977 { 2459 /* vmax */, ARM::MVE_VMAXu16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
12978 { 2459 /* vmax */, ARM::MVE_VMAXu32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
12979 { 2459 /* vmax */, ARM::MVE_VMAXu8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
12993 { 2477 /* vmaxnm */, ARM::MVE_VMAXNMf32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_f32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
12994 { 2477 /* vmaxnm */, ARM::MVE_VMAXNMf16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_f16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13039 { 2515 /* vmin */, ARM::MVE_VMINs16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13040 { 2515 /* vmin */, ARM::MVE_VMINs32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13041 { 2515 /* vmin */, ARM::MVE_VMINs8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13042 { 2515 /* vmin */, ARM::MVE_VMINu16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13043 { 2515 /* vmin */, ARM::MVE_VMINu32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13044 { 2515 /* vmin */, ARM::MVE_VMINu8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13058 { 2533 /* vminnm */, ARM::MVE_VMINNMf32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_f32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13059 { 2533 /* vminnm */, ARM::MVE_VMINNMf16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_f16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13221 { 2779 /* vmov */, ARM::MVE_VORR, Convert__Reg1_1__Reg1_2__Reg1_2__VPTPredR3_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK_MQPR, MCK_MQPR }, },
13271 { 2779 /* vmov */, ARM::MVE_VMOVimmf32, Convert__Reg1_2__FPImm1_3__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_f32, MCK_MQPR, MCK_FPImm }, },
13272 { 2779 /* vmov */, ARM::MVE_VMOVimmi16, Convert__Reg1_2__NEONi16splat1_3__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_i16, MCK_MQPR, MCK_NEONi16splat }, },
13273 { 2779 /* vmov */, ARM::MVE_VMOVimmi32, Convert__Reg1_2__NEONi32vmov1_3__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_i32, MCK_MQPR, MCK_NEONi32vmov }, },
13274 { 2779 /* vmov */, ARM::MVE_VMOVimmi64, Convert__Reg1_2__NEONi64splat1_3__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_i64, MCK_MQPR, MCK_NEONi64splat }, },
13275 { 2779 /* vmov */, ARM::MVE_VMOVimmi8, Convert__Reg1_2__NEONi8splat1_3__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_i8, MCK_MQPR, MCK_NEONi8splat }, },
13304 { 2790 /* vmovlb */, ARM::MVE_VMOVLs16bh, Convert__Reg1_2__Reg1_3__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s16, MCK_MQPR, MCK_MQPR }, },
13305 { 2790 /* vmovlb */, ARM::MVE_VMOVLs8bh, Convert__Reg1_2__Reg1_3__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s8, MCK_MQPR, MCK_MQPR }, },
13306 { 2790 /* vmovlb */, ARM::MVE_VMOVLu16bh, Convert__Reg1_2__Reg1_3__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u16, MCK_MQPR, MCK_MQPR }, },
13307 { 2790 /* vmovlb */, ARM::MVE_VMOVLu8bh, Convert__Reg1_2__Reg1_3__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u8, MCK_MQPR, MCK_MQPR }, },
13308 { 2797 /* vmovlt */, ARM::MVE_VMOVLs16th, Convert__Reg1_2__Reg1_3__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s16, MCK_MQPR, MCK_MQPR }, },
13309 { 2797 /* vmovlt */, ARM::MVE_VMOVLs8th, Convert__Reg1_2__Reg1_3__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s8, MCK_MQPR, MCK_MQPR }, },
13310 { 2797 /* vmovlt */, ARM::MVE_VMOVLu16th, Convert__Reg1_2__Reg1_3__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u16, MCK_MQPR, MCK_MQPR }, },
13311 { 2797 /* vmovlt */, ARM::MVE_VMOVLu8th, Convert__Reg1_2__Reg1_3__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u8, MCK_MQPR, MCK_MQPR }, },
13382 { 2840 /* vmul */, ARM::MVE_VMULf32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_f32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13383 { 2840 /* vmul */, ARM::MVE_VMUL_qr_f32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_f32, MCK_MQPR, MCK_MQPR, MCK_rGPR }, },
13384 { 2840 /* vmul */, ARM::MVE_VMULt1i16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_i16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13385 { 2840 /* vmul */, ARM::MVE_VMUL_qr_i16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_i16, MCK_MQPR, MCK_MQPR, MCK_rGPR }, },
13386 { 2840 /* vmul */, ARM::MVE_VMULt1i32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_i32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13387 { 2840 /* vmul */, ARM::MVE_VMUL_qr_i32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_i32, MCK_MQPR, MCK_MQPR, MCK_rGPR }, },
13388 { 2840 /* vmul */, ARM::MVE_VMULt1i8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_i8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13389 { 2840 /* vmul */, ARM::MVE_VMUL_qr_i8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_i8, MCK_MQPR, MCK_MQPR, MCK_rGPR }, },
13390 { 2840 /* vmul */, ARM::MVE_VMULf16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_f16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13391 { 2840 /* vmul */, ARM::MVE_VMUL_qr_f16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_f16, MCK_MQPR, MCK_MQPR, MCK_rGPR }, },
13400 { 2845 /* vmulh */, ARM::MVE_VMULHs16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13401 { 2845 /* vmulh */, ARM::MVE_VMULHs32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13402 { 2845 /* vmulh */, ARM::MVE_VMULHs8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13403 { 2845 /* vmulh */, ARM::MVE_VMULHu16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13404 { 2845 /* vmulh */, ARM::MVE_VMULHu32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13405 { 2845 /* vmulh */, ARM::MVE_VMULHu8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13418 { 2857 /* vmullb */, ARM::MVE_VMULLs16bh, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13419 { 2857 /* vmullb */, ARM::MVE_VMULLs32bh, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13420 { 2857 /* vmullb */, ARM::MVE_VMULLs8bh, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13421 { 2857 /* vmullb */, ARM::MVE_VMULLu16bh, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13422 { 2857 /* vmullb */, ARM::MVE_VMULLu32bh, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13423 { 2857 /* vmullb */, ARM::MVE_VMULLu8bh, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13424 { 2857 /* vmullb */, ARM::MVE_VMULLp16bh, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_p16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13425 { 2857 /* vmullb */, ARM::MVE_VMULLp8bh, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_p8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13426 { 2864 /* vmullt */, ARM::MVE_VMULLs16th, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13427 { 2864 /* vmullt */, ARM::MVE_VMULLs32th, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13428 { 2864 /* vmullt */, ARM::MVE_VMULLs8th, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13429 { 2864 /* vmullt */, ARM::MVE_VMULLu16th, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13430 { 2864 /* vmullt */, ARM::MVE_VMULLu32th, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13431 { 2864 /* vmullt */, ARM::MVE_VMULLu8th, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13432 { 2864 /* vmullt */, ARM::MVE_VMULLp16th, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_p16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13433 { 2864 /* vmullt */, ARM::MVE_VMULLp8th, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_p8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13436 { 2871 /* vmvn */, ARM::MVE_VMVN, Convert__Reg1_1__Reg1_2__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK_MQPR, MCK_MQPR }, },
13463 { 2871 /* vmvn */, ARM::MVE_VMVNimmi16, Convert__Reg1_2__NEONi16splat1_3__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_i16, MCK_MQPR, MCK_NEONi16splat }, },
13464 { 2871 /* vmvn */, ARM::MVE_VMVNimmi32, Convert__Reg1_2__NEONi32vmov1_3__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_i32, MCK_MQPR, MCK_NEONi32vmov }, },
13478 { 2876 /* vneg */, ARM::MVE_VNEGs16, Convert__Reg1_2__Reg1_3__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s16, MCK_MQPR, MCK_MQPR }, },
13479 { 2876 /* vneg */, ARM::MVE_VNEGs32, Convert__Reg1_2__Reg1_3__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s32, MCK_MQPR, MCK_MQPR }, },
13480 { 2876 /* vneg */, ARM::MVE_VNEGs8, Convert__Reg1_2__Reg1_3__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s8, MCK_MQPR, MCK_MQPR }, },
13481 { 2876 /* vneg */, ARM::MVE_VNEGf32, Convert__Reg1_2__Reg1_3__VPTPredR3_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_f32, MCK_MQPR, MCK_MQPR }, },
13482 { 2876 /* vneg */, ARM::MVE_VNEGf16, Convert__Reg1_2__Reg1_3__VPTPredR3_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_f16, MCK_MQPR, MCK_MQPR }, },
13500 { 2899 /* vorn */, ARM::MVE_VORN, Convert__Reg1_1__Reg1_2__Reg1_3__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13501 { 2899 /* vorn */, ARM::MVE_VORN, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13502 { 2899 /* vorn */, ARM::MVE_VORN, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13503 { 2899 /* vorn */, ARM::MVE_VORN, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_s8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13504 { 2899 /* vorn */, ARM::MVE_VORN, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_u16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13505 { 2899 /* vorn */, ARM::MVE_VORN, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_u32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13506 { 2899 /* vorn */, ARM::MVE_VORN, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_u8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13507 { 2899 /* vorn */, ARM::MVE_VORN, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_f32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13508 { 2899 /* vorn */, ARM::MVE_VORN, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_i16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13509 { 2899 /* vorn */, ARM::MVE_VORN, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_i32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13510 { 2899 /* vorn */, ARM::MVE_VORN, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_i8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13511 { 2899 /* vorn */, ARM::MVE_VORN, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_f16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13534 { 2904 /* vorr */, ARM::MVE_VORR, Convert__Reg1_1__Reg1_2__Reg1_3__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13543 { 2904 /* vorr */, ARM::MVE_VORR, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13544 { 2904 /* vorr */, ARM::MVE_VORR, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13545 { 2904 /* vorr */, ARM::MVE_VORR, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_s8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13546 { 2904 /* vorr */, ARM::MVE_VORR, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_u16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13547 { 2904 /* vorr */, ARM::MVE_VORR, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_u32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13548 { 2904 /* vorr */, ARM::MVE_VORR, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_u8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13549 { 2904 /* vorr */, ARM::MVE_VORR, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_f32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13550 { 2904 /* vorr */, ARM::MVE_VORR, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_i16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13551 { 2904 /* vorr */, ARM::MVE_VORR, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_i32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13552 { 2904 /* vorr */, ARM::MVE_VORR, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_i8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13553 { 2904 /* vorr */, ARM::MVE_VORR, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt_IsThumb, { MCK_VPTPredR, MCK__DOT_f16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13682 { 2973 /* vqabs */, ARM::MVE_VQABSs16, Convert__Reg1_2__Reg1_3__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s16, MCK_MQPR, MCK_MQPR }, },
13683 { 2973 /* vqabs */, ARM::MVE_VQABSs32, Convert__Reg1_2__Reg1_3__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s32, MCK_MQPR, MCK_MQPR }, },
13684 { 2973 /* vqabs */, ARM::MVE_VQABSs8, Convert__Reg1_2__Reg1_3__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s8, MCK_MQPR, MCK_MQPR }, },
13717 { 2979 /* vqadd */, ARM::MVE_VQADDs16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13718 { 2979 /* vqadd */, ARM::MVE_VQADD_qr_s16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_rGPR }, },
13719 { 2979 /* vqadd */, ARM::MVE_VQADDs32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13720 { 2979 /* vqadd */, ARM::MVE_VQADD_qr_s32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_rGPR }, },
13721 { 2979 /* vqadd */, ARM::MVE_VQADDs8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13722 { 2979 /* vqadd */, ARM::MVE_VQADD_qr_s8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s8, MCK_MQPR, MCK_MQPR, MCK_rGPR }, },
13723 { 2979 /* vqadd */, ARM::MVE_VQADDu16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13724 { 2979 /* vqadd */, ARM::MVE_VQADD_qr_u16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u16, MCK_MQPR, MCK_MQPR, MCK_rGPR }, },
13725 { 2979 /* vqadd */, ARM::MVE_VQADDu32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13726 { 2979 /* vqadd */, ARM::MVE_VQADD_qr_u32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u32, MCK_MQPR, MCK_MQPR, MCK_rGPR }, },
13727 { 2979 /* vqadd */, ARM::MVE_VQADDu8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13728 { 2979 /* vqadd */, ARM::MVE_VQADD_qr_u8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u8, MCK_MQPR, MCK_MQPR, MCK_rGPR }, },
13763 { 3056 /* vqdmulh */, ARM::MVE_VQDMULHi16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13764 { 3056 /* vqdmulh */, ARM::MVE_VQDMULH_qr_s16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_rGPR }, },
13765 { 3056 /* vqdmulh */, ARM::MVE_VQDMULHi32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13766 { 3056 /* vqdmulh */, ARM::MVE_VQDMULH_qr_s32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_rGPR }, },
13767 { 3056 /* vqdmulh */, ARM::MVE_VQDMULHi8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13768 { 3056 /* vqdmulh */, ARM::MVE_VQDMULH_qr_s8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s8, MCK_MQPR, MCK_MQPR, MCK_rGPR }, },
13777 { 3072 /* vqdmullb */, ARM::MVE_VQDMULLs16bh, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13778 { 3072 /* vqdmullb */, ARM::MVE_VQDMULL_qr_s16bh, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_rGPR }, },
13779 { 3072 /* vqdmullb */, ARM::MVE_VQDMULLs32bh, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13780 { 3072 /* vqdmullb */, ARM::MVE_VQDMULL_qr_s32bh, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_rGPR }, },
13781 { 3081 /* vqdmullt */, ARM::MVE_VQDMULLs16th, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13782 { 3081 /* vqdmullt */, ARM::MVE_VQDMULL_qr_s16th, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_rGPR }, },
13783 { 3081 /* vqdmullt */, ARM::MVE_VQDMULLs32th, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13784 { 3081 /* vqdmullt */, ARM::MVE_VQDMULL_qr_s32th, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_rGPR }, },
13812 { 3139 /* vqneg */, ARM::MVE_VQNEGs16, Convert__Reg1_2__Reg1_3__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s16, MCK_MQPR, MCK_MQPR }, },
13813 { 3139 /* vqneg */, ARM::MVE_VQNEGs32, Convert__Reg1_2__Reg1_3__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s32, MCK_MQPR, MCK_MQPR }, },
13814 { 3139 /* vqneg */, ARM::MVE_VQNEGs8, Convert__Reg1_2__Reg1_3__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s8, MCK_MQPR, MCK_MQPR }, },
13857 { 3215 /* vqrdmulh */, ARM::MVE_VQRDMULHi16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13858 { 3215 /* vqrdmulh */, ARM::MVE_VQRDMULH_qr_s16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_rGPR }, },
13859 { 3215 /* vqrdmulh */, ARM::MVE_VQRDMULHi32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13860 { 3215 /* vqrdmulh */, ARM::MVE_VQRDMULH_qr_s32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_rGPR }, },
13861 { 3215 /* vqrdmulh */, ARM::MVE_VQRDMULHi8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13862 { 3215 /* vqrdmulh */, ARM::MVE_VQRDMULH_qr_s8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s8, MCK_MQPR, MCK_MQPR, MCK_rGPR }, },
13905 { 3224 /* vqrshl */, ARM::MVE_VQRSHL_by_vecs16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13906 { 3224 /* vqrshl */, ARM::MVE_VQRSHL_by_vecs32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13907 { 3224 /* vqrshl */, ARM::MVE_VQRSHL_by_vecs8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13908 { 3224 /* vqrshl */, ARM::MVE_VQRSHL_by_vecu16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13909 { 3224 /* vqrshl */, ARM::MVE_VQRSHL_by_vecu32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
13910 { 3224 /* vqrshl */, ARM::MVE_VQRSHL_by_vecu8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
14002 { 3286 /* vqshl */, ARM::MVE_VQSHL_by_vecs16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
14003 { 3286 /* vqshl */, ARM::MVE_VSLIimms16, Convert__Reg1_2__Reg1_3__Imm0_151_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_Imm0_15 }, },
14004 { 3286 /* vqshl */, ARM::MVE_VQSHL_by_vecs32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
14005 { 3286 /* vqshl */, ARM::MVE_VSLIimms32, Convert__Reg1_2__Reg1_3__Imm0_311_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_Imm0_31 }, },
14006 { 3286 /* vqshl */, ARM::MVE_VQSHL_by_vecs8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
14007 { 3286 /* vqshl */, ARM::MVE_VSLIimms8, Convert__Reg1_2__Reg1_3__Imm0_71_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s8, MCK_MQPR, MCK_MQPR, MCK_Imm0_7 }, },
14008 { 3286 /* vqshl */, ARM::MVE_VQSHL_by_vecu16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
14009 { 3286 /* vqshl */, ARM::MVE_VSLIimmu16, Convert__Reg1_2__Reg1_3__Imm0_151_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u16, MCK_MQPR, MCK_MQPR, MCK_Imm0_15 }, },
14010 { 3286 /* vqshl */, ARM::MVE_VQSHL_by_vecu32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
14011 { 3286 /* vqshl */, ARM::MVE_VSLIimmu32, Convert__Reg1_2__Reg1_3__Imm0_311_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u32, MCK_MQPR, MCK_MQPR, MCK_Imm0_31 }, },
14012 { 3286 /* vqshl */, ARM::MVE_VQSHL_by_vecu8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
14013 { 3286 /* vqshl */, ARM::MVE_VSLIimmu8, Convert__Reg1_2__Reg1_3__Imm0_71_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u8, MCK_MQPR, MCK_MQPR, MCK_Imm0_7 }, },
14030 { 3292 /* vqshlu */, ARM::MVE_VQSHLU_imms16, Convert__Reg1_2__Reg1_3__Imm0_151_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_Imm0_15 }, },
14031 { 3292 /* vqshlu */, ARM::MVE_VQSHLU_imms32, Convert__Reg1_2__Reg1_3__Imm0_311_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_Imm0_31 }, },
14032 { 3292 /* vqshlu */, ARM::MVE_VQSHLU_imms8, Convert__Reg1_2__Reg1_3__Imm0_71_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s8, MCK_MQPR, MCK_MQPR, MCK_Imm0_7 }, },
14086 { 3348 /* vqsub */, ARM::MVE_VQSUBs16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
14087 { 3348 /* vqsub */, ARM::MVE_VQSUB_qr_s16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_rGPR }, },
14088 { 3348 /* vqsub */, ARM::MVE_VQSUBs32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
14089 { 3348 /* vqsub */, ARM::MVE_VQSUB_qr_s32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_rGPR }, },
14090 { 3348 /* vqsub */, ARM::MVE_VQSUBs8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
14091 { 3348 /* vqsub */, ARM::MVE_VQSUB_qr_s8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s8, MCK_MQPR, MCK_MQPR, MCK_rGPR }, },
14092 { 3348 /* vqsub */, ARM::MVE_VQSUBu16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
14093 { 3348 /* vqsub */, ARM::MVE_VQSUB_qr_u16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u16, MCK_MQPR, MCK_MQPR, MCK_rGPR }, },
14094 { 3348 /* vqsub */, ARM::MVE_VQSUBu32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
14095 { 3348 /* vqsub */, ARM::MVE_VQSUB_qr_u32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u32, MCK_MQPR, MCK_MQPR, MCK_rGPR }, },
14096 { 3348 /* vqsub */, ARM::MVE_VQSUBu8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
14097 { 3348 /* vqsub */, ARM::MVE_VQSUB_qr_u8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u8, MCK_MQPR, MCK_MQPR, MCK_rGPR }, },
14117 { 3376 /* vrev16 */, ARM::MVE_VREV16_8, Convert__Reg1_2__Reg1_3__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_8, MCK_MQPR, MCK_MQPR }, },
14122 { 3383 /* vrev32 */, ARM::MVE_VREV32_16, Convert__Reg1_2__Reg1_3__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_16, MCK_MQPR, MCK_MQPR }, },
14123 { 3383 /* vrev32 */, ARM::MVE_VREV32_8, Convert__Reg1_2__Reg1_3__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_8, MCK_MQPR, MCK_MQPR }, },
14130 { 3390 /* vrev64 */, ARM::MVE_VREV64_16, Convert__Reg1_2__Reg1_3__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_16, MCK_MQPR, MCK_MQPR }, },
14131 { 3390 /* vrev64 */, ARM::MVE_VREV64_32, Convert__Reg1_2__Reg1_3__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_32, MCK_MQPR, MCK_MQPR }, },
14132 { 3390 /* vrev64 */, ARM::MVE_VREV64_8, Convert__Reg1_2__Reg1_3__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_8, MCK_MQPR, MCK_MQPR }, },
14157 { 3397 /* vrhadd */, ARM::MVE_VRHADDs16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
14158 { 3397 /* vrhadd */, ARM::MVE_VRHADDs32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
14159 { 3397 /* vrhadd */, ARM::MVE_VRHADDs8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
14160 { 3397 /* vrhadd */, ARM::MVE_VRHADDu16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
14161 { 3397 /* vrhadd */, ARM::MVE_VRHADDu32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
14162 { 3397 /* vrhadd */, ARM::MVE_VRHADDu8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
14176 { 3404 /* vrinta */, ARM::MVE_VRINTf32A, Convert__Reg1_2__Reg1_3__VPTPredR3_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_f32, MCK_MQPR, MCK_MQPR }, },
14177 { 3404 /* vrinta */, ARM::MVE_VRINTf16A, Convert__Reg1_2__Reg1_3__VPTPredR3_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_f16, MCK_MQPR, MCK_MQPR }, },
14191 { 3411 /* vrintm */, ARM::MVE_VRINTf32M, Convert__Reg1_2__Reg1_3__VPTPredR3_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_f32, MCK_MQPR, MCK_MQPR }, },
14192 { 3411 /* vrintm */, ARM::MVE_VRINTf16M, Convert__Reg1_2__Reg1_3__VPTPredR3_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_f16, MCK_MQPR, MCK_MQPR }, },
14206 { 3418 /* vrintn */, ARM::MVE_VRINTf32N, Convert__Reg1_2__Reg1_3__VPTPredR3_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_f32, MCK_MQPR, MCK_MQPR }, },
14207 { 3418 /* vrintn */, ARM::MVE_VRINTf16N, Convert__Reg1_2__Reg1_3__VPTPredR3_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_f16, MCK_MQPR, MCK_MQPR }, },
14221 { 3425 /* vrintp */, ARM::MVE_VRINTf32P, Convert__Reg1_2__Reg1_3__VPTPredR3_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_f32, MCK_MQPR, MCK_MQPR }, },
14222 { 3425 /* vrintp */, ARM::MVE_VRINTf16P, Convert__Reg1_2__Reg1_3__VPTPredR3_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_f16, MCK_MQPR, MCK_MQPR }, },
14240 { 3439 /* vrintx */, ARM::MVE_VRINTf32X, Convert__Reg1_2__Reg1_3__VPTPredR3_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_f32, MCK_MQPR, MCK_MQPR }, },
14241 { 3439 /* vrintx */, ARM::MVE_VRINTf16X, Convert__Reg1_2__Reg1_3__VPTPredR3_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_f16, MCK_MQPR, MCK_MQPR }, },
14256 { 3446 /* vrintz */, ARM::MVE_VRINTf32Z, Convert__Reg1_2__Reg1_3__VPTPredR3_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_f32, MCK_MQPR, MCK_MQPR }, },
14257 { 3446 /* vrintz */, ARM::MVE_VRINTf16Z, Convert__Reg1_2__Reg1_3__VPTPredR3_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_f16, MCK_MQPR, MCK_MQPR }, },
14275 { 3568 /* vrmulh */, ARM::MVE_VRMULHs16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
14276 { 3568 /* vrmulh */, ARM::MVE_VRMULHs32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
14277 { 3568 /* vrmulh */, ARM::MVE_VRMULHs8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
14278 { 3568 /* vrmulh */, ARM::MVE_VRMULHu16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
14279 { 3568 /* vrmulh */, ARM::MVE_VRMULHu32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
14280 { 3568 /* vrmulh */, ARM::MVE_VRMULHu8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
14319 { 3575 /* vrshl */, ARM::MVE_VRSHL_by_vecs16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
14320 { 3575 /* vrshl */, ARM::MVE_VRSHL_by_vecs32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
14321 { 3575 /* vrshl */, ARM::MVE_VRSHL_by_vecs8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
14322 { 3575 /* vrshl */, ARM::MVE_VRSHL_by_vecu16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
14323 { 3575 /* vrshl */, ARM::MVE_VRSHL_by_vecu32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
14324 { 3575 /* vrshl */, ARM::MVE_VRSHL_by_vecu8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
14357 { 3581 /* vrshr */, ARM::MVE_VRSHR_imms16, Convert__Reg1_2__Reg1_3__ShrImm161_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_ShrImm16 }, },
14358 { 3581 /* vrshr */, ARM::MVE_VRSHR_imms32, Convert__Reg1_2__Reg1_3__ShrImm321_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_ShrImm32 }, },
14359 { 3581 /* vrshr */, ARM::MVE_VRSHR_imms8, Convert__Reg1_2__Reg1_3__ShrImm81_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s8, MCK_MQPR, MCK_MQPR, MCK_ShrImm8 }, },
14360 { 3581 /* vrshr */, ARM::MVE_VRSHR_immu16, Convert__Reg1_2__Reg1_3__ShrImm161_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u16, MCK_MQPR, MCK_MQPR, MCK_ShrImm16 }, },
14361 { 3581 /* vrshr */, ARM::MVE_VRSHR_immu32, Convert__Reg1_2__Reg1_3__ShrImm321_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u32, MCK_MQPR, MCK_MQPR, MCK_ShrImm32 }, },
14362 { 3581 /* vrshr */, ARM::MVE_VRSHR_immu8, Convert__Reg1_2__Reg1_3__ShrImm81_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u8, MCK_MQPR, MCK_MQPR, MCK_ShrImm8 }, },
14419 { 3640 /* vsbc */, ARM::MVE_VSBC, Convert__Reg1_2__imm_95_0__Reg1_3__Reg1_4__imm_95_0__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_i32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
14420 { 3645 /* vsbci */, ARM::MVE_VSBCI, Convert__Reg1_2__imm_95_0__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_i32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
14493 { 3693 /* vshl */, ARM::MVE_VSHL_by_vecs16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
14494 { 3693 /* vshl */, ARM::MVE_VSHL_by_vecs32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
14495 { 3693 /* vshl */, ARM::MVE_VSHL_by_vecs8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
14496 { 3693 /* vshl */, ARM::MVE_VSHL_by_vecu16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
14497 { 3693 /* vshl */, ARM::MVE_VSHL_by_vecu32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
14498 { 3693 /* vshl */, ARM::MVE_VSHL_by_vecu8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
14499 { 3693 /* vshl */, ARM::MVE_VSHL_immi16, Convert__Reg1_2__Reg1_3__Imm0_151_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_i16, MCK_MQPR, MCK_MQPR, MCK_Imm0_15 }, },
14500 { 3693 /* vshl */, ARM::MVE_VSHL_immi32, Convert__Reg1_2__Reg1_3__Imm0_311_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_i32, MCK_MQPR, MCK_MQPR, MCK_Imm0_31 }, },
14501 { 3693 /* vshl */, ARM::MVE_VSHL_immi8, Convert__Reg1_2__Reg1_3__Imm0_71_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_i8, MCK_MQPR, MCK_MQPR, MCK_Imm0_7 }, },
14512 { 3710 /* vshllb */, ARM::MVE_VSHLL_lws16bh, Convert__Reg1_2__Reg1_3__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK__HASH_16 }, },
14513 { 3710 /* vshllb */, ARM::MVE_VSHLL_imms16bh, Convert__Reg1_2__Reg1_3__MVEShiftImm1_151_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_MVEShiftImm1_15 }, },
14514 { 3710 /* vshllb */, ARM::MVE_VSHLL_lws8bh, Convert__Reg1_2__Reg1_3__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s8, MCK_MQPR, MCK_MQPR, MCK__HASH_8 }, },
14515 { 3710 /* vshllb */, ARM::MVE_VSHLL_imms8bh, Convert__Reg1_2__Reg1_3__MVEShiftImm1_71_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s8, MCK_MQPR, MCK_MQPR, MCK_MVEShiftImm1_7 }, },
14516 { 3710 /* vshllb */, ARM::MVE_VSHLL_lwu16bh, Convert__Reg1_2__Reg1_3__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u16, MCK_MQPR, MCK_MQPR, MCK__HASH_16 }, },
14517 { 3710 /* vshllb */, ARM::MVE_VSHLL_immu16bh, Convert__Reg1_2__Reg1_3__MVEShiftImm1_151_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u16, MCK_MQPR, MCK_MQPR, MCK_MVEShiftImm1_15 }, },
14518 { 3710 /* vshllb */, ARM::MVE_VSHLL_lwu8bh, Convert__Reg1_2__Reg1_3__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u8, MCK_MQPR, MCK_MQPR, MCK__HASH_8 }, },
14519 { 3710 /* vshllb */, ARM::MVE_VSHLL_immu8bh, Convert__Reg1_2__Reg1_3__MVEShiftImm1_71_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u8, MCK_MQPR, MCK_MQPR, MCK_MVEShiftImm1_7 }, },
14520 { 3717 /* vshllt */, ARM::MVE_VSHLL_lws16th, Convert__Reg1_2__Reg1_3__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK__HASH_16 }, },
14521 { 3717 /* vshllt */, ARM::MVE_VSHLL_imms16th, Convert__Reg1_2__Reg1_3__MVEShiftImm1_151_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_MVEShiftImm1_15 }, },
14522 { 3717 /* vshllt */, ARM::MVE_VSHLL_lws8th, Convert__Reg1_2__Reg1_3__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s8, MCK_MQPR, MCK_MQPR, MCK__HASH_8 }, },
14523 { 3717 /* vshllt */, ARM::MVE_VSHLL_imms8th, Convert__Reg1_2__Reg1_3__MVEShiftImm1_71_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s8, MCK_MQPR, MCK_MQPR, MCK_MVEShiftImm1_7 }, },
14524 { 3717 /* vshllt */, ARM::MVE_VSHLL_lwu16th, Convert__Reg1_2__Reg1_3__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u16, MCK_MQPR, MCK_MQPR, MCK__HASH_16 }, },
14525 { 3717 /* vshllt */, ARM::MVE_VSHLL_immu16th, Convert__Reg1_2__Reg1_3__MVEShiftImm1_151_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u16, MCK_MQPR, MCK_MQPR, MCK_MVEShiftImm1_15 }, },
14526 { 3717 /* vshllt */, ARM::MVE_VSHLL_lwu8th, Convert__Reg1_2__Reg1_3__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u8, MCK_MQPR, MCK_MQPR, MCK__HASH_8 }, },
14527 { 3717 /* vshllt */, ARM::MVE_VSHLL_immu8th, Convert__Reg1_2__Reg1_3__MVEShiftImm1_71_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u8, MCK_MQPR, MCK_MQPR, MCK_MVEShiftImm1_7 }, },
14560 { 3724 /* vshr */, ARM::MVE_VSHR_imms16, Convert__Reg1_2__Reg1_3__ShrImm161_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s16, MCK_MQPR, MCK_MQPR, MCK_ShrImm16 }, },
14561 { 3724 /* vshr */, ARM::MVE_VSHR_imms32, Convert__Reg1_2__Reg1_3__ShrImm321_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s32, MCK_MQPR, MCK_MQPR, MCK_ShrImm32 }, },
14562 { 3724 /* vshr */, ARM::MVE_VSHR_imms8, Convert__Reg1_2__Reg1_3__ShrImm81_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_s8, MCK_MQPR, MCK_MQPR, MCK_ShrImm8 }, },
14563 { 3724 /* vshr */, ARM::MVE_VSHR_immu16, Convert__Reg1_2__Reg1_3__ShrImm161_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u16, MCK_MQPR, MCK_MQPR, MCK_ShrImm16 }, },
14564 { 3724 /* vshr */, ARM::MVE_VSHR_immu32, Convert__Reg1_2__Reg1_3__ShrImm321_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u32, MCK_MQPR, MCK_MQPR, MCK_ShrImm32 }, },
14565 { 3724 /* vshr */, ARM::MVE_VSHR_immu8, Convert__Reg1_2__Reg1_3__ShrImm81_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_u8, MCK_MQPR, MCK_MQPR, MCK_ShrImm8 }, },
14971 { 3869 /* vsub */, ARM::MVE_VSUBf32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_f32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
14972 { 3869 /* vsub */, ARM::MVE_VSUB_qr_f32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_f32, MCK_MQPR, MCK_MQPR, MCK_rGPR }, },
14973 { 3869 /* vsub */, ARM::MVE_VSUBi16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_i16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
14974 { 3869 /* vsub */, ARM::MVE_VSUB_qr_i16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_i16, MCK_MQPR, MCK_MQPR, MCK_rGPR }, },
14975 { 3869 /* vsub */, ARM::MVE_VSUBi32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_i32, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
14976 { 3869 /* vsub */, ARM::MVE_VSUB_qr_i32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_i32, MCK_MQPR, MCK_MQPR, MCK_rGPR }, },
14977 { 3869 /* vsub */, ARM::MVE_VSUBi8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_i8, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
14978 { 3869 /* vsub */, ARM::MVE_VSUB_qr_i8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEInt, { MCK_VPTPredR, MCK__DOT_i8, MCK_MQPR, MCK_MQPR, MCK_rGPR }, },
14979 { 3869 /* vsub */, ARM::MVE_VSUBf16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_f16, MCK_MQPR, MCK_MQPR, MCK_MQPR }, },
14980 { 3869 /* vsub */, ARM::MVE_VSUB_qr_f16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEFloat, { MCK_VPTPredR, MCK__DOT_f16, MCK_MQPR, MCK_MQPR, MCK_rGPR }, },