reference, declaration → definition definition → references, declarations, derived classes, virtual overrides reference to multiple definitions → definitions unreferenced |
8706 case MCK_TMemImm7Shift0Offset: { 9700 case MCK_TMemImm7Shift0Offset: return "MCK_TMemImm7Shift0Offset"; 12895 { 2423 /* vldrb */, ARM::MVE_VLDRBS16, Convert__Reg1_2__TMemImm7Shift0Offset2_3__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s16, MCK_MQPR, MCK_TMemImm7Shift0Offset }, }, 12897 { 2423 /* vldrb */, ARM::MVE_VLDRBS32, Convert__Reg1_2__TMemImm7Shift0Offset2_3__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_MQPR, MCK_TMemImm7Shift0Offset }, }, 12899 { 2423 /* vldrb */, ARM::MVE_VLDRBU16, Convert__Reg1_2__TMemImm7Shift0Offset2_3__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u16, MCK_MQPR, MCK_TMemImm7Shift0Offset }, }, 12901 { 2423 /* vldrb */, ARM::MVE_VLDRBU32, Convert__Reg1_2__TMemImm7Shift0Offset2_3__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u32, MCK_MQPR, MCK_TMemImm7Shift0Offset }, }, 12905 { 2423 /* vldrb */, ARM::MVE_VLDRBS16_pre, Convert__imm_95_0__Reg1_2__TMemImm7Shift0Offset2_3__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s16, MCK_MQPR, MCK_TMemImm7Shift0Offset, MCK__EXCLAIM_ }, }, 12907 { 2423 /* vldrb */, ARM::MVE_VLDRBS32_pre, Convert__imm_95_0__Reg1_2__TMemImm7Shift0Offset2_3__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_MQPR, MCK_TMemImm7Shift0Offset, MCK__EXCLAIM_ }, }, 12909 { 2423 /* vldrb */, ARM::MVE_VLDRBU16_pre, Convert__imm_95_0__Reg1_2__TMemImm7Shift0Offset2_3__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u16, MCK_MQPR, MCK_TMemImm7Shift0Offset, MCK__EXCLAIM_ }, }, 12911 { 2423 /* vldrb */, ARM::MVE_VLDRBU32_pre, Convert__imm_95_0__Reg1_2__TMemImm7Shift0Offset2_3__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u32, MCK_MQPR, MCK_TMemImm7Shift0Offset, MCK__EXCLAIM_ }, }, 14909 { 3845 /* vstrb */, ARM::MVE_VSTRB16, Convert__Reg1_2__TMemImm7Shift0Offset2_3__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_16, MCK_MQPR, MCK_TMemImm7Shift0Offset }, }, 14911 { 3845 /* vstrb */, ARM::MVE_VSTRB32, Convert__Reg1_2__TMemImm7Shift0Offset2_3__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_32, MCK_MQPR, MCK_TMemImm7Shift0Offset }, }, 14915 { 3845 /* vstrb */, ARM::MVE_VSTRB16_pre, Convert__imm_95_0__Reg1_2__TMemImm7Shift0Offset2_3__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_16, MCK_MQPR, MCK_TMemImm7Shift0Offset, MCK__EXCLAIM_ }, }, 14917 { 3845 /* vstrb */, ARM::MVE_VSTRB32_pre, Convert__imm_95_0__Reg1_2__TMemImm7Shift0Offset2_3__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_32, MCK_MQPR, MCK_TMemImm7Shift0Offset, MCK__EXCLAIM_ }, },