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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/ARM/ARMGenAsmMatcher.inc 8107 case MCK_RotImm: {
9617 case MCK_RotImm: return "MCK_RotImm";
11390 { 1627 /* sxtab */, ARM::t2SXTAB, Convert__Reg1_1__Reg1_2__Reg1_3__RotImm1_4__CondCode2_0, AMFBS_HasDSP_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR, MCK_RotImm }, },
11391 { 1627 /* sxtab */, ARM::SXTAB, Convert__Reg1_1__Reg1_2__Reg1_3__RotImm1_4__CondCode2_0, AMFBS_IsARM_HasV6, { MCK_CondCode, MCK_GPRnopc, MCK_GPR, MCK_GPRnopc, MCK_RotImm }, },
11394 { 1633 /* sxtab16 */, ARM::t2SXTAB16, Convert__Reg1_1__Reg1_2__Reg1_3__RotImm1_4__CondCode2_0, AMFBS_HasDSP_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR, MCK_RotImm }, },
11395 { 1633 /* sxtab16 */, ARM::SXTAB16, Convert__Reg1_1__Reg1_2__Reg1_3__RotImm1_4__CondCode2_0, AMFBS_IsARM_HasV6, { MCK_CondCode, MCK_GPRnopc, MCK_GPR, MCK_GPRnopc, MCK_RotImm }, },
11398 { 1641 /* sxtah */, ARM::t2SXTAH, Convert__Reg1_1__Reg1_2__Reg1_3__RotImm1_4__CondCode2_0, AMFBS_HasDSP_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR, MCK_RotImm }, },
11399 { 1641 /* sxtah */, ARM::SXTAH, Convert__Reg1_1__Reg1_2__Reg1_3__RotImm1_4__CondCode2_0, AMFBS_IsARM_HasV6, { MCK_CondCode, MCK_GPRnopc, MCK_GPR, MCK_GPRnopc, MCK_RotImm }, },
11404 { 1647 /* sxtb */, ARM::t2SXTB, Convert__Reg1_1__Reg1_2__RotImm1_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_RotImm }, },
11405 { 1647 /* sxtb */, ARM::SXTB, Convert__Reg1_1__Reg1_2__RotImm1_3__CondCode2_0, AMFBS_IsARM_HasV6, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_RotImm }, },
11406 { 1647 /* sxtb */, ARM::t2SXTB, Convert__Reg1_2__Reg1_3__RotImm1_4__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR, MCK_RotImm }, },
11409 { 1652 /* sxtb16 */, ARM::t2SXTB16, Convert__Reg1_1__Reg1_2__RotImm1_3__CondCode2_0, AMFBS_HasDSP_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_RotImm }, },
11410 { 1652 /* sxtb16 */, ARM::t2SXTB16, Convert__Reg1_1__Reg1_2__RotImm1_3__CondCode2_0, AMFBS_HasDSP_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_RotImm }, },
11411 { 1652 /* sxtb16 */, ARM::SXTB16, Convert__Reg1_1__Reg1_2__RotImm1_3__CondCode2_0, AMFBS_IsARM_HasV6, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_RotImm }, },
11416 { 1659 /* sxth */, ARM::t2SXTH, Convert__Reg1_1__Reg1_2__RotImm1_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_RotImm }, },
11417 { 1659 /* sxth */, ARM::SXTH, Convert__Reg1_1__Reg1_2__RotImm1_3__CondCode2_0, AMFBS_IsARM_HasV6, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_RotImm }, },
11418 { 1659 /* sxth */, ARM::t2SXTH, Convert__Reg1_2__Reg1_3__RotImm1_4__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR, MCK_RotImm }, },
11520 { 1923 /* uxtab */, ARM::t2UXTAB, Convert__Reg1_1__Reg1_2__Reg1_3__RotImm1_4__CondCode2_0, AMFBS_HasDSP_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR, MCK_RotImm }, },
11521 { 1923 /* uxtab */, ARM::UXTAB, Convert__Reg1_1__Reg1_2__Reg1_3__RotImm1_4__CondCode2_0, AMFBS_IsARM_HasV6, { MCK_CondCode, MCK_GPRnopc, MCK_GPR, MCK_GPRnopc, MCK_RotImm }, },
11524 { 1929 /* uxtab16 */, ARM::t2UXTAB16, Convert__Reg1_1__Reg1_2__Reg1_3__RotImm1_4__CondCode2_0, AMFBS_HasDSP_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR, MCK_RotImm }, },
11525 { 1929 /* uxtab16 */, ARM::UXTAB16, Convert__Reg1_1__Reg1_2__Reg1_3__RotImm1_4__CondCode2_0, AMFBS_IsARM_HasV6, { MCK_CondCode, MCK_GPRnopc, MCK_GPR, MCK_GPRnopc, MCK_RotImm }, },
11528 { 1937 /* uxtah */, ARM::t2UXTAH, Convert__Reg1_1__Reg1_2__Reg1_3__RotImm1_4__CondCode2_0, AMFBS_HasDSP_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_rGPR, MCK_RotImm }, },
11529 { 1937 /* uxtah */, ARM::UXTAH, Convert__Reg1_1__Reg1_2__Reg1_3__RotImm1_4__CondCode2_0, AMFBS_IsARM_HasV6, { MCK_CondCode, MCK_GPRnopc, MCK_GPR, MCK_GPRnopc, MCK_RotImm }, },
11534 { 1943 /* uxtb */, ARM::t2UXTB, Convert__Reg1_1__Reg1_2__RotImm1_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_RotImm }, },
11535 { 1943 /* uxtb */, ARM::UXTB, Convert__Reg1_1__Reg1_2__RotImm1_3__CondCode2_0, AMFBS_IsARM_HasV6, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_RotImm }, },
11536 { 1943 /* uxtb */, ARM::t2UXTB, Convert__Reg1_2__Reg1_3__RotImm1_4__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR, MCK_RotImm }, },
11539 { 1948 /* uxtb16 */, ARM::t2UXTB16, Convert__Reg1_1__Reg1_2__RotImm1_3__CondCode2_0, AMFBS_HasDSP_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_RotImm }, },
11540 { 1948 /* uxtb16 */, ARM::t2UXTB16, Convert__Reg1_1__Reg1_2__RotImm1_3__CondCode2_0, AMFBS_HasDSP_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_RotImm }, },
11541 { 1948 /* uxtb16 */, ARM::UXTB16, Convert__Reg1_1__Reg1_2__RotImm1_3__CondCode2_0, AMFBS_IsARM_HasV6, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_RotImm }, },
11546 { 1955 /* uxth */, ARM::t2UXTH, Convert__Reg1_1__Reg1_2__RotImm1_3__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK_rGPR, MCK_rGPR, MCK_RotImm }, },
11547 { 1955 /* uxth */, ARM::UXTH, Convert__Reg1_1__Reg1_2__RotImm1_3__CondCode2_0, AMFBS_IsARM_HasV6, { MCK_CondCode, MCK_GPRnopc, MCK_GPRnopc, MCK_RotImm }, },
11548 { 1955 /* uxth */, ARM::t2UXTH, Convert__Reg1_2__Reg1_3__RotImm1_4__CondCode2_0, AMFBS_IsThumb2, { MCK_CondCode, MCK__DOT_w, MCK_rGPR, MCK_rGPR, MCK_RotImm }, },
15636 { 1627 /* sxtab */, 16 /* 4 */, MCK_RotImm, AMFBS_HasDSP_IsThumb2 },
15637 { 1627 /* sxtab */, 16 /* 4 */, MCK_RotImm, AMFBS_IsARM_HasV6 },
15638 { 1633 /* sxtab16 */, 16 /* 4 */, MCK_RotImm, AMFBS_HasDSP_IsThumb2 },
15639 { 1633 /* sxtab16 */, 16 /* 4 */, MCK_RotImm, AMFBS_IsARM_HasV6 },
15640 { 1641 /* sxtah */, 16 /* 4 */, MCK_RotImm, AMFBS_HasDSP_IsThumb2 },
15641 { 1641 /* sxtah */, 16 /* 4 */, MCK_RotImm, AMFBS_IsARM_HasV6 },
15642 { 1647 /* sxtb */, 8 /* 3 */, MCK_RotImm, AMFBS_IsThumb2 },
15643 { 1647 /* sxtb */, 8 /* 3 */, MCK_RotImm, AMFBS_IsARM_HasV6 },
15644 { 1647 /* sxtb */, 16 /* 4 */, MCK_RotImm, AMFBS_IsThumb2 },
15645 { 1652 /* sxtb16 */, 8 /* 3 */, MCK_RotImm, AMFBS_HasDSP_IsThumb2 },
15646 { 1652 /* sxtb16 */, 8 /* 3 */, MCK_RotImm, AMFBS_HasDSP_IsThumb2 },
15647 { 1652 /* sxtb16 */, 8 /* 3 */, MCK_RotImm, AMFBS_IsARM_HasV6 },
15648 { 1659 /* sxth */, 8 /* 3 */, MCK_RotImm, AMFBS_IsThumb2 },
15649 { 1659 /* sxth */, 8 /* 3 */, MCK_RotImm, AMFBS_IsARM_HasV6 },
15650 { 1659 /* sxth */, 16 /* 4 */, MCK_RotImm, AMFBS_IsThumb2 },
15657 { 1923 /* uxtab */, 16 /* 4 */, MCK_RotImm, AMFBS_HasDSP_IsThumb2 },
15658 { 1923 /* uxtab */, 16 /* 4 */, MCK_RotImm, AMFBS_IsARM_HasV6 },
15659 { 1929 /* uxtab16 */, 16 /* 4 */, MCK_RotImm, AMFBS_HasDSP_IsThumb2 },
15660 { 1929 /* uxtab16 */, 16 /* 4 */, MCK_RotImm, AMFBS_IsARM_HasV6 },
15661 { 1937 /* uxtah */, 16 /* 4 */, MCK_RotImm, AMFBS_HasDSP_IsThumb2 },
15662 { 1937 /* uxtah */, 16 /* 4 */, MCK_RotImm, AMFBS_IsARM_HasV6 },
15663 { 1943 /* uxtb */, 8 /* 3 */, MCK_RotImm, AMFBS_IsThumb2 },
15664 { 1943 /* uxtb */, 8 /* 3 */, MCK_RotImm, AMFBS_IsARM_HasV6 },
15665 { 1943 /* uxtb */, 16 /* 4 */, MCK_RotImm, AMFBS_IsThumb2 },
15666 { 1948 /* uxtb16 */, 8 /* 3 */, MCK_RotImm, AMFBS_HasDSP_IsThumb2 },
15667 { 1948 /* uxtb16 */, 8 /* 3 */, MCK_RotImm, AMFBS_HasDSP_IsThumb2 },
15668 { 1948 /* uxtb16 */, 8 /* 3 */, MCK_RotImm, AMFBS_IsARM_HasV6 },
15669 { 1955 /* uxth */, 8 /* 3 */, MCK_RotImm, AMFBS_IsThumb2 },
15670 { 1955 /* uxth */, 8 /* 3 */, MCK_RotImm, AMFBS_IsARM_HasV6 },
15671 { 1955 /* uxth */, 16 /* 4 */, MCK_RotImm, AMFBS_IsThumb2 },
16243 case MCK_RotImm: