reference, declaration → definition definition → references, declarations, derived classes, virtual overrides reference to multiple definitions → definitions unreferenced |
7984 case MCK_MemRegRQS0Offset: { 9600 case MCK_MemRegRQS0Offset: return "MCK_MemRegRQS0Offset"; 12894 { 2423 /* vldrb */, ARM::MVE_VLDRBS16_rq, Convert__Reg1_2__MemRegRQS0Offset2_3__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s16, MCK_MQPR, MCK_MemRegRQS0Offset }, }, 12896 { 2423 /* vldrb */, ARM::MVE_VLDRBS32_rq, Convert__Reg1_2__MemRegRQS0Offset2_3__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_MQPR, MCK_MemRegRQS0Offset }, }, 12898 { 2423 /* vldrb */, ARM::MVE_VLDRBU16_rq, Convert__Reg1_2__MemRegRQS0Offset2_3__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u16, MCK_MQPR, MCK_MemRegRQS0Offset }, }, 12900 { 2423 /* vldrb */, ARM::MVE_VLDRBU32_rq, Convert__Reg1_2__MemRegRQS0Offset2_3__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u32, MCK_MQPR, MCK_MemRegRQS0Offset }, }, 12903 { 2423 /* vldrb */, ARM::MVE_VLDRBU8_rq, Convert__Reg1_2__MemRegRQS0Offset2_3__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u8, MCK_MQPR, MCK_MemRegRQS0Offset }, }, 12915 { 2429 /* vldrd */, ARM::MVE_VLDRDU64_rq_u, Convert__Reg1_2__MemRegRQS0Offset2_3__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u64, MCK_MQPR, MCK_MemRegRQS0Offset }, }, 12918 { 2435 /* vldrh */, ARM::MVE_VLDRHS32_rq_u, Convert__Reg1_2__MemRegRQS0Offset2_3__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_MQPR, MCK_MemRegRQS0Offset }, }, 12922 { 2435 /* vldrh */, ARM::MVE_VLDRHU16_rq_u, Convert__Reg1_2__MemRegRQS0Offset2_3__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u16, MCK_MQPR, MCK_MemRegRQS0Offset }, }, 12924 { 2435 /* vldrh */, ARM::MVE_VLDRHU32_rq_u, Convert__Reg1_2__MemRegRQS0Offset2_3__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u32, MCK_MQPR, MCK_MemRegRQS0Offset }, }, 12935 { 2441 /* vldrw */, ARM::MVE_VLDRWU32_rq_u, Convert__Reg1_2__MemRegRQS0Offset2_3__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u32, MCK_MQPR, MCK_MemRegRQS0Offset }, }, 14908 { 3845 /* vstrb */, ARM::MVE_VSTRB16_rq, Convert__Reg1_2__MemRegRQS0Offset2_3__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_16, MCK_MQPR, MCK_MemRegRQS0Offset }, }, 14910 { 3845 /* vstrb */, ARM::MVE_VSTRB32_rq, Convert__Reg1_2__MemRegRQS0Offset2_3__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_32, MCK_MQPR, MCK_MemRegRQS0Offset }, }, 14913 { 3845 /* vstrb */, ARM::MVE_VSTRB8_rq, Convert__Reg1_2__MemRegRQS0Offset2_3__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_8, MCK_MQPR, MCK_MemRegRQS0Offset }, }, 14921 { 3851 /* vstrd */, ARM::MVE_VSTRD64_rq_u, Convert__Reg1_2__MemRegRQS0Offset2_3__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_64, MCK_MQPR, MCK_MemRegRQS0Offset }, }, 14925 { 3857 /* vstrh */, ARM::MVE_VSTRH16_rq_u, Convert__Reg1_2__MemRegRQS0Offset2_3__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_16, MCK_MQPR, MCK_MemRegRQS0Offset }, }, 14927 { 3857 /* vstrh */, ARM::MVE_VSTRH32_rq_u, Convert__Reg1_2__MemRegRQS0Offset2_3__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_32, MCK_MQPR, MCK_MemRegRQS0Offset }, }, 14936 { 3863 /* vstrw */, ARM::MVE_VSTRW32_rq_u, Convert__Reg1_2__MemRegRQS0Offset2_3__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_32, MCK_MQPR, MCK_MemRegRQS0Offset }, },