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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/ARM/ARMGenAsmMatcher.inc 6120 case MCK_HPR:
7332 case MCK_HPR: return true;
7339 case MCK_HPR:
9110 case ARM::S16: OpKind = MCK_HPR; break;
9111 case ARM::S17: OpKind = MCK_HPR; break;
9112 case ARM::S18: OpKind = MCK_HPR; break;
9113 case ARM::S19: OpKind = MCK_HPR; break;
9114 case ARM::S20: OpKind = MCK_HPR; break;
9115 case ARM::S21: OpKind = MCK_HPR; break;
9116 case ARM::S22: OpKind = MCK_HPR; break;
9117 case ARM::S23: OpKind = MCK_HPR; break;
9118 case ARM::S24: OpKind = MCK_HPR; break;
9119 case ARM::S25: OpKind = MCK_HPR; break;
9120 case ARM::S26: OpKind = MCK_HPR; break;
9121 case ARM::S27: OpKind = MCK_HPR; break;
9122 case ARM::S28: OpKind = MCK_HPR; break;
9123 case ARM::S29: OpKind = MCK_HPR; break;
9124 case ARM::S30: OpKind = MCK_HPR; break;
9125 case ARM::S31: OpKind = MCK_HPR; break;
9519 case MCK_HPR: return "MCK_HPR";
10500 { 337 /* fadds */, ARM::VADDS, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK_HPR, MCK_HPR, MCK_HPR }, },
10500 { 337 /* fadds */, ARM::VADDS, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK_HPR, MCK_HPR, MCK_HPR }, },
10500 { 337 /* fadds */, ARM::VADDS, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK_HPR, MCK_HPR, MCK_HPR }, },
10502 { 350 /* fcmpzs */, ARM::VCMPZS, Convert__Reg1_1__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK_HPR }, },
10504 { 365 /* fconsts */, ARM::FCONSTS, Convert__Reg1_1__FPImm1_2__CondCode2_0, AMFBS_HasVFP3, { MCK_CondCode, MCK_HPR, MCK_FPImm }, },
10515 { 430 /* fsubs */, ARM::VSUBS, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK_HPR, MCK_HPR, MCK_HPR }, },
10515 { 430 /* fsubs */, ARM::VSUBS, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK_HPR, MCK_HPR, MCK_HPR }, },
10515 { 430 /* fsubs */, ARM::VSUBS, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK_HPR, MCK_HPR, MCK_HPR }, },
11627 { 1988 /* vabs */, ARM::VABSS, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK__DOT_f32, MCK_HPR, MCK_HPR }, },
11627 { 1988 /* vabs */, ARM::VABSS, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK__DOT_f32, MCK_HPR, MCK_HPR }, },
11631 { 1988 /* vabs */, ARM::VABSH, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_HPR, MCK_HPR }, },
11631 { 1988 /* vabs */, ARM::VABSH, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_HPR, MCK_HPR }, },
11673 { 2028 /* vadd */, ARM::VADDS, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK__DOT_f32, MCK_HPR, MCK_HPR }, },
11673 { 2028 /* vadd */, ARM::VADDS, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK__DOT_f32, MCK_HPR, MCK_HPR }, },
11685 { 2028 /* vadd */, ARM::VADDH, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_HPR, MCK_HPR }, },
11685 { 2028 /* vadd */, ARM::VADDH, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_HPR, MCK_HPR }, },
11688 { 2028 /* vadd */, ARM::VADDS, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK__DOT_f32, MCK_HPR, MCK_HPR, MCK_HPR }, },
11688 { 2028 /* vadd */, ARM::VADDS, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK__DOT_f32, MCK_HPR, MCK_HPR, MCK_HPR }, },
11688 { 2028 /* vadd */, ARM::VADDS, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK__DOT_f32, MCK_HPR, MCK_HPR, MCK_HPR }, },
11700 { 2028 /* vadd */, ARM::VADDH, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_HPR, MCK_HPR, MCK_HPR }, },
11700 { 2028 /* vadd */, ARM::VADDH, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_HPR, MCK_HPR, MCK_HPR }, },
11700 { 2028 /* vadd */, ARM::VADDH, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_HPR, MCK_HPR, MCK_HPR }, },
12110 { 2158 /* vcmp */, ARM::VCMPZS, Convert__Reg1_2__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK__DOT_f32, MCK_HPR, MCK__HASH_0 }, },
12111 { 2158 /* vcmp */, ARM::VCMPS, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK__DOT_f32, MCK_HPR, MCK_HPR }, },
12111 { 2158 /* vcmp */, ARM::VCMPS, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK__DOT_f32, MCK_HPR, MCK_HPR }, },
12114 { 2158 /* vcmp */, ARM::VCMPZH, Convert__Reg1_2__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_HPR, MCK__HASH_0 }, },
12115 { 2158 /* vcmp */, ARM::VCMPH, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_HPR, MCK_HPR }, },
12115 { 2158 /* vcmp */, ARM::VCMPH, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_HPR, MCK_HPR }, },
12138 { 2163 /* vcmpe */, ARM::VCMPEZS, Convert__Reg1_2__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK__DOT_f32, MCK_HPR, MCK__HASH_0 }, },
12139 { 2163 /* vcmpe */, ARM::VCMPES, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK__DOT_f32, MCK_HPR, MCK_HPR }, },
12139 { 2163 /* vcmpe */, ARM::VCMPES, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK__DOT_f32, MCK_HPR, MCK_HPR }, },
12142 { 2163 /* vcmpe */, ARM::VCMPEZH, Convert__Reg1_2__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_HPR, MCK__HASH_0 }, },
12143 { 2163 /* vcmpe */, ARM::VCMPEH, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_HPR, MCK_HPR }, },
12143 { 2163 /* vcmpe */, ARM::VCMPEH, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_HPR, MCK_HPR }, },
12156 { 2185 /* vcvt */, ARM::VTOSIZS, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK__DOT_s32, MCK__DOT_f32, MCK_HPR, MCK_HPR }, },
12156 { 2185 /* vcvt */, ARM::VTOSIZS, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK__DOT_s32, MCK__DOT_f32, MCK_HPR, MCK_HPR }, },
12157 { 2185 /* vcvt */, ARM::VTOSIZD, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasVFP2_HasDPVFP, { MCK_CondCode, MCK__DOT_s32, MCK__DOT_f64, MCK_HPR, MCK_DPR }, },
12158 { 2185 /* vcvt */, ARM::VTOSIZH, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_s32, MCK__DOT_f16, MCK_HPR, MCK_HPR }, },
12158 { 2185 /* vcvt */, ARM::VTOSIZH, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_s32, MCK__DOT_f16, MCK_HPR, MCK_HPR }, },
12163 { 2185 /* vcvt */, ARM::VTOUIZS, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK__DOT_u32, MCK__DOT_f32, MCK_HPR, MCK_HPR }, },
12163 { 2185 /* vcvt */, ARM::VTOUIZS, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK__DOT_u32, MCK__DOT_f32, MCK_HPR, MCK_HPR }, },
12164 { 2185 /* vcvt */, ARM::VTOUIZD, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasVFP2_HasDPVFP, { MCK_CondCode, MCK__DOT_u32, MCK__DOT_f64, MCK_HPR, MCK_DPR }, },
12165 { 2185 /* vcvt */, ARM::VTOUIZH, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_u32, MCK__DOT_f16, MCK_HPR, MCK_HPR }, },
12165 { 2185 /* vcvt */, ARM::VTOUIZH, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_u32, MCK__DOT_f16, MCK_HPR, MCK_HPR }, },
12168 { 2185 /* vcvt */, ARM::VSITOS, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK__DOT_f32, MCK__DOT_s32, MCK_HPR, MCK_HPR }, },
12168 { 2185 /* vcvt */, ARM::VSITOS, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK__DOT_f32, MCK__DOT_s32, MCK_HPR, MCK_HPR }, },
12171 { 2185 /* vcvt */, ARM::VUITOS, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK__DOT_f32, MCK__DOT_u32, MCK_HPR, MCK_HPR }, },
12171 { 2185 /* vcvt */, ARM::VUITOS, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK__DOT_f32, MCK__DOT_u32, MCK_HPR, MCK_HPR }, },
12172 { 2185 /* vcvt */, ARM::VCVTSD, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasVFP2_HasDPVFP, { MCK_CondCode, MCK__DOT_f32, MCK__DOT_f64, MCK_HPR, MCK_DPR }, },
12174 { 2185 /* vcvt */, ARM::VSITOD, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasVFP2_HasDPVFP, { MCK_CondCode, MCK__DOT_f64, MCK__DOT_s32, MCK_DPR, MCK_HPR }, },
12175 { 2185 /* vcvt */, ARM::VUITOD, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasVFP2_HasDPVFP, { MCK_CondCode, MCK__DOT_f64, MCK__DOT_u32, MCK_DPR, MCK_HPR }, },
12176 { 2185 /* vcvt */, ARM::VCVTDS, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasVFP2_HasDPVFP, { MCK_CondCode, MCK__DOT_f64, MCK__DOT_f32, MCK_DPR, MCK_HPR }, },
12179 { 2185 /* vcvt */, ARM::VSITOH, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK__DOT_s32, MCK_HPR, MCK_HPR }, },
12179 { 2185 /* vcvt */, ARM::VSITOH, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK__DOT_s32, MCK_HPR, MCK_HPR }, },
12182 { 2185 /* vcvt */, ARM::VUITOH, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK__DOT_u32, MCK_HPR, MCK_HPR }, },
12182 { 2185 /* vcvt */, ARM::VUITOH, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK__DOT_u32, MCK_HPR, MCK_HPR }, },
12192 { 2185 /* vcvt */, ARM::VTOSHS, Convert__Reg1_3__Tie0_4_5__FBits161_5__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK__DOT_s16, MCK__DOT_f32, MCK_HPR, MCK_HPR, MCK_FBits16 }, },
12192 { 2185 /* vcvt */, ARM::VTOSHS, Convert__Reg1_3__Tie0_4_5__FBits161_5__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK__DOT_s16, MCK__DOT_f32, MCK_HPR, MCK_HPR, MCK_FBits16 }, },
12198 { 2185 /* vcvt */, ARM::VTOSHH, Convert__Reg1_3__Tie0_4_5__FBits161_5__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_s16, MCK__DOT_f16, MCK_HPR, MCK_HPR, MCK_FBits16 }, },
12198 { 2185 /* vcvt */, ARM::VTOSHH, Convert__Reg1_3__Tie0_4_5__FBits161_5__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_s16, MCK__DOT_f16, MCK_HPR, MCK_HPR, MCK_FBits16 }, },
12203 { 2185 /* vcvt */, ARM::VTOSLS, Convert__Reg1_3__Tie0_4_5__FBits321_5__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK__DOT_s32, MCK__DOT_f32, MCK_HPR, MCK_HPR, MCK_FBits32 }, },
12203 { 2185 /* vcvt */, ARM::VTOSLS, Convert__Reg1_3__Tie0_4_5__FBits321_5__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK__DOT_s32, MCK__DOT_f32, MCK_HPR, MCK_HPR, MCK_FBits32 }, },
12205 { 2185 /* vcvt */, ARM::VTOSLH, Convert__Reg1_3__Tie0_4_5__FBits321_5__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_s32, MCK__DOT_f16, MCK_HPR, MCK_HPR, MCK_FBits32 }, },
12205 { 2185 /* vcvt */, ARM::VTOSLH, Convert__Reg1_3__Tie0_4_5__FBits321_5__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_s32, MCK__DOT_f16, MCK_HPR, MCK_HPR, MCK_FBits32 }, },
12206 { 2185 /* vcvt */, ARM::VTOUHS, Convert__Reg1_3__Tie0_4_5__FBits161_5__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK__DOT_u16, MCK__DOT_f32, MCK_HPR, MCK_HPR, MCK_FBits16 }, },
12206 { 2185 /* vcvt */, ARM::VTOUHS, Convert__Reg1_3__Tie0_4_5__FBits161_5__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK__DOT_u16, MCK__DOT_f32, MCK_HPR, MCK_HPR, MCK_FBits16 }, },
12212 { 2185 /* vcvt */, ARM::VTOUHH, Convert__Reg1_3__Tie0_4_5__FBits161_5__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_u16, MCK__DOT_f16, MCK_HPR, MCK_HPR, MCK_FBits16 }, },
12212 { 2185 /* vcvt */, ARM::VTOUHH, Convert__Reg1_3__Tie0_4_5__FBits161_5__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_u16, MCK__DOT_f16, MCK_HPR, MCK_HPR, MCK_FBits16 }, },
12217 { 2185 /* vcvt */, ARM::VTOULS, Convert__Reg1_3__Tie0_4_5__FBits321_5__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK__DOT_u32, MCK__DOT_f32, MCK_HPR, MCK_HPR, MCK_FBits32 }, },
12217 { 2185 /* vcvt */, ARM::VTOULS, Convert__Reg1_3__Tie0_4_5__FBits321_5__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK__DOT_u32, MCK__DOT_f32, MCK_HPR, MCK_HPR, MCK_FBits32 }, },
12219 { 2185 /* vcvt */, ARM::VTOULH, Convert__Reg1_3__Tie0_4_5__FBits321_5__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_u32, MCK__DOT_f16, MCK_HPR, MCK_HPR, MCK_FBits32 }, },
12219 { 2185 /* vcvt */, ARM::VTOULH, Convert__Reg1_3__Tie0_4_5__FBits321_5__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_u32, MCK__DOT_f16, MCK_HPR, MCK_HPR, MCK_FBits32 }, },
12220 { 2185 /* vcvt */, ARM::VSHTOS, Convert__Reg1_3__Tie0_4_5__FBits161_5__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK__DOT_f32, MCK__DOT_s16, MCK_HPR, MCK_HPR, MCK_FBits16 }, },
12220 { 2185 /* vcvt */, ARM::VSHTOS, Convert__Reg1_3__Tie0_4_5__FBits161_5__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK__DOT_f32, MCK__DOT_s16, MCK_HPR, MCK_HPR, MCK_FBits16 }, },
12225 { 2185 /* vcvt */, ARM::VSLTOS, Convert__Reg1_3__Tie0_4_5__FBits321_5__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK__DOT_f32, MCK__DOT_s32, MCK_HPR, MCK_HPR, MCK_FBits32 }, },
12225 { 2185 /* vcvt */, ARM::VSLTOS, Convert__Reg1_3__Tie0_4_5__FBits321_5__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK__DOT_f32, MCK__DOT_s32, MCK_HPR, MCK_HPR, MCK_FBits32 }, },
12226 { 2185 /* vcvt */, ARM::VUHTOS, Convert__Reg1_3__Tie0_4_5__FBits161_5__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK__DOT_f32, MCK__DOT_u16, MCK_HPR, MCK_HPR, MCK_FBits16 }, },
12226 { 2185 /* vcvt */, ARM::VUHTOS, Convert__Reg1_3__Tie0_4_5__FBits161_5__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK__DOT_f32, MCK__DOT_u16, MCK_HPR, MCK_HPR, MCK_FBits16 }, },
12231 { 2185 /* vcvt */, ARM::VULTOS, Convert__Reg1_3__Tie0_4_5__FBits321_5__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK__DOT_f32, MCK__DOT_u32, MCK_HPR, MCK_HPR, MCK_FBits32 }, },
12231 { 2185 /* vcvt */, ARM::VULTOS, Convert__Reg1_3__Tie0_4_5__FBits321_5__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK__DOT_f32, MCK__DOT_u32, MCK_HPR, MCK_HPR, MCK_FBits32 }, },
12240 { 2185 /* vcvt */, ARM::VSHTOH, Convert__Reg1_3__Tie0_4_5__FBits161_5__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK__DOT_s16, MCK_HPR, MCK_HPR, MCK_FBits16 }, },
12240 { 2185 /* vcvt */, ARM::VSHTOH, Convert__Reg1_3__Tie0_4_5__FBits161_5__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK__DOT_s16, MCK_HPR, MCK_HPR, MCK_FBits16 }, },
12241 { 2185 /* vcvt */, ARM::VSLTOH, Convert__Reg1_3__Tie0_4_5__FBits321_5__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK__DOT_s32, MCK_HPR, MCK_HPR, MCK_FBits32 }, },
12241 { 2185 /* vcvt */, ARM::VSLTOH, Convert__Reg1_3__Tie0_4_5__FBits321_5__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK__DOT_s32, MCK_HPR, MCK_HPR, MCK_FBits32 }, },
12246 { 2185 /* vcvt */, ARM::VUHTOH, Convert__Reg1_3__Tie0_4_5__FBits161_5__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK__DOT_u16, MCK_HPR, MCK_HPR, MCK_FBits16 }, },
12246 { 2185 /* vcvt */, ARM::VUHTOH, Convert__Reg1_3__Tie0_4_5__FBits161_5__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK__DOT_u16, MCK_HPR, MCK_HPR, MCK_FBits16 }, },
12247 { 2185 /* vcvt */, ARM::VULTOH, Convert__Reg1_3__Tie0_4_5__FBits321_5__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK__DOT_u32, MCK_HPR, MCK_HPR, MCK_FBits32 }, },
12247 { 2185 /* vcvt */, ARM::VULTOH, Convert__Reg1_3__Tie0_4_5__FBits321_5__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK__DOT_u32, MCK_HPR, MCK_HPR, MCK_FBits32 }, },
12260 { 2190 /* vcvta */, ARM::VCVTASS, Convert__Reg1_2__Reg1_3, AMFBS_HasFPARMv8, { MCK__DOT_s32, MCK__DOT_f32, MCK_HPR, MCK_HPR }, },
12260 { 2190 /* vcvta */, ARM::VCVTASS, Convert__Reg1_2__Reg1_3, AMFBS_HasFPARMv8, { MCK__DOT_s32, MCK__DOT_f32, MCK_HPR, MCK_HPR }, },
12261 { 2190 /* vcvta */, ARM::VCVTASD, Convert__Reg1_2__Reg1_3, AMFBS_HasFPARMv8_HasDPVFP, { MCK__DOT_s32, MCK__DOT_f64, MCK_HPR, MCK_DPR }, },
12262 { 2190 /* vcvta */, ARM::VCVTASH, Convert__Reg1_2__Reg1_3, AMFBS_HasFullFP16, { MCK__DOT_s32, MCK__DOT_f16, MCK_HPR, MCK_HPR }, },
12262 { 2190 /* vcvta */, ARM::VCVTASH, Convert__Reg1_2__Reg1_3, AMFBS_HasFullFP16, { MCK__DOT_s32, MCK__DOT_f16, MCK_HPR, MCK_HPR }, },
12267 { 2190 /* vcvta */, ARM::VCVTAUS, Convert__Reg1_2__Reg1_3, AMFBS_HasFPARMv8, { MCK__DOT_u32, MCK__DOT_f32, MCK_HPR, MCK_HPR }, },
12267 { 2190 /* vcvta */, ARM::VCVTAUS, Convert__Reg1_2__Reg1_3, AMFBS_HasFPARMv8, { MCK__DOT_u32, MCK__DOT_f32, MCK_HPR, MCK_HPR }, },
12268 { 2190 /* vcvta */, ARM::VCVTAUD, Convert__Reg1_2__Reg1_3, AMFBS_HasFPARMv8_HasDPVFP, { MCK__DOT_u32, MCK__DOT_f64, MCK_HPR, MCK_DPR }, },
12269 { 2190 /* vcvta */, ARM::VCVTAUH, Convert__Reg1_2__Reg1_3, AMFBS_HasFullFP16, { MCK__DOT_u32, MCK__DOT_f16, MCK_HPR, MCK_HPR }, },
12269 { 2190 /* vcvta */, ARM::VCVTAUH, Convert__Reg1_2__Reg1_3, AMFBS_HasFullFP16, { MCK__DOT_u32, MCK__DOT_f16, MCK_HPR, MCK_HPR }, },
12274 { 2196 /* vcvtb */, ARM::VCVTBHS, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasFP16, { MCK_CondCode, MCK__DOT_f32, MCK__DOT_f16, MCK_HPR, MCK_HPR }, },
12274 { 2196 /* vcvtb */, ARM::VCVTBHS, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasFP16, { MCK_CondCode, MCK__DOT_f32, MCK__DOT_f16, MCK_HPR, MCK_HPR }, },
12275 { 2196 /* vcvtb */, ARM::VCVTBHD, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasFPARMv8_HasDPVFP, { MCK_CondCode, MCK__DOT_f64, MCK__DOT_f16, MCK_DPR, MCK_HPR }, },
12276 { 2196 /* vcvtb */, ARM::VCVTBSH, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasFP16, { MCK_CondCode, MCK__DOT_f16, MCK__DOT_f32, MCK_HPR, MCK_HPR }, },
12276 { 2196 /* vcvtb */, ARM::VCVTBSH, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasFP16, { MCK_CondCode, MCK__DOT_f16, MCK__DOT_f32, MCK_HPR, MCK_HPR }, },
12277 { 2196 /* vcvtb */, ARM::VCVTBDH, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasFPARMv8_HasDPVFP, { MCK_CondCode, MCK__DOT_f16, MCK__DOT_f64, MCK_HPR, MCK_DPR }, },
12284 { 2202 /* vcvtm */, ARM::VCVTMSS, Convert__Reg1_2__Reg1_3, AMFBS_HasFPARMv8, { MCK__DOT_s32, MCK__DOT_f32, MCK_HPR, MCK_HPR }, },
12284 { 2202 /* vcvtm */, ARM::VCVTMSS, Convert__Reg1_2__Reg1_3, AMFBS_HasFPARMv8, { MCK__DOT_s32, MCK__DOT_f32, MCK_HPR, MCK_HPR }, },
12285 { 2202 /* vcvtm */, ARM::VCVTMSD, Convert__Reg1_2__Reg1_3, AMFBS_HasFPARMv8_HasDPVFP, { MCK__DOT_s32, MCK__DOT_f64, MCK_HPR, MCK_DPR }, },
12286 { 2202 /* vcvtm */, ARM::VCVTMSH, Convert__Reg1_2__Reg1_3, AMFBS_HasFullFP16, { MCK__DOT_s32, MCK__DOT_f16, MCK_HPR, MCK_HPR }, },
12286 { 2202 /* vcvtm */, ARM::VCVTMSH, Convert__Reg1_2__Reg1_3, AMFBS_HasFullFP16, { MCK__DOT_s32, MCK__DOT_f16, MCK_HPR, MCK_HPR }, },
12291 { 2202 /* vcvtm */, ARM::VCVTMUS, Convert__Reg1_2__Reg1_3, AMFBS_HasFPARMv8, { MCK__DOT_u32, MCK__DOT_f32, MCK_HPR, MCK_HPR }, },
12291 { 2202 /* vcvtm */, ARM::VCVTMUS, Convert__Reg1_2__Reg1_3, AMFBS_HasFPARMv8, { MCK__DOT_u32, MCK__DOT_f32, MCK_HPR, MCK_HPR }, },
12292 { 2202 /* vcvtm */, ARM::VCVTMUD, Convert__Reg1_2__Reg1_3, AMFBS_HasFPARMv8_HasDPVFP, { MCK__DOT_u32, MCK__DOT_f64, MCK_HPR, MCK_DPR }, },
12293 { 2202 /* vcvtm */, ARM::VCVTMUH, Convert__Reg1_2__Reg1_3, AMFBS_HasFullFP16, { MCK__DOT_u32, MCK__DOT_f16, MCK_HPR, MCK_HPR }, },
12293 { 2202 /* vcvtm */, ARM::VCVTMUH, Convert__Reg1_2__Reg1_3, AMFBS_HasFullFP16, { MCK__DOT_u32, MCK__DOT_f16, MCK_HPR, MCK_HPR }, },
12302 { 2208 /* vcvtn */, ARM::VCVTNSS, Convert__Reg1_2__Reg1_3, AMFBS_HasFPARMv8, { MCK__DOT_s32, MCK__DOT_f32, MCK_HPR, MCK_HPR }, },
12302 { 2208 /* vcvtn */, ARM::VCVTNSS, Convert__Reg1_2__Reg1_3, AMFBS_HasFPARMv8, { MCK__DOT_s32, MCK__DOT_f32, MCK_HPR, MCK_HPR }, },
12303 { 2208 /* vcvtn */, ARM::VCVTNSD, Convert__Reg1_2__Reg1_3, AMFBS_HasFPARMv8_HasDPVFP, { MCK__DOT_s32, MCK__DOT_f64, MCK_HPR, MCK_DPR }, },
12304 { 2208 /* vcvtn */, ARM::VCVTNSH, Convert__Reg1_2__Reg1_3, AMFBS_HasFullFP16, { MCK__DOT_s32, MCK__DOT_f16, MCK_HPR, MCK_HPR }, },
12304 { 2208 /* vcvtn */, ARM::VCVTNSH, Convert__Reg1_2__Reg1_3, AMFBS_HasFullFP16, { MCK__DOT_s32, MCK__DOT_f16, MCK_HPR, MCK_HPR }, },
12309 { 2208 /* vcvtn */, ARM::VCVTNUS, Convert__Reg1_2__Reg1_3, AMFBS_HasFPARMv8, { MCK__DOT_u32, MCK__DOT_f32, MCK_HPR, MCK_HPR }, },
12309 { 2208 /* vcvtn */, ARM::VCVTNUS, Convert__Reg1_2__Reg1_3, AMFBS_HasFPARMv8, { MCK__DOT_u32, MCK__DOT_f32, MCK_HPR, MCK_HPR }, },
12310 { 2208 /* vcvtn */, ARM::VCVTNUD, Convert__Reg1_2__Reg1_3, AMFBS_HasFPARMv8_HasDPVFP, { MCK__DOT_u32, MCK__DOT_f64, MCK_HPR, MCK_DPR }, },
12311 { 2208 /* vcvtn */, ARM::VCVTNUH, Convert__Reg1_2__Reg1_3, AMFBS_HasFullFP16, { MCK__DOT_u32, MCK__DOT_f16, MCK_HPR, MCK_HPR }, },
12311 { 2208 /* vcvtn */, ARM::VCVTNUH, Convert__Reg1_2__Reg1_3, AMFBS_HasFullFP16, { MCK__DOT_u32, MCK__DOT_f16, MCK_HPR, MCK_HPR }, },
12320 { 2214 /* vcvtp */, ARM::VCVTPSS, Convert__Reg1_2__Reg1_3, AMFBS_HasFPARMv8, { MCK__DOT_s32, MCK__DOT_f32, MCK_HPR, MCK_HPR }, },
12320 { 2214 /* vcvtp */, ARM::VCVTPSS, Convert__Reg1_2__Reg1_3, AMFBS_HasFPARMv8, { MCK__DOT_s32, MCK__DOT_f32, MCK_HPR, MCK_HPR }, },
12321 { 2214 /* vcvtp */, ARM::VCVTPSD, Convert__Reg1_2__Reg1_3, AMFBS_HasFPARMv8_HasDPVFP, { MCK__DOT_s32, MCK__DOT_f64, MCK_HPR, MCK_DPR }, },
12322 { 2214 /* vcvtp */, ARM::VCVTPSH, Convert__Reg1_2__Reg1_3, AMFBS_HasFullFP16, { MCK__DOT_s32, MCK__DOT_f16, MCK_HPR, MCK_HPR }, },
12322 { 2214 /* vcvtp */, ARM::VCVTPSH, Convert__Reg1_2__Reg1_3, AMFBS_HasFullFP16, { MCK__DOT_s32, MCK__DOT_f16, MCK_HPR, MCK_HPR }, },
12327 { 2214 /* vcvtp */, ARM::VCVTPUS, Convert__Reg1_2__Reg1_3, AMFBS_HasFPARMv8, { MCK__DOT_u32, MCK__DOT_f32, MCK_HPR, MCK_HPR }, },
12327 { 2214 /* vcvtp */, ARM::VCVTPUS, Convert__Reg1_2__Reg1_3, AMFBS_HasFPARMv8, { MCK__DOT_u32, MCK__DOT_f32, MCK_HPR, MCK_HPR }, },
12328 { 2214 /* vcvtp */, ARM::VCVTPUD, Convert__Reg1_2__Reg1_3, AMFBS_HasFPARMv8_HasDPVFP, { MCK__DOT_u32, MCK__DOT_f64, MCK_HPR, MCK_DPR }, },
12329 { 2214 /* vcvtp */, ARM::VCVTPUH, Convert__Reg1_2__Reg1_3, AMFBS_HasFullFP16, { MCK__DOT_u32, MCK__DOT_f16, MCK_HPR, MCK_HPR }, },
12329 { 2214 /* vcvtp */, ARM::VCVTPUH, Convert__Reg1_2__Reg1_3, AMFBS_HasFullFP16, { MCK__DOT_u32, MCK__DOT_f16, MCK_HPR, MCK_HPR }, },
12334 { 2220 /* vcvtr */, ARM::VTOSIRS, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK__DOT_s32, MCK__DOT_f32, MCK_HPR, MCK_HPR }, },
12334 { 2220 /* vcvtr */, ARM::VTOSIRS, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK__DOT_s32, MCK__DOT_f32, MCK_HPR, MCK_HPR }, },
12335 { 2220 /* vcvtr */, ARM::VTOSIRD, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasVFP2_HasDPVFP, { MCK_CondCode, MCK__DOT_s32, MCK__DOT_f64, MCK_HPR, MCK_DPR }, },
12336 { 2220 /* vcvtr */, ARM::VTOSIRH, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_s32, MCK__DOT_f16, MCK_HPR, MCK_HPR }, },
12336 { 2220 /* vcvtr */, ARM::VTOSIRH, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_s32, MCK__DOT_f16, MCK_HPR, MCK_HPR }, },
12337 { 2220 /* vcvtr */, ARM::VTOUIRS, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK__DOT_u32, MCK__DOT_f32, MCK_HPR, MCK_HPR }, },
12337 { 2220 /* vcvtr */, ARM::VTOUIRS, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK__DOT_u32, MCK__DOT_f32, MCK_HPR, MCK_HPR }, },
12338 { 2220 /* vcvtr */, ARM::VTOUIRD, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasVFP2_HasDPVFP, { MCK_CondCode, MCK__DOT_u32, MCK__DOT_f64, MCK_HPR, MCK_DPR }, },
12339 { 2220 /* vcvtr */, ARM::VTOUIRH, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_u32, MCK__DOT_f16, MCK_HPR, MCK_HPR }, },
12339 { 2220 /* vcvtr */, ARM::VTOUIRH, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_u32, MCK__DOT_f16, MCK_HPR, MCK_HPR }, },
12340 { 2226 /* vcvtt */, ARM::VCVTTHS, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasFP16, { MCK_CondCode, MCK__DOT_f32, MCK__DOT_f16, MCK_HPR, MCK_HPR }, },
12340 { 2226 /* vcvtt */, ARM::VCVTTHS, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasFP16, { MCK_CondCode, MCK__DOT_f32, MCK__DOT_f16, MCK_HPR, MCK_HPR }, },
12341 { 2226 /* vcvtt */, ARM::VCVTTHD, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasFPARMv8_HasDPVFP, { MCK_CondCode, MCK__DOT_f64, MCK__DOT_f16, MCK_DPR, MCK_HPR }, },
12342 { 2226 /* vcvtt */, ARM::VCVTTSH, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasFP16, { MCK_CondCode, MCK__DOT_f16, MCK__DOT_f32, MCK_HPR, MCK_HPR }, },
12342 { 2226 /* vcvtt */, ARM::VCVTTSH, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasFP16, { MCK_CondCode, MCK__DOT_f16, MCK__DOT_f32, MCK_HPR, MCK_HPR }, },
12343 { 2226 /* vcvtt */, ARM::VCVTTDH, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasFPARMv8_HasDPVFP, { MCK_CondCode, MCK__DOT_f16, MCK__DOT_f64, MCK_HPR, MCK_DPR }, },
12349 { 2238 /* vdiv */, ARM::VDIVS, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK__DOT_f32, MCK_HPR, MCK_HPR }, },
12349 { 2238 /* vdiv */, ARM::VDIVS, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK__DOT_f32, MCK_HPR, MCK_HPR }, },
12351 { 2238 /* vdiv */, ARM::VDIVH, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_HPR, MCK_HPR }, },
12351 { 2238 /* vdiv */, ARM::VDIVH, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_HPR, MCK_HPR }, },
12352 { 2238 /* vdiv */, ARM::VDIVS, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK__DOT_f32, MCK_HPR, MCK_HPR, MCK_HPR }, },
12352 { 2238 /* vdiv */, ARM::VDIVS, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK__DOT_f32, MCK_HPR, MCK_HPR, MCK_HPR }, },
12352 { 2238 /* vdiv */, ARM::VDIVS, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK__DOT_f32, MCK_HPR, MCK_HPR, MCK_HPR }, },
12354 { 2238 /* vdiv */, ARM::VDIVH, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_HPR, MCK_HPR, MCK_HPR }, },
12354 { 2238 /* vdiv */, ARM::VDIVH, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_HPR, MCK_HPR, MCK_HPR }, },
12354 { 2238 /* vdiv */, ARM::VDIVH, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_HPR, MCK_HPR, MCK_HPR }, },
12421 { 2265 /* vfma */, ARM::VFMAS, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasVFP4, { MCK_CondCode, MCK__DOT_f32, MCK_HPR, MCK_HPR, MCK_HPR }, },
12421 { 2265 /* vfma */, ARM::VFMAS, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasVFP4, { MCK_CondCode, MCK__DOT_f32, MCK_HPR, MCK_HPR, MCK_HPR }, },
12421 { 2265 /* vfma */, ARM::VFMAS, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasVFP4, { MCK_CondCode, MCK__DOT_f32, MCK_HPR, MCK_HPR, MCK_HPR }, },
12425 { 2265 /* vfma */, ARM::VFMAH, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_HPR, MCK_HPR, MCK_HPR }, },
12425 { 2265 /* vfma */, ARM::VFMAH, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_HPR, MCK_HPR, MCK_HPR }, },
12425 { 2265 /* vfma */, ARM::VFMAH, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_HPR, MCK_HPR, MCK_HPR }, },
12431 { 2270 /* vfmal */, ARM::VFMALD, Convert__Reg1_1__Reg1_2__Reg1_3, AMFBS_HasNEON_HasFP16FML, { MCK__DOT_f16, MCK_DPR, MCK_HPR, MCK_HPR }, },
12431 { 2270 /* vfmal */, ARM::VFMALD, Convert__Reg1_1__Reg1_2__Reg1_3, AMFBS_HasNEON_HasFP16FML, { MCK__DOT_f16, MCK_DPR, MCK_HPR, MCK_HPR }, },
12433 { 2270 /* vfmal */, ARM::VFMALDI, Convert__Reg1_1__Reg1_2__Reg1_3__VectorIndex321_4, AMFBS_HasNEON_HasFP16FML, { MCK__DOT_f16, MCK_DPR, MCK_HPR, MCK_SPR_8, MCK_VectorIndex32 }, },
12438 { 2282 /* vfms */, ARM::VFMSS, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasVFP4, { MCK_CondCode, MCK__DOT_f32, MCK_HPR, MCK_HPR, MCK_HPR }, },
12438 { 2282 /* vfms */, ARM::VFMSS, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasVFP4, { MCK_CondCode, MCK__DOT_f32, MCK_HPR, MCK_HPR, MCK_HPR }, },
12438 { 2282 /* vfms */, ARM::VFMSS, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasVFP4, { MCK_CondCode, MCK__DOT_f32, MCK_HPR, MCK_HPR, MCK_HPR }, },
12442 { 2282 /* vfms */, ARM::VFMSH, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_HPR, MCK_HPR, MCK_HPR }, },
12442 { 2282 /* vfms */, ARM::VFMSH, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_HPR, MCK_HPR, MCK_HPR }, },
12442 { 2282 /* vfms */, ARM::VFMSH, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_HPR, MCK_HPR, MCK_HPR }, },
12446 { 2287 /* vfmsl */, ARM::VFMSLD, Convert__Reg1_1__Reg1_2__Reg1_3, AMFBS_HasNEON_HasFP16FML, { MCK__DOT_f16, MCK_DPR, MCK_HPR, MCK_HPR }, },
12446 { 2287 /* vfmsl */, ARM::VFMSLD, Convert__Reg1_1__Reg1_2__Reg1_3, AMFBS_HasNEON_HasFP16FML, { MCK__DOT_f16, MCK_DPR, MCK_HPR, MCK_HPR }, },
12448 { 2287 /* vfmsl */, ARM::VFMSLDI, Convert__Reg1_1__Reg1_2__Reg1_3__VectorIndex321_4, AMFBS_HasNEON_HasFP16FML, { MCK__DOT_f16, MCK_DPR, MCK_HPR, MCK_SPR_8, MCK_VectorIndex32 }, },
12449 { 2293 /* vfnma */, ARM::VFNMAS, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasVFP4, { MCK_CondCode, MCK__DOT_f32, MCK_HPR, MCK_HPR, MCK_HPR }, },
12449 { 2293 /* vfnma */, ARM::VFNMAS, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasVFP4, { MCK_CondCode, MCK__DOT_f32, MCK_HPR, MCK_HPR, MCK_HPR }, },
12449 { 2293 /* vfnma */, ARM::VFNMAS, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasVFP4, { MCK_CondCode, MCK__DOT_f32, MCK_HPR, MCK_HPR, MCK_HPR }, },
12451 { 2293 /* vfnma */, ARM::VFNMAH, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_HPR, MCK_HPR, MCK_HPR }, },
12451 { 2293 /* vfnma */, ARM::VFNMAH, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_HPR, MCK_HPR, MCK_HPR }, },
12451 { 2293 /* vfnma */, ARM::VFNMAH, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_HPR, MCK_HPR, MCK_HPR }, },
12452 { 2299 /* vfnms */, ARM::VFNMSS, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasVFP4, { MCK_CondCode, MCK__DOT_f32, MCK_HPR, MCK_HPR, MCK_HPR }, },
12452 { 2299 /* vfnms */, ARM::VFNMSS, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasVFP4, { MCK_CondCode, MCK__DOT_f32, MCK_HPR, MCK_HPR, MCK_HPR }, },
12452 { 2299 /* vfnms */, ARM::VFNMSS, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasVFP4, { MCK_CondCode, MCK__DOT_f32, MCK_HPR, MCK_HPR, MCK_HPR }, },
12454 { 2299 /* vfnms */, ARM::VFNMSH, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_HPR, MCK_HPR, MCK_HPR }, },
12454 { 2299 /* vfnms */, ARM::VFNMSH, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_HPR, MCK_HPR, MCK_HPR }, },
12454 { 2299 /* vfnms */, ARM::VFNMSH, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_HPR, MCK_HPR, MCK_HPR }, },
12533 { 2330 /* vins */, ARM::VINSH, Convert__Reg1_1__Reg1_2, AMFBS_HasFullFP16, { MCK__DOT_f16, MCK_HPR, MCK_HPR }, },
12533 { 2330 /* vins */, ARM::VINSH, Convert__Reg1_1__Reg1_2, AMFBS_HasFullFP16, { MCK__DOT_f16, MCK_HPR, MCK_HPR }, },
12537 { 2342 /* vjcvt */, ARM::VJCVT, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasFPARMv8_HasV8_3a, { MCK_CondCode, MCK__DOT_s32, MCK__DOT_f64, MCK_HPR, MCK_DPR }, },
12878 { 2418 /* vldr */, ARM::VLDRS, Convert__Reg1_1__AddrMode52_2__CondCode2_0, AMFBS_HasFPRegs, { MCK_CondCode, MCK_HPR, MCK_AddrMode5 }, },
12879 { 2418 /* vldr */, ARM::VLDRH, Convert__Reg1_2__AddrMode5FP162_3__CondCode2_0, AMFBS_HasFPRegs16, { MCK_CondCode, MCK__DOT_16, MCK_HPR, MCK_AddrMode5FP16 }, },
12880 { 2418 /* vldr */, ARM::VLDRS, Convert__Reg1_2__AddrMode52_3__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK__DOT_32, MCK_HPR, MCK_AddrMode5 }, },
12988 { 2477 /* vmaxnm */, ARM::VFP_VMAXNMS, Convert__Reg1_1__Reg1_2__Reg1_3, AMFBS_HasFPARMv8, { MCK__DOT_f32, MCK_HPR, MCK_HPR, MCK_HPR }, },
12988 { 2477 /* vmaxnm */, ARM::VFP_VMAXNMS, Convert__Reg1_1__Reg1_2__Reg1_3, AMFBS_HasFPARMv8, { MCK__DOT_f32, MCK_HPR, MCK_HPR, MCK_HPR }, },
12988 { 2477 /* vmaxnm */, ARM::VFP_VMAXNMS, Convert__Reg1_1__Reg1_2__Reg1_3, AMFBS_HasFPARMv8, { MCK__DOT_f32, MCK_HPR, MCK_HPR, MCK_HPR }, },
12992 { 2477 /* vmaxnm */, ARM::VFP_VMAXNMH, Convert__Reg1_1__Reg1_2__Reg1_3, AMFBS_HasFullFP16, { MCK__DOT_f16, MCK_HPR, MCK_HPR, MCK_HPR }, },
12992 { 2477 /* vmaxnm */, ARM::VFP_VMAXNMH, Convert__Reg1_1__Reg1_2__Reg1_3, AMFBS_HasFullFP16, { MCK__DOT_f16, MCK_HPR, MCK_HPR, MCK_HPR }, },
12992 { 2477 /* vmaxnm */, ARM::VFP_VMAXNMH, Convert__Reg1_1__Reg1_2__Reg1_3, AMFBS_HasFullFP16, { MCK__DOT_f16, MCK_HPR, MCK_HPR, MCK_HPR }, },
13053 { 2533 /* vminnm */, ARM::VFP_VMINNMS, Convert__Reg1_1__Reg1_2__Reg1_3, AMFBS_HasFPARMv8, { MCK__DOT_f32, MCK_HPR, MCK_HPR, MCK_HPR }, },
13053 { 2533 /* vminnm */, ARM::VFP_VMINNMS, Convert__Reg1_1__Reg1_2__Reg1_3, AMFBS_HasFPARMv8, { MCK__DOT_f32, MCK_HPR, MCK_HPR, MCK_HPR }, },
13053 { 2533 /* vminnm */, ARM::VFP_VMINNMS, Convert__Reg1_1__Reg1_2__Reg1_3, AMFBS_HasFPARMv8, { MCK__DOT_f32, MCK_HPR, MCK_HPR, MCK_HPR }, },
13057 { 2533 /* vminnm */, ARM::VFP_VMINNMH, Convert__Reg1_1__Reg1_2__Reg1_3, AMFBS_HasFullFP16, { MCK__DOT_f16, MCK_HPR, MCK_HPR, MCK_HPR }, },
13057 { 2533 /* vminnm */, ARM::VFP_VMINNMH, Convert__Reg1_1__Reg1_2__Reg1_3, AMFBS_HasFullFP16, { MCK__DOT_f16, MCK_HPR, MCK_HPR, MCK_HPR }, },
13057 { 2533 /* vminnm */, ARM::VFP_VMINNMH, Convert__Reg1_1__Reg1_2__Reg1_3, AMFBS_HasFullFP16, { MCK__DOT_f16, MCK_HPR, MCK_HPR, MCK_HPR }, },
13074 { 2571 /* vmla */, ARM::VMLAS, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK__DOT_f32, MCK_HPR, MCK_HPR, MCK_HPR }, },
13074 { 2571 /* vmla */, ARM::VMLAS, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK__DOT_f32, MCK_HPR, MCK_HPR, MCK_HPR }, },
13074 { 2571 /* vmla */, ARM::VMLAS, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK__DOT_f32, MCK_HPR, MCK_HPR, MCK_HPR }, },
13084 { 2571 /* vmla */, ARM::VMLAH, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_HPR, MCK_HPR, MCK_HPR }, },
13084 { 2571 /* vmla */, ARM::VMLAH, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_HPR, MCK_HPR, MCK_HPR }, },
13084 { 2571 /* vmla */, ARM::VMLAH, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_HPR, MCK_HPR, MCK_HPR }, },
13167 { 2692 /* vmls */, ARM::VMLSS, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK__DOT_f32, MCK_HPR, MCK_HPR, MCK_HPR }, },
13167 { 2692 /* vmls */, ARM::VMLSS, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK__DOT_f32, MCK_HPR, MCK_HPR, MCK_HPR }, },
13167 { 2692 /* vmls */, ARM::VMLSS, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK__DOT_f32, MCK_HPR, MCK_HPR, MCK_HPR }, },
13177 { 2692 /* vmls */, ARM::VMLSH, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_HPR, MCK_HPR, MCK_HPR }, },
13177 { 2692 /* vmls */, ARM::VMLSH, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_HPR, MCK_HPR, MCK_HPR }, },
13177 { 2692 /* vmls */, ARM::VMLSH, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_HPR, MCK_HPR, MCK_HPR }, },
13216 { 2779 /* vmov */, ARM::VMOVRS, Convert__Reg1_1__Reg1_2__CondCode2_0, AMFBS_HasFPRegs, { MCK_CondCode, MCK_GPR, MCK_HPR }, },
13219 { 2779 /* vmov */, ARM::VMOVSR, Convert__Reg1_1__Reg1_2__CondCode2_0, AMFBS_HasFPRegs, { MCK_CondCode, MCK_HPR, MCK_GPR }, },
13220 { 2779 /* vmov */, ARM::VMOVS, Convert__Reg1_1__Reg1_2__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK_HPR, MCK_HPR }, },
13220 { 2779 /* vmov */, ARM::VMOVS, Convert__Reg1_1__Reg1_2__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK_HPR, MCK_HPR }, },
13226 { 2779 /* vmov */, ARM::VMOVS, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasFPRegs, { MCK_CondCode, MCK__DOT_f32, MCK_HPR, MCK_HPR }, },
13226 { 2779 /* vmov */, ARM::VMOVS, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasFPRegs, { MCK_CondCode, MCK__DOT_f32, MCK_HPR, MCK_HPR }, },
13227 { 2779 /* vmov */, ARM::FCONSTS, Convert__Reg1_2__FPImm1_3__CondCode2_0, AMFBS_HasVFP3, { MCK_CondCode, MCK__DOT_f32, MCK_HPR, MCK_FPImm }, },
13252 { 2779 /* vmov */, ARM::VMOVRS, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK__DOT_16, MCK_GPR, MCK_HPR }, },
13255 { 2779 /* vmov */, ARM::VMOVSR, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK__DOT_16, MCK_HPR, MCK_GPR }, },
13256 { 2779 /* vmov */, ARM::VMOVRS, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK__DOT_32, MCK_GPR, MCK_HPR }, },
13259 { 2779 /* vmov */, ARM::VMOVSR, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK__DOT_32, MCK_HPR, MCK_GPR }, },
13262 { 2779 /* vmov */, ARM::VMOVRS, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK__DOT_8, MCK_GPR, MCK_HPR }, },
13265 { 2779 /* vmov */, ARM::VMOVSR, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK__DOT_8, MCK_HPR, MCK_GPR }, },
13266 { 2779 /* vmov */, ARM::VMOVRH, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasFPRegs16, { MCK_CondCode, MCK__DOT_f16, MCK_rGPR, MCK_HPR }, },
13267 { 2779 /* vmov */, ARM::VMOVHR, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasFPRegs16, { MCK_CondCode, MCK__DOT_f16, MCK_HPR, MCK_rGPR }, },
13268 { 2779 /* vmov */, ARM::FCONSTH, Convert__Reg1_2__FPImm1_3__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_HPR, MCK_FPImm }, },
13294 { 2779 /* vmov */, ARM::VMOVRRS, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasFPRegs, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_HPR, MCK_HPR }, },
13294 { 2779 /* vmov */, ARM::VMOVRRS, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasFPRegs, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_HPR, MCK_HPR }, },
13295 { 2779 /* vmov */, ARM::VMOVSRR, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasFPRegs, { MCK_CondCode, MCK_HPR, MCK_HPR, MCK_GPR, MCK_GPR }, },
13295 { 2779 /* vmov */, ARM::VMOVSRR, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasFPRegs, { MCK_CondCode, MCK_HPR, MCK_HPR, MCK_GPR, MCK_GPR }, },
13319 { 2824 /* vmovx */, ARM::VMOVH, Convert__Reg1_1__Reg1_2, AMFBS_HasFullFP16, { MCK__DOT_f16, MCK_HPR, MCK_HPR }, },
13319 { 2824 /* vmovx */, ARM::VMOVH, Convert__Reg1_1__Reg1_2, AMFBS_HasFullFP16, { MCK__DOT_f16, MCK_HPR, MCK_HPR }, },
13346 { 2840 /* vmul */, ARM::VMULS, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK__DOT_f32, MCK_HPR, MCK_HPR }, },
13346 { 2840 /* vmul */, ARM::VMULS, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK__DOT_f32, MCK_HPR, MCK_HPR }, },
13358 { 2840 /* vmul */, ARM::VMULH, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_HPR, MCK_HPR }, },
13358 { 2840 /* vmul */, ARM::VMULH, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_HPR, MCK_HPR }, },
13363 { 2840 /* vmul */, ARM::VMULS, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK__DOT_f32, MCK_HPR, MCK_HPR, MCK_HPR }, },
13363 { 2840 /* vmul */, ARM::VMULS, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK__DOT_f32, MCK_HPR, MCK_HPR, MCK_HPR }, },
13363 { 2840 /* vmul */, ARM::VMULS, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK__DOT_f32, MCK_HPR, MCK_HPR, MCK_HPR }, },
13381 { 2840 /* vmul */, ARM::VMULH, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_HPR, MCK_HPR, MCK_HPR }, },
13381 { 2840 /* vmul */, ARM::VMULH, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_HPR, MCK_HPR, MCK_HPR }, },
13381 { 2840 /* vmul */, ARM::VMULH, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_HPR, MCK_HPR, MCK_HPR }, },
13473 { 2876 /* vneg */, ARM::VNEGS, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK__DOT_f32, MCK_HPR, MCK_HPR }, },
13473 { 2876 /* vneg */, ARM::VNEGS, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK__DOT_f32, MCK_HPR, MCK_HPR }, },
13477 { 2876 /* vneg */, ARM::VNEGH, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_HPR, MCK_HPR }, },
13477 { 2876 /* vneg */, ARM::VNEGH, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_HPR, MCK_HPR }, },
13483 { 2881 /* vnmla */, ARM::VNMLAS, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK__DOT_f32, MCK_HPR, MCK_HPR, MCK_HPR }, },
13483 { 2881 /* vnmla */, ARM::VNMLAS, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK__DOT_f32, MCK_HPR, MCK_HPR, MCK_HPR }, },
13483 { 2881 /* vnmla */, ARM::VNMLAS, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK__DOT_f32, MCK_HPR, MCK_HPR, MCK_HPR }, },
13485 { 2881 /* vnmla */, ARM::VNMLAH, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_HPR, MCK_HPR, MCK_HPR }, },
13485 { 2881 /* vnmla */, ARM::VNMLAH, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_HPR, MCK_HPR, MCK_HPR }, },
13485 { 2881 /* vnmla */, ARM::VNMLAH, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_HPR, MCK_HPR, MCK_HPR }, },
13486 { 2887 /* vnmls */, ARM::VNMLSS, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK__DOT_f32, MCK_HPR, MCK_HPR, MCK_HPR }, },
13486 { 2887 /* vnmls */, ARM::VNMLSS, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK__DOT_f32, MCK_HPR, MCK_HPR, MCK_HPR }, },
13486 { 2887 /* vnmls */, ARM::VNMLSS, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK__DOT_f32, MCK_HPR, MCK_HPR, MCK_HPR }, },
13488 { 2887 /* vnmls */, ARM::VNMLSH, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_HPR, MCK_HPR, MCK_HPR }, },
13488 { 2887 /* vnmls */, ARM::VNMLSH, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_HPR, MCK_HPR, MCK_HPR }, },
13488 { 2887 /* vnmls */, ARM::VNMLSH, Convert__Reg1_2__Tie0_1_1__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_HPR, MCK_HPR, MCK_HPR }, },
13489 { 2893 /* vnmul */, ARM::VNMULS, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK__DOT_f32, MCK_HPR, MCK_HPR, MCK_HPR }, },
13489 { 2893 /* vnmul */, ARM::VNMULS, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK__DOT_f32, MCK_HPR, MCK_HPR, MCK_HPR }, },
13489 { 2893 /* vnmul */, ARM::VNMULS, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK__DOT_f32, MCK_HPR, MCK_HPR, MCK_HPR }, },
13491 { 2893 /* vnmul */, ARM::VNMULH, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_HPR, MCK_HPR, MCK_HPR }, },
13491 { 2893 /* vnmul */, ARM::VNMULH, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_HPR, MCK_HPR, MCK_HPR }, },
13491 { 2893 /* vnmul */, ARM::VNMULH, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_HPR, MCK_HPR, MCK_HPR }, },
14165 { 3404 /* vrinta */, ARM::VRINTAS, Convert__Reg1_1__Reg1_2, AMFBS_HasFPARMv8, { MCK__DOT_f32, MCK_HPR, MCK_HPR }, },
14165 { 3404 /* vrinta */, ARM::VRINTAS, Convert__Reg1_1__Reg1_2, AMFBS_HasFPARMv8, { MCK__DOT_f32, MCK_HPR, MCK_HPR }, },
14169 { 3404 /* vrinta */, ARM::VRINTAH, Convert__Reg1_1__Reg1_2, AMFBS_HasFullFP16, { MCK__DOT_f16, MCK_HPR, MCK_HPR }, },
14169 { 3404 /* vrinta */, ARM::VRINTAH, Convert__Reg1_1__Reg1_2, AMFBS_HasFullFP16, { MCK__DOT_f16, MCK_HPR, MCK_HPR }, },
14172 { 3404 /* vrinta */, ARM::VRINTAS, Convert__Reg1_2__Reg1_3, AMFBS_HasFPARMv8, { MCK__DOT_f32, MCK__DOT_f32, MCK_HPR, MCK_HPR }, },
14172 { 3404 /* vrinta */, ARM::VRINTAS, Convert__Reg1_2__Reg1_3, AMFBS_HasFPARMv8, { MCK__DOT_f32, MCK__DOT_f32, MCK_HPR, MCK_HPR }, },
14180 { 3411 /* vrintm */, ARM::VRINTMS, Convert__Reg1_1__Reg1_2, AMFBS_HasFPARMv8, { MCK__DOT_f32, MCK_HPR, MCK_HPR }, },
14180 { 3411 /* vrintm */, ARM::VRINTMS, Convert__Reg1_1__Reg1_2, AMFBS_HasFPARMv8, { MCK__DOT_f32, MCK_HPR, MCK_HPR }, },
14184 { 3411 /* vrintm */, ARM::VRINTMH, Convert__Reg1_1__Reg1_2, AMFBS_HasFullFP16, { MCK__DOT_f16, MCK_HPR, MCK_HPR }, },
14184 { 3411 /* vrintm */, ARM::VRINTMH, Convert__Reg1_1__Reg1_2, AMFBS_HasFullFP16, { MCK__DOT_f16, MCK_HPR, MCK_HPR }, },
14187 { 3411 /* vrintm */, ARM::VRINTMS, Convert__Reg1_2__Reg1_3, AMFBS_HasFPARMv8, { MCK__DOT_f32, MCK__DOT_f32, MCK_HPR, MCK_HPR }, },
14187 { 3411 /* vrintm */, ARM::VRINTMS, Convert__Reg1_2__Reg1_3, AMFBS_HasFPARMv8, { MCK__DOT_f32, MCK__DOT_f32, MCK_HPR, MCK_HPR }, },
14195 { 3418 /* vrintn */, ARM::VRINTNS, Convert__Reg1_1__Reg1_2, AMFBS_HasFPARMv8, { MCK__DOT_f32, MCK_HPR, MCK_HPR }, },
14195 { 3418 /* vrintn */, ARM::VRINTNS, Convert__Reg1_1__Reg1_2, AMFBS_HasFPARMv8, { MCK__DOT_f32, MCK_HPR, MCK_HPR }, },
14199 { 3418 /* vrintn */, ARM::VRINTNH, Convert__Reg1_1__Reg1_2, AMFBS_HasFullFP16, { MCK__DOT_f16, MCK_HPR, MCK_HPR }, },
14199 { 3418 /* vrintn */, ARM::VRINTNH, Convert__Reg1_1__Reg1_2, AMFBS_HasFullFP16, { MCK__DOT_f16, MCK_HPR, MCK_HPR }, },
14202 { 3418 /* vrintn */, ARM::VRINTNS, Convert__Reg1_2__Reg1_3, AMFBS_HasFPARMv8, { MCK__DOT_f32, MCK__DOT_f32, MCK_HPR, MCK_HPR }, },
14202 { 3418 /* vrintn */, ARM::VRINTNS, Convert__Reg1_2__Reg1_3, AMFBS_HasFPARMv8, { MCK__DOT_f32, MCK__DOT_f32, MCK_HPR, MCK_HPR }, },
14210 { 3425 /* vrintp */, ARM::VRINTPS, Convert__Reg1_1__Reg1_2, AMFBS_HasFPARMv8, { MCK__DOT_f32, MCK_HPR, MCK_HPR }, },
14210 { 3425 /* vrintp */, ARM::VRINTPS, Convert__Reg1_1__Reg1_2, AMFBS_HasFPARMv8, { MCK__DOT_f32, MCK_HPR, MCK_HPR }, },
14214 { 3425 /* vrintp */, ARM::VRINTPH, Convert__Reg1_1__Reg1_2, AMFBS_HasFullFP16, { MCK__DOT_f16, MCK_HPR, MCK_HPR }, },
14214 { 3425 /* vrintp */, ARM::VRINTPH, Convert__Reg1_1__Reg1_2, AMFBS_HasFullFP16, { MCK__DOT_f16, MCK_HPR, MCK_HPR }, },
14217 { 3425 /* vrintp */, ARM::VRINTPS, Convert__Reg1_2__Reg1_3, AMFBS_HasFPARMv8, { MCK__DOT_f32, MCK__DOT_f32, MCK_HPR, MCK_HPR }, },
14217 { 3425 /* vrintp */, ARM::VRINTPS, Convert__Reg1_2__Reg1_3, AMFBS_HasFPARMv8, { MCK__DOT_f32, MCK__DOT_f32, MCK_HPR, MCK_HPR }, },
14223 { 3432 /* vrintr */, ARM::VRINTRS, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasFPARMv8, { MCK_CondCode, MCK__DOT_f32, MCK_HPR, MCK_HPR }, },
14223 { 3432 /* vrintr */, ARM::VRINTRS, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasFPARMv8, { MCK_CondCode, MCK__DOT_f32, MCK_HPR, MCK_HPR }, },
14225 { 3432 /* vrintr */, ARM::VRINTRH, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_HPR, MCK_HPR }, },
14225 { 3432 /* vrintr */, ARM::VRINTRH, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_HPR, MCK_HPR }, },
14226 { 3432 /* vrintr */, ARM::VRINTRS, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasFPARMv8, { MCK_CondCode, MCK__DOT_f32, MCK__DOT_f32, MCK_HPR, MCK_HPR }, },
14226 { 3432 /* vrintr */, ARM::VRINTRS, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasFPARMv8, { MCK_CondCode, MCK__DOT_f32, MCK__DOT_f32, MCK_HPR, MCK_HPR }, },
14228 { 3432 /* vrintr */, ARM::VRINTRH, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK__DOT_f16, MCK_HPR, MCK_HPR }, },
14228 { 3432 /* vrintr */, ARM::VRINTRH, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK__DOT_f16, MCK_HPR, MCK_HPR }, },
14237 { 3439 /* vrintx */, ARM::VRINTXS, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasFPARMv8, { MCK_CondCode, MCK__DOT_f32, MCK_HPR, MCK_HPR }, },
14237 { 3439 /* vrintx */, ARM::VRINTXS, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasFPARMv8, { MCK_CondCode, MCK__DOT_f32, MCK_HPR, MCK_HPR }, },
14239 { 3439 /* vrintx */, ARM::VRINTXH, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_HPR, MCK_HPR }, },
14239 { 3439 /* vrintx */, ARM::VRINTXH, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_HPR, MCK_HPR }, },
14242 { 3439 /* vrintx */, ARM::VRINTXS, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasFPARMv8, { MCK_CondCode, MCK__DOT_f32, MCK__DOT_f32, MCK_HPR, MCK_HPR }, },
14242 { 3439 /* vrintx */, ARM::VRINTXS, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasFPARMv8, { MCK_CondCode, MCK__DOT_f32, MCK__DOT_f32, MCK_HPR, MCK_HPR }, },
14244 { 3439 /* vrintx */, ARM::VRINTXH, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK__DOT_f16, MCK_HPR, MCK_HPR }, },
14244 { 3439 /* vrintx */, ARM::VRINTXH, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK__DOT_f16, MCK_HPR, MCK_HPR }, },
14253 { 3446 /* vrintz */, ARM::VRINTZS, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasFPARMv8, { MCK_CondCode, MCK__DOT_f32, MCK_HPR, MCK_HPR }, },
14253 { 3446 /* vrintz */, ARM::VRINTZS, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasFPARMv8, { MCK_CondCode, MCK__DOT_f32, MCK_HPR, MCK_HPR }, },
14255 { 3446 /* vrintz */, ARM::VRINTZH, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_HPR, MCK_HPR }, },
14255 { 3446 /* vrintz */, ARM::VRINTZH, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_HPR, MCK_HPR }, },
14258 { 3446 /* vrintz */, ARM::VRINTZS, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasFPARMv8, { MCK_CondCode, MCK__DOT_f32, MCK__DOT_f32, MCK_HPR, MCK_HPR }, },
14258 { 3446 /* vrintz */, ARM::VRINTZS, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasFPARMv8, { MCK_CondCode, MCK__DOT_f32, MCK__DOT_f32, MCK_HPR, MCK_HPR }, },
14260 { 3446 /* vrintz */, ARM::VRINTZH, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK__DOT_f16, MCK_HPR, MCK_HPR }, },
14260 { 3446 /* vrintz */, ARM::VRINTZH, Convert__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK__DOT_f16, MCK_HPR, MCK_HPR }, },
14427 { 3665 /* vseleq */, ARM::VSELEQS, Convert__Reg1_1__Reg1_2__Reg1_3, AMFBS_HasFPARMv8, { MCK__DOT_f32, MCK_HPR, MCK_HPR, MCK_HPR }, },
14427 { 3665 /* vseleq */, ARM::VSELEQS, Convert__Reg1_1__Reg1_2__Reg1_3, AMFBS_HasFPARMv8, { MCK__DOT_f32, MCK_HPR, MCK_HPR, MCK_HPR }, },
14427 { 3665 /* vseleq */, ARM::VSELEQS, Convert__Reg1_1__Reg1_2__Reg1_3, AMFBS_HasFPARMv8, { MCK__DOT_f32, MCK_HPR, MCK_HPR, MCK_HPR }, },
14429 { 3665 /* vseleq */, ARM::VSELEQH, Convert__Reg1_1__Reg1_2__Reg1_3, AMFBS_HasFullFP16, { MCK__DOT_f16, MCK_HPR, MCK_HPR, MCK_HPR }, },
14429 { 3665 /* vseleq */, ARM::VSELEQH, Convert__Reg1_1__Reg1_2__Reg1_3, AMFBS_HasFullFP16, { MCK__DOT_f16, MCK_HPR, MCK_HPR, MCK_HPR }, },
14429 { 3665 /* vseleq */, ARM::VSELEQH, Convert__Reg1_1__Reg1_2__Reg1_3, AMFBS_HasFullFP16, { MCK__DOT_f16, MCK_HPR, MCK_HPR, MCK_HPR }, },
14430 { 3672 /* vselge */, ARM::VSELGES, Convert__Reg1_1__Reg1_2__Reg1_3, AMFBS_HasFPARMv8, { MCK__DOT_f32, MCK_HPR, MCK_HPR, MCK_HPR }, },
14430 { 3672 /* vselge */, ARM::VSELGES, Convert__Reg1_1__Reg1_2__Reg1_3, AMFBS_HasFPARMv8, { MCK__DOT_f32, MCK_HPR, MCK_HPR, MCK_HPR }, },
14430 { 3672 /* vselge */, ARM::VSELGES, Convert__Reg1_1__Reg1_2__Reg1_3, AMFBS_HasFPARMv8, { MCK__DOT_f32, MCK_HPR, MCK_HPR, MCK_HPR }, },
14432 { 3672 /* vselge */, ARM::VSELGEH, Convert__Reg1_1__Reg1_2__Reg1_3, AMFBS_HasFullFP16, { MCK__DOT_f16, MCK_HPR, MCK_HPR, MCK_HPR }, },
14432 { 3672 /* vselge */, ARM::VSELGEH, Convert__Reg1_1__Reg1_2__Reg1_3, AMFBS_HasFullFP16, { MCK__DOT_f16, MCK_HPR, MCK_HPR, MCK_HPR }, },
14432 { 3672 /* vselge */, ARM::VSELGEH, Convert__Reg1_1__Reg1_2__Reg1_3, AMFBS_HasFullFP16, { MCK__DOT_f16, MCK_HPR, MCK_HPR, MCK_HPR }, },
14433 { 3679 /* vselgt */, ARM::VSELGTS, Convert__Reg1_1__Reg1_2__Reg1_3, AMFBS_HasFPARMv8, { MCK__DOT_f32, MCK_HPR, MCK_HPR, MCK_HPR }, },
14433 { 3679 /* vselgt */, ARM::VSELGTS, Convert__Reg1_1__Reg1_2__Reg1_3, AMFBS_HasFPARMv8, { MCK__DOT_f32, MCK_HPR, MCK_HPR, MCK_HPR }, },
14433 { 3679 /* vselgt */, ARM::VSELGTS, Convert__Reg1_1__Reg1_2__Reg1_3, AMFBS_HasFPARMv8, { MCK__DOT_f32, MCK_HPR, MCK_HPR, MCK_HPR }, },
14435 { 3679 /* vselgt */, ARM::VSELGTH, Convert__Reg1_1__Reg1_2__Reg1_3, AMFBS_HasFullFP16, { MCK__DOT_f16, MCK_HPR, MCK_HPR, MCK_HPR }, },
14435 { 3679 /* vselgt */, ARM::VSELGTH, Convert__Reg1_1__Reg1_2__Reg1_3, AMFBS_HasFullFP16, { MCK__DOT_f16, MCK_HPR, MCK_HPR, MCK_HPR }, },
14435 { 3679 /* vselgt */, ARM::VSELGTH, Convert__Reg1_1__Reg1_2__Reg1_3, AMFBS_HasFullFP16, { MCK__DOT_f16, MCK_HPR, MCK_HPR, MCK_HPR }, },
14436 { 3686 /* vselvs */, ARM::VSELVSS, Convert__Reg1_1__Reg1_2__Reg1_3, AMFBS_HasFPARMv8, { MCK__DOT_f32, MCK_HPR, MCK_HPR, MCK_HPR }, },
14436 { 3686 /* vselvs */, ARM::VSELVSS, Convert__Reg1_1__Reg1_2__Reg1_3, AMFBS_HasFPARMv8, { MCK__DOT_f32, MCK_HPR, MCK_HPR, MCK_HPR }, },
14436 { 3686 /* vselvs */, ARM::VSELVSS, Convert__Reg1_1__Reg1_2__Reg1_3, AMFBS_HasFPARMv8, { MCK__DOT_f32, MCK_HPR, MCK_HPR, MCK_HPR }, },
14438 { 3686 /* vselvs */, ARM::VSELVSH, Convert__Reg1_1__Reg1_2__Reg1_3, AMFBS_HasFullFP16, { MCK__DOT_f16, MCK_HPR, MCK_HPR, MCK_HPR }, },
14438 { 3686 /* vselvs */, ARM::VSELVSH, Convert__Reg1_1__Reg1_2__Reg1_3, AMFBS_HasFullFP16, { MCK__DOT_f16, MCK_HPR, MCK_HPR, MCK_HPR }, },
14438 { 3686 /* vselvs */, ARM::VSELVSH, Convert__Reg1_1__Reg1_2__Reg1_3, AMFBS_HasFullFP16, { MCK__DOT_f16, MCK_HPR, MCK_HPR, MCK_HPR }, },
14593 { 3754 /* vsqrt */, ARM::VSQRTS, Convert__Reg1_1__Reg1_2__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK_HPR, MCK_HPR }, },
14593 { 3754 /* vsqrt */, ARM::VSQRTS, Convert__Reg1_1__Reg1_2__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK_HPR, MCK_HPR }, },
14594 { 3754 /* vsqrt */, ARM::VSQRTS, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK__DOT_f32, MCK_HPR, MCK_HPR }, },
14594 { 3754 /* vsqrt */, ARM::VSQRTS, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK__DOT_f32, MCK_HPR, MCK_HPR }, },
14596 { 3754 /* vsqrt */, ARM::VSQRTH, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_HPR, MCK_HPR }, },
14596 { 3754 /* vsqrt */, ARM::VSQRTH, Convert__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_HPR, MCK_HPR }, },
14892 { 3840 /* vstr */, ARM::VSTRS, Convert__Reg1_1__AddrMode52_2__CondCode2_0, AMFBS_HasFPRegs, { MCK_CondCode, MCK_HPR, MCK_AddrMode5 }, },
14893 { 3840 /* vstr */, ARM::VSTRH, Convert__Reg1_2__AddrMode5FP162_3__CondCode2_0, AMFBS_HasFPRegs16, { MCK_CondCode, MCK__DOT_16, MCK_HPR, MCK_AddrMode5FP16 }, },
14894 { 3840 /* vstr */, ARM::VSTRS, Convert__Reg1_2__AddrMode52_3__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK__DOT_32, MCK_HPR, MCK_AddrMode5 }, },
14943 { 3869 /* vsub */, ARM::VSUBS, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK__DOT_f32, MCK_HPR, MCK_HPR }, },
14943 { 3869 /* vsub */, ARM::VSUBS, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK__DOT_f32, MCK_HPR, MCK_HPR }, },
14955 { 3869 /* vsub */, ARM::VSUBH, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_HPR, MCK_HPR }, },
14955 { 3869 /* vsub */, ARM::VSUBH, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_HPR, MCK_HPR }, },
14958 { 3869 /* vsub */, ARM::VSUBS, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK__DOT_f32, MCK_HPR, MCK_HPR, MCK_HPR }, },
14958 { 3869 /* vsub */, ARM::VSUBS, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK__DOT_f32, MCK_HPR, MCK_HPR, MCK_HPR }, },
14958 { 3869 /* vsub */, ARM::VSUBS, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasVFP2, { MCK_CondCode, MCK__DOT_f32, MCK_HPR, MCK_HPR, MCK_HPR }, },
14970 { 3869 /* vsub */, ARM::VSUBH, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_HPR, MCK_HPR, MCK_HPR }, },
14970 { 3869 /* vsub */, ARM::VSUBH, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_HPR, MCK_HPR, MCK_HPR }, },
14970 { 3869 /* vsub */, ARM::VSUBH, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasFullFP16, { MCK_CondCode, MCK__DOT_f16, MCK_HPR, MCK_HPR, MCK_HPR }, },