reference, declaration → definition definition → references, declarations, derived classes, virtual overrides reference to multiple definitions → definitions unreferenced |
6112 case MCK_GPRwithZR: 6427 case MCK_GPRwithZR: return true; 6471 case MCK_GPRwithZR: return true; 6482 case MCK_GPRwithZR: return true; 6512 case MCK_GPRwithZR: return true; 6530 case MCK_GPRwithZR: return true; 6546 case MCK_GPRwithZR: return true; 6609 case MCK_GPRwithZR: return true; 6709 case MCK_GPRwithZR: return true; 6724 case MCK_GPRwithZR: return true; 6739 case MCK_GPRwithZR: return true; 6755 case MCK_GPRwithZR: return true; 6886 case MCK_GPRwithZR: return true; 6900 case MCK_GPRwithZR: return true; 6978 case MCK_GPRwithZR: return true; 6988 case MCK_GPRwithZR: return true; 7184 case MCK_GPRwithZR: return true; 7196 case MCK_GPRwithZR: return true; 7260 case MCK_GPRwithZR: return true; 7295 case MCK_GPRwithZR: return true; 7299 return B == MCK_GPRwithZR; 9510 case MCK_GPRwithZR: return "MCK_GPRwithZR"; 12117 { 2158 /* vcmp */, ARM::MVE_VCMPs16r, Convert__imm_95_0__Reg1_3__Reg1_4__CondCodeRestrictedS1_2__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s16, MCK_CondCodeRestrictedS, MCK_MQPR, MCK_GPRwithZR }, }, 12119 { 2158 /* vcmp */, ARM::MVE_VCMPs32r, Convert__imm_95_0__Reg1_3__Reg1_4__CondCodeRestrictedS1_2__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_CondCodeRestrictedS, MCK_MQPR, MCK_GPRwithZR }, }, 12121 { 2158 /* vcmp */, ARM::MVE_VCMPs8r, Convert__imm_95_0__Reg1_3__Reg1_4__CondCodeRestrictedS1_2__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s8, MCK_CondCodeRestrictedS, MCK_MQPR, MCK_GPRwithZR }, }, 12123 { 2158 /* vcmp */, ARM::MVE_VCMPu16r, Convert__imm_95_0__Reg1_3__Reg1_4__CondCodeRestrictedU1_2__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u16, MCK_CondCodeRestrictedU, MCK_MQPR, MCK_GPRwithZR }, }, 12125 { 2158 /* vcmp */, ARM::MVE_VCMPu32r, Convert__imm_95_0__Reg1_3__Reg1_4__CondCodeRestrictedU1_2__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u32, MCK_CondCodeRestrictedU, MCK_MQPR, MCK_GPRwithZR }, }, 12127 { 2158 /* vcmp */, ARM::MVE_VCMPu8r, Convert__imm_95_0__Reg1_3__Reg1_4__CondCodeRestrictedU1_2__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_u8, MCK_CondCodeRestrictedU, MCK_MQPR, MCK_GPRwithZR }, }, 12129 { 2158 /* vcmp */, ARM::MVE_VCMPf32r, Convert__imm_95_0__Reg1_3__Reg1_4__CondCodeRestrictedFP1_2__VPTPredN2_0, AMFBS_HasMVEFloat, { MCK_VPTPredN, MCK__DOT_f32, MCK_CondCodeRestrictedFP, MCK_MQPR, MCK_GPRwithZR }, }, 12131 { 2158 /* vcmp */, ARM::MVE_VCMPi16r, Convert__imm_95_0__Reg1_3__Reg1_4__CondCodeRestrictedI1_2__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_i16, MCK_CondCodeRestrictedI, MCK_MQPR, MCK_GPRwithZR }, }, 12133 { 2158 /* vcmp */, ARM::MVE_VCMPi32r, Convert__imm_95_0__Reg1_3__Reg1_4__CondCodeRestrictedI1_2__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_i32, MCK_CondCodeRestrictedI, MCK_MQPR, MCK_GPRwithZR }, }, 12135 { 2158 /* vcmp */, ARM::MVE_VCMPi8r, Convert__imm_95_0__Reg1_3__Reg1_4__CondCodeRestrictedI1_2__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_i8, MCK_CondCodeRestrictedI, MCK_MQPR, MCK_GPRwithZR }, }, 12137 { 2158 /* vcmp */, ARM::MVE_VCMPf16r, Convert__imm_95_0__Reg1_3__Reg1_4__CondCodeRestrictedFP1_2__VPTPredN2_0, AMFBS_HasMVEFloat, { MCK_VPTPredN, MCK__DOT_f16, MCK_CondCodeRestrictedFP, MCK_MQPR, MCK_GPRwithZR }, }, 13645 { 2963 /* vpt */, ARM::MVE_VPTv8s16r, Convert__ITMask1_0__Reg1_3__Reg1_4__CondCodeRestrictedS1_2, AMFBS_HasMVEInt, { MCK_ITMask, MCK__DOT_s16, MCK_CondCodeRestrictedS, MCK_MQPR, MCK_GPRwithZR }, }, 13647 { 2963 /* vpt */, ARM::MVE_VPTv4s32r, Convert__ITMask1_0__Reg1_3__Reg1_4__CondCodeRestrictedS1_2, AMFBS_HasMVEInt, { MCK_ITMask, MCK__DOT_s32, MCK_CondCodeRestrictedS, MCK_MQPR, MCK_GPRwithZR }, }, 13649 { 2963 /* vpt */, ARM::MVE_VPTv16s8r, Convert__ITMask1_0__Reg1_3__Reg1_4__CondCodeRestrictedS1_2, AMFBS_HasMVEInt, { MCK_ITMask, MCK__DOT_s8, MCK_CondCodeRestrictedS, MCK_MQPR, MCK_GPRwithZR }, }, 13651 { 2963 /* vpt */, ARM::MVE_VPTv8u16r, Convert__ITMask1_0__Reg1_3__Reg1_4__CondCodeRestrictedU1_2, AMFBS_HasMVEInt, { MCK_ITMask, MCK__DOT_u16, MCK_CondCodeRestrictedU, MCK_MQPR, MCK_GPRwithZR }, }, 13653 { 2963 /* vpt */, ARM::MVE_VPTv4u32r, Convert__ITMask1_0__Reg1_3__Reg1_4__CondCodeRestrictedU1_2, AMFBS_HasMVEInt, { MCK_ITMask, MCK__DOT_u32, MCK_CondCodeRestrictedU, MCK_MQPR, MCK_GPRwithZR }, }, 13655 { 2963 /* vpt */, ARM::MVE_VPTv16u8r, Convert__ITMask1_0__Reg1_3__Reg1_4__CondCodeRestrictedU1_2, AMFBS_HasMVEInt, { MCK_ITMask, MCK__DOT_u8, MCK_CondCodeRestrictedU, MCK_MQPR, MCK_GPRwithZR }, }, 13657 { 2963 /* vpt */, ARM::MVE_VPTv4f32r, Convert__ITMask1_0__Reg1_3__Reg1_4__CondCodeRestrictedFP1_2, AMFBS_HasMVEFloat, { MCK_ITMask, MCK__DOT_f32, MCK_CondCodeRestrictedFP, MCK_MQPR, MCK_GPRwithZR }, }, 13659 { 2963 /* vpt */, ARM::MVE_VPTv8i16r, Convert__ITMask1_0__Reg1_3__Reg1_4__CondCodeRestrictedI1_2, AMFBS_HasMVEInt, { MCK_ITMask, MCK__DOT_i16, MCK_CondCodeRestrictedI, MCK_MQPR, MCK_GPRwithZR }, }, 13661 { 2963 /* vpt */, ARM::MVE_VPTv4i32r, Convert__ITMask1_0__Reg1_3__Reg1_4__CondCodeRestrictedI1_2, AMFBS_HasMVEInt, { MCK_ITMask, MCK__DOT_i32, MCK_CondCodeRestrictedI, MCK_MQPR, MCK_GPRwithZR }, }, 13663 { 2963 /* vpt */, ARM::MVE_VPTv16i8r, Convert__ITMask1_0__Reg1_3__Reg1_4__CondCodeRestrictedI1_2, AMFBS_HasMVEInt, { MCK_ITMask, MCK__DOT_i8, MCK_CondCodeRestrictedI, MCK_MQPR, MCK_GPRwithZR }, }, 13665 { 2963 /* vpt */, ARM::MVE_VPTv8f16r, Convert__ITMask1_0__Reg1_3__Reg1_4__CondCodeRestrictedFP1_2, AMFBS_HasMVEFloat, { MCK_ITMask, MCK__DOT_f16, MCK_CondCodeRestrictedFP, MCK_MQPR, MCK_GPRwithZR }, },