reference, declaration → definition definition → references, declarations, derived classes, virtual overrides reference to multiple definitions → definitions unreferenced |
8877 case MCK_CondCodeRestrictedS: { 9723 case MCK_CondCodeRestrictedS: return "MCK_CondCodeRestrictedS"; 12116 { 2158 /* vcmp */, ARM::MVE_VCMPs16, Convert__imm_95_0__Reg1_3__Reg1_4__CondCodeRestrictedS1_2__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s16, MCK_CondCodeRestrictedS, MCK_MQPR, MCK_MQPR }, }, 12117 { 2158 /* vcmp */, ARM::MVE_VCMPs16r, Convert__imm_95_0__Reg1_3__Reg1_4__CondCodeRestrictedS1_2__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s16, MCK_CondCodeRestrictedS, MCK_MQPR, MCK_GPRwithZR }, }, 12118 { 2158 /* vcmp */, ARM::MVE_VCMPs32, Convert__imm_95_0__Reg1_3__Reg1_4__CondCodeRestrictedS1_2__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_CondCodeRestrictedS, MCK_MQPR, MCK_MQPR }, }, 12119 { 2158 /* vcmp */, ARM::MVE_VCMPs32r, Convert__imm_95_0__Reg1_3__Reg1_4__CondCodeRestrictedS1_2__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s32, MCK_CondCodeRestrictedS, MCK_MQPR, MCK_GPRwithZR }, }, 12120 { 2158 /* vcmp */, ARM::MVE_VCMPs8, Convert__imm_95_0__Reg1_3__Reg1_4__CondCodeRestrictedS1_2__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s8, MCK_CondCodeRestrictedS, MCK_MQPR, MCK_MQPR }, }, 12121 { 2158 /* vcmp */, ARM::MVE_VCMPs8r, Convert__imm_95_0__Reg1_3__Reg1_4__CondCodeRestrictedS1_2__VPTPredN2_0, AMFBS_HasMVEInt, { MCK_VPTPredN, MCK__DOT_s8, MCK_CondCodeRestrictedS, MCK_MQPR, MCK_GPRwithZR }, }, 13644 { 2963 /* vpt */, ARM::MVE_VPTv8s16, Convert__ITMask1_0__Reg1_3__Reg1_4__CondCodeRestrictedS1_2, AMFBS_HasMVEInt, { MCK_ITMask, MCK__DOT_s16, MCK_CondCodeRestrictedS, MCK_MQPR, MCK_MQPR }, }, 13645 { 2963 /* vpt */, ARM::MVE_VPTv8s16r, Convert__ITMask1_0__Reg1_3__Reg1_4__CondCodeRestrictedS1_2, AMFBS_HasMVEInt, { MCK_ITMask, MCK__DOT_s16, MCK_CondCodeRestrictedS, MCK_MQPR, MCK_GPRwithZR }, }, 13646 { 2963 /* vpt */, ARM::MVE_VPTv4s32, Convert__ITMask1_0__Reg1_3__Reg1_4__CondCodeRestrictedS1_2, AMFBS_HasMVEInt, { MCK_ITMask, MCK__DOT_s32, MCK_CondCodeRestrictedS, MCK_MQPR, MCK_MQPR }, }, 13647 { 2963 /* vpt */, ARM::MVE_VPTv4s32r, Convert__ITMask1_0__Reg1_3__Reg1_4__CondCodeRestrictedS1_2, AMFBS_HasMVEInt, { MCK_ITMask, MCK__DOT_s32, MCK_CondCodeRestrictedS, MCK_MQPR, MCK_GPRwithZR }, }, 13648 { 2963 /* vpt */, ARM::MVE_VPTv16s8, Convert__ITMask1_0__Reg1_3__Reg1_4__CondCodeRestrictedS1_2, AMFBS_HasMVEInt, { MCK_ITMask, MCK__DOT_s8, MCK_CondCodeRestrictedS, MCK_MQPR, MCK_MQPR }, }, 13649 { 2963 /* vpt */, ARM::MVE_VPTv16s8r, Convert__ITMask1_0__Reg1_3__Reg1_4__CondCodeRestrictedS1_2, AMFBS_HasMVEInt, { MCK_ITMask, MCK__DOT_s8, MCK_CondCodeRestrictedS, MCK_MQPR, MCK_GPRwithZR }, }, 15672 { 2158 /* vcmp */, 4 /* 2 */, MCK_CondCodeRestrictedS, AMFBS_HasMVEInt }, 15673 { 2158 /* vcmp */, 4 /* 2 */, MCK_CondCodeRestrictedS, AMFBS_HasMVEInt }, 15674 { 2158 /* vcmp */, 4 /* 2 */, MCK_CondCodeRestrictedS, AMFBS_HasMVEInt }, 15675 { 2158 /* vcmp */, 4 /* 2 */, MCK_CondCodeRestrictedS, AMFBS_HasMVEInt }, 15676 { 2158 /* vcmp */, 4 /* 2 */, MCK_CondCodeRestrictedS, AMFBS_HasMVEInt }, 15677 { 2158 /* vcmp */, 4 /* 2 */, MCK_CondCodeRestrictedS, AMFBS_HasMVEInt }, 15973 { 2963 /* vpt */, 4 /* 2 */, MCK_CondCodeRestrictedS, AMFBS_HasMVEInt }, 15974 { 2963 /* vpt */, 4 /* 2 */, MCK_CondCodeRestrictedS, AMFBS_HasMVEInt }, 15975 { 2963 /* vpt */, 4 /* 2 */, MCK_CondCodeRestrictedS, AMFBS_HasMVEInt }, 15976 { 2963 /* vpt */, 4 /* 2 */, MCK_CondCodeRestrictedS, AMFBS_HasMVEInt }, 15977 { 2963 /* vpt */, 4 /* 2 */, MCK_CondCodeRestrictedS, AMFBS_HasMVEInt }, 15978 { 2963 /* vpt */, 4 /* 2 */, MCK_CondCodeRestrictedS, AMFBS_HasMVEInt }, 16329 case MCK_CondCodeRestrictedS: